Analog & Digital VLSI

Design
EEE/ INSTR F313
BITS Pilani ANU GUPTA
Pilani Campus EEE
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Digital VLSI Design

Concepts

• Boolean Algebra, and minimization

• Gates, Combinational networks

• Logic design with PLD

• FLIP FLOPS, counters

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Concepts

• Synchronous sequential networks-mealy / moore

machine, state table and its reduction

• ASM- design using ASM chart, state assignment, ASM

tables, ASM realizations

• Asynchronous sequential network-analysis, primitive flow

table and its reduction, races, hazards

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Digital VLSI Design

Current Digital VLSI Design

• Full Automation
• Maximum benefit of scaling
• High speed
• low power
• Robustness

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Design metrics
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Long channel MOSFET

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MOSFET as switch in digital design.

Good Switch behavior
• In digital logic (CMOS inverter), MOSFET is used as
switch..
• NMOS/ PMOS should switch off without any current below
Vto.
• But the current reduces gradually below Vto.

• To measure fast turn off ability, a parameter subthreshold

slope(S) is calculated
• S must be large for fast turn off ability of MOSFET.

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Design of CMOS inverter

for long channel MOSFET s
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INVERTER

STATIC CHARACTERISTICS
Ideal inverter voltage transfer
characteristics (VTC)

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VTC-- Design Issues

• Less Static Power Consumption

• Get Full Logic Levels

• Obtain Sharp Transition

• Switching Threshold→ Noise Margins max.

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Practical VTC

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Five Critical Voltages

VOH  Max. output voltage when output is logic “1”

VOL  Min. output voltage when output is logic “0”

VIL  Max. input voltage which can be interpreted as

logic “0”

VIH  Min. input voltage which can be interpreted as

logic “1”
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SWITCHING THRESHOLD

• Vth= VM= Vinv

• Output changes its Logic

state
Noise margins and Noise
immunity

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BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Noise Margins

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How much Noise margins are
sufficient?

Question---how much Vdd to guarantee Noise

immunity ????

Noise margin are governed by Vdd

Answer---- How much noise margin is required

depends on the value of total noise generated in
a system.?
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Noise margin vs. noise
immunity.

If value of total noise generated in a system is high,

large noise margins will be required that
necessitates a high Vdd.

So, working at low values of Vdd will not give noise

immunity to a system. Else noise reduction
techniques to be used aggressively in design.

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System Noise modelling

System Noise ( Vn) modelling equation ---

𝑉𝑁 = 𝑉𝑁𝐼 + 𝐾𝑁 ∆𝑉;

𝑤ℎ𝑒𝑟𝑒 𝑠𝑖𝑔𝑛𝑎𝑙 𝑠𝑤𝑖𝑛𝑔 ∆𝑉=𝑉𝑑𝑑

𝑉𝑑𝑑 𝑉𝑑𝑑
Ideal noise margins ≤ ; so 𝑉𝑁 =
2 2

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What is Kn?
Cross Talk ( swing dependent noise source) - Coupling between Lines

Cross talk from a driven line, A, to a

static line, B:
Any incremental voltage waveform
on A will appear on B attenuated
by the capacitive voltage divider

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Kn
Example--Cross talk phenomena

keeper MOSFET to maintain logic ‘1’ at B

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Noise immunity –
Noise modelling

Binary signaling----

Required swing

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Example---
How much Vdd for required noise margin?

Binary signaling----

Required swing

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Noise immunity vs. noise
margin

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Implementation
Resistive load inverter
Reference: Kang. S.M and Leblebici Y., “CMOS
Digital Integrated Circuits: Analysis and Design,

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VOH

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Operating region of NMOS

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VOL

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VIH
VIL

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Switching threshold
VM
VM– defined at a point Vin= Vout= VM
Hence NMOS operates in saturation region
Using condition I pu=I pd
𝑉𝑑𝑑 − 𝑉𝑚 1 𝑊 2
= 𝜇𝑛 𝐶𝑜𝑥 𝑉𝑀 − 𝑉𝑡𝑜,𝑛
𝑅𝐿 2 𝐿
𝑾
Put 𝝁𝒏 𝑪𝒐𝒙 = 𝒌𝒏
𝑳
2 𝑉𝑑𝑑 − 𝑉𝑚
= 𝑉𝑀 2 + 𝑉𝑡𝑜,𝑛 2 − 2𝑉𝑀 𝑉𝑡𝑜,𝑛
𝒌𝒏 𝑅𝐿

2 𝟏 2 𝟐𝑉𝑑𝑑
𝑉𝑀 − 2𝑉𝑀 𝑉𝑡𝑜,𝑛 − + 𝑉𝑡𝑜,𝑛 − =0
𝒌𝒏 𝑅𝐿 𝒌𝒏 𝑅𝐿

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 2 𝟏 2 𝟐𝑉𝑑𝑑
𝑉𝑀 − 2𝑉𝑀 𝑉𝑡𝑜,𝑛 − + 𝑉𝑡𝑜,𝑛 − =0
𝒌𝒏 𝑅𝐿 𝒌𝒏 𝑅𝐿
Design for Vol
Sat. Enhancement Load Inv.
Lin. Enhancement Load Inv.
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CMOS Inverter
CMOS INVERTER

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Static characteristics

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Operating regions
VOH
VOL
VIL
VIH
V inv=V th = VM --- switching/ logic threshold
Long channel MOSFET-- VM

𝑘𝑛
𝑘𝑅 =
𝑘𝑝
Long channel MOSFET VM
Long channel MOSFET VM
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Slow/ Fast MOSFET

Bad NMOS/ good NMOS
Variation in VM by (W/L)

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Impact Of Device Variations on Vm
Effect on kR= unCox[W/L]n / upCox[W/L]p
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Impact of reducing Vdd on VTC

Impact of reducing Vdd on
VTC
Vdd ≥ Vtn + │Vtp│

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Reducing supply voltage
Hysteresis behavior
• If the power supply voltage is reduced below the
sum of the two threshold –

• The VTC will contain a region in which none of

the transistors is conducting

• The output voltage level is determine by

previous state of the output

• The VTC exhibits a hysteresis behavior

Hysteresis behavior
 Vdd < Vtn + │Vtp│

Both
transistors
off
Choose appropriate VM, but it serves
only either high or low signal noise
Cmos inverter hysteresis
So, need Vm+, Vm- voltages
Can we use hysteresis
behavior of cmos inverter???
• Yes, (but new vdd to be generated)
• Can generate a clean signal
Problem---- no control on design of Vm+, Vm- voltages

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Schmitt trigger
Design for Vm(+/-) voltage
Removes spurious transitions
CMOS BUFFER

SCHMITT TRIGGER
Schmitt trigger circuit (inverting
type) design for glitch removal

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Design
Vm+

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Design
Vm-

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CMOS BUFFER

SCHMITT TRIGGER
CMOS Schmitt trigger ckt (non inverting type)
used to improve signal slope and noise margins
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Symmetric CMOS inverter

Which voltage is critical in
CMOS inverter?
None
• So design for widest noise margin, NML /
NMH

OR
• Design For VM

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Critical Voltage

We can design for wide noise

margins

Set Vth= ½Vdd

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Deviations
In symmetric cmos inverter

What if Vton ≠ |Vtop|??

Then for Ip= In;

𝑊
𝐿 𝑛 𝜇𝑝
≠
𝑊 𝜇𝑛
𝐿 𝑝

Hence, 𝑵𝑴𝑯 ≠ 𝑵𝑴𝑳

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Choose appropriate VM+, Vm-
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Static CMOS gate logic

Static CMOS Logic Design
Full Static CMOS or complementary CMOS logic

RATIOLESS LOGIC

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2 input NAND/ NOR

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Sizing
NAND gate, Equivalent inverter approach

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Sizing
NOR gate, equivalent inverter approach

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Full Static CMOS gate
VTC--Input data dependent
2 input XOR/ XNOR
DRAWBACK
complementary signals are required

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3 input XOR

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Removing redundant paths
Transistor count reduced by 4 transistors

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OAI/ AOI gates
Compound gate

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And Or Invert (AOI) gate
AOI22

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AOI22
CMOS implementation

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Static CMOS
Compound gate

𝐹 = 𝐴. 𝐷 + 𝐸 ) + (𝐵. 𝐶)

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Design of CMOS inverter

With short channel MOSFET s
THE SHORT CHANNEL
MOSFET

Operating condition --L≥ xd1+xd2

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Short channel MOSFET-
DIBL/ Punchthrough

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 Punch through
• This continue until the VDS reaches value that deplete the
whole remaining neutral substrate region where the two space
charge region almost touch each other.
• As the voltage is increased further the drain space charge
region expands while the space charge region of the source
junction contracts
• This means that its internal electric field decreases which
means that the source junction becomes appreciable forward
biased
• So, the net barrier height at the source is appreciably
decrease which enables electrons to flow with large number
from source to drain.
• This is the punch through current signifying the onset of punch
through breakdown.
• Long-channel MOSFET is defined as devices with width and
length long enough so that edge effects from the four sides
can be neglected
• Short channel MOSFET is defined as devices with width and
length short enough such that the edge effects can not be
neglected.
• Channel length L is comparable to the depletion widths
associated with the drain and source, or , channel depletion
width in channel region before inversion layer appears..
• But Channel length L must be greater than the sum of the
drain and source depletion widths to get operational
MOSFET

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Velocity saturated device

Extended sat. region operation
Drain current equation:
long channel/ short channel

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Short channel MOS current equation
saturates before (Vgs-Vt) due to carrier
velocity saturation

This model is first order and empirical

DIFFERENCE
Long Channel Vs. Short Channel

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Long Channel Vs. Short Channel
SAME
Long Channel Vs. Short Channel
Id vs Vgs
Extended sat. region operation

NMOS

PMOS

vsat= 105 m/sec, VDSATn= 0.63V, VDSATp= -1 V

Switching threshold, Vm—
short channel CMOS Inv.

  pVDSATp 
 p cox 
w
  VDSATp W p ox 
c  

 l p  l p W p coxvSAT
r   
 V
 n cox 
w  Wn coxvSAT
  VDSATn Wn cox  n DSATn 
 l n  l n
VM-- For velocity saturated device-inverter
Finding VIL, VIH
Using Piece wise linear approx.
Gain of CMOS inverter
Inverter gain
Gain of CMOS inverter
Alternative way

Drift velocity, Vde= µVdsat/ L = 105 m/sec

gds (in saturation) is dominated by channel length

modulation. Va is early voltage

1 I D sat
 g ds  Early Voltage, Va = 7 V / um
ro LVa
Noise Margins
Short channel MOSFET--Estimation of NM USING
Piecewise lin. approx.
Determine gain (g) at Vin~Vm
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End