Siemens Digital Industries Software
SystemVerilog
constraints: appreciating
what you forgot in school
to get better results
Executive summary
This paper looks at two of the most common issues when constraint solver
results do not match your intent: not understanding how Verilog expres-
sion evaluation rules apply to interpret the rules of basic algebra and not
understanding the affect probability has on choosing solution values.
Coding recommendations for improving your code to get better results
are provided.
Dave Rich
siemens.com/eda
White paper | SystemVerilog constraints: appreciating what you forgot in school to get better results
Abstract
Constrained random verification (CRV) addresses the until much later in the process; perhaps after you check
time-consuming task of writing individual di-rected tests your functional coverage reports.
for complex systems. We sometimes say that CRV auto-
This paper looks at two of the most common issues
mates writing tests for quickly producing the test cases
when constraint solver results do not match your intent:
you can think of, or hitting the corner cases you didn’t.
1) not understanding how Verilog expression evaluation
But the reality is, like with any computer programming rules apply to interpret the rules of basic algebra, and 2)
language, your code executes exactly the way it is writ- not under-standing the affect probability has on choos-
ten, and has no concern for what you were thinking. In ing solution values. These are subjects you may have
particular when coding constraints, this manifests as learned (or slept through) in school long ago and need
results that satisfy the constraints, but may not match refreshing. This paper presents a background defining
what you intend. Crashes or conflicting constraint fail- how SystemVerilog con-straints work, and how these
ures are usually easier to resolve because of their abrupt issues play into getting unwanted results. Also, it offers
termination. However, without an abrupt termination, a few coding recommendations for improving your code
you may not notice anything wrong with the results to get better results along the way.
Introduction
In its simplest form, a constraint is nothing more than a constraint. That is 16 possible value combinations for X
Boolean expression with random variables where the and Y with only 6 valid solutions We could break this
solver is asked to find values that make the expression down into individual dependent steps shown in figure 2.
true. One simplistic way of thinking how a constraint
solver works is that it repeatedly tries different values bit [1:0] X; // 0, 1, 2, 3 bit [1:0] Y;
for the random variables until finding values making the do begin
expression true. Then those values are left as the result X = $urandom;
for the random variables. It’s actually much more com- Y = $urandom;
plicated because we want the solver to quickly converge end while (! (X<Y) );
on a solution or tell us no solution is possible without
wasting a lot of CPU resources. To understand this Figure 1: Brute force randomization.
better, it helps to look at how one might go about solv-
ing constraints without a constraint solver. Assume we begin
have two random variables X and Y that need to have X = $urandom_range(0,2);
the constraint X < Y. The code might look like what we
Y = $urandom_range(X+1,3);
have in figure 1.
end
This loop iterates an average of 16/6 times before finding
a set of values for the X and Y variables that satisfy the Figure 2: Constraint dependencies.
Siemens Digital Industries Software 2
White paper | SystemVerilog constraints: appreciating what you forgot in school to get better results
But this rapidly gets complex with the addition of other class A;
constraints, like X[0] != Y[0]. Constraint solvers take all X Y
rand bit [1:0] X;
constraint expressions at once, figure out all the depen- rand bit [1:0] Y; constraint C1 { X < Y;}
0 1
dencies and come up with solution sets for all random 0 2
endclass : A
variables at once. In SystemVerilog, we would write this 0 3
as a class and the constraint solver would formally 1 2
deduce that there are six possible solutions as listed in 1 2
figure 3. 2 3
Figure 3: SystemVerilog Class with random variables.
Verilog expressions
A fundamental principle that drove SystemVerilog’s
bit [2:0] A = 4; // 3 bits
development was the unification of language semantics
bit [3:0] B = 14; // 4 bits
so that rules for expression evaluation were identical
int C = 1;
across all facets of the language. This meant all of the
bit [3:0] D = 8; // 4 bits
old idiosyncrasies from Verilog’s weak type and expres-
sion evaluation rules got absorbed into SystemVerilog’s if( A + B >> C < D )...
new constraint expressions.
Figure 4: Steps in evaluating an expression.
One of the unique things that distinguishes the Verilog
Hardware Description Language (HDL) from most other The first step when evaluating an expression is figuring
soft-ware programming languages is its ability to out the order of operators in the form of precedence
declare variables of different bit-widths and have rules. When we see
expressions of mixed bit-width operands, whereas most ( A + B >> C < D)
other programming languages only consider of byte or
precedence rules group the operators as
word sized operands. But most hardware engineers are
not trained in software development and tend to favor ((A + B) >> C < D)
many implicit rules and weak type systems. These rules
The next step is context determination. This tells us
mean many expressions silently truncate or pads to
which operands within an expression influence the
different bit widths without any notice of overflow or
implicit casting of other operands. Expressions are either
underflow. This type system radically different from
self-determined, meaning they do not have outside
another rival language, VHSIC-HDL (VHDL) which has an
influences, or they are context-determined when some
extremely strong type system.
outside part of the expression has influence over it.
Since Verilog is used for synthesis into hardware, it does Context affects the resulting types when mixing differ-
need precise definitions for generation of hardware ent bit-widths, signed and unsigned types and real and
without ambiguity or creating unnecessary extra logic. integer types. The language reference manual (LRM)
In addition to syntax, there are many transformational specifies these steps in a number of tables which have
steps Verilog needs to follow when evaluating an been consolidated into one in figure 5 for this example.
expression. Suppose we had the code in figure 4.
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White paper | SystemVerilog constraints: appreciating what you forgot in school to get better results
According to these rules, we recognize that operands A, the overflow truncation. It is not 5’d18 as most would
B and D from figure 4 get sized to the maximum length, expect. That makes the overall result of 4’d2 < 4’d8 to be
4 bits – so A gets padded with one 0 bit. The size of C is true, 1’b1. To make the expression deal with the over-
self-determined and has no influence on the rest of the flow, some operand or sub-expression must be cast to 5
expres-sion. The result of 4’d4 + 4’d14 is 4’d2 because of bits (e.g. 5’(A + B) >> C < D ).
Operators i op j i op j result length Context Precedence
+- Max(Length(i),Length(j)) Operands get sized to max before operation Higher
<< >> Length(i) j is self-determined
< <= > >= 1 bit Operands get sized to max before operation
{} L(i)+L(J) All operands are self-determined Lower
Figure 5: Context and bit-length determination.
Constraint expressions
Now let’s take a look at the same expression used in a class tx;
random constraint expression. For simplicity of the code rand bit [2:0] A;
in figure 6, only the variables A and B are declared rand.
rand bit [3:0] B;
Variables C and D are converted into literal constants.
constraint C1{ A + B >> 32’d1 < 4’d8; }
As we saw in the previous section, 4 and 14 are per- endclass : tx
fectly valid values for A and B that make the expression
result true, satisfying the constraint. The constraint Figure 6: Class constraint.
must be written to deal with overflow properly by cast-
ing to the appro-priate width to handle the overflow. constraint c { A + B >> 32’d1 < 5’d8; }
Any one of the casts shown in figure 7 handle the over- constraint c { int’(A + B) >> 32’d1 < 4’d8; }
flow properly giving us the solutions we expect. constraint c { 5’(A) + B >> 32’d1 < 4’d8; }
Another common mistake arises when using the array
Figure 7: Possible corrections.
reduction methods, like sum(). These methods get
expanded to iterate over each element in an unpacked The concatenation operator serves to show the result is
array. But the problem is that by default the result is the self-determined (review the table in figure 5), and only
same bit-width as each element type. If you have 1-bit wide since each array element is only 1-bit wide. The
rand bit bits[6]; reduction methods have an in-line extension capability
constraint c {bits.sum() == 3; } using the with() clause allowing you to substitute a differ-
ent expression for each element. By casting each element
The built-in sum method gets expanded to to a larger width, the result no longer overflows.
(bits[0]+bits[1]+bits[2]+bits[3]+bits[4]+bits[5]) } == 3 constraint c {bits.sum() with (int’(item)) == 3; }
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White paper | SystemVerilog constraints: appreciating what you forgot in school to get better results
Signed expressions
A signed operand only affects how that operand gets But the most common mistakes when using signed
padded to a larger width (sign extension) or its magni- operands is forgetting that they could have negative
tude for the comparison of relational operators. It has values and that comparing signed to unsigned operands
no effect on how the value is stored or truncated. One becomes all unsigned. In figure 9, -1 is a valid value that
of the most confusing rules when mixing signed and could be chosen for max_address.
unsigned operands is that all operands in the context
must be signed for the result to be signed, and that rand int max_address;
introduction of an unsigned type halts propagation of rand bit [11:0] address;
sign extension. constraint c { max_address < 10;
address < max_address; }
bit signed [2:0] A = -1;
bit [3:0] B = 14;
Figure 9: Allows negative values.
A + B < 14
Figure 8: Mixing signed and unsigned operands. But in the relational comparison to the unsigned
address that value would become an unsigned positive
In figure 8, even though A and B both get extended to 32’hFFFFFFFF resulting in unexpected large values for
32 bits before the addition (From the LRM, literals (14) address. It is always safer to use an explicit range using
are implicitly a 32-bit signed operands), A does not get the inside operator as shown in figure 10.
sign extended. This is because B is unsigned, and the
rand int max_address;
rest of the expression is treated as unsigned. A becomes
32’d7 and the result of the expression becomes 32’d21 < rand bit [11:0] address;
32’d14, which is a false 1’b0. The need for mixing signed constraint c { max_address inside {[0:10]};
and unsigned operands is rare. Try to use all one type or address < max_address; }
the other, or make sure you cast the unsigned operands
to signed (signed’(B)). Figure 10: Bounded range constraint.
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White paper | SystemVerilog constraints: appreciating what you forgot in school to get better results
Probabilities and statistics
Going back to figure 3 with the constraint X<Y, we saw It is not possible with most constraints to get uniform
that there are six solutions the constraint solver can value distributions for all random variables unless their
choose from. Although each solution has an even prob- solution spaces are independent of each other. For a
ability of being chosen, the probability of a particular small solution set like the one generated for figure 12
value being chosen for a random variable is uneven. this might not be an issue, but for larger solution sets,
The table in figure 11 shows the probabilities of the getting particular values becomes much harder. The
three possible values available to be chosen for Y and Y. seemingly simple example
Y==3 X==2 or 1 or 0 3/6 = 50% class A;
Y==2 X==1 or 0 2/6 = 33% rand bit ctrl;
Y==1 X==0 1/6 = 16% rand bit [31:0] data;
constraint C0 {ctrl -> data == 0;}
X==0 Y==3 or 2 or 1 3/6 = 50%
endclass : A
X==1 Y==3 or 2 2/6 = 33%
X==2 Y==3 1/6 = 16% Figure 13: Unobtainable solutions.
Figure 11: Probability of selecting a value. shown in figure 13 has 232+1 (~4 billion) possible solu-
tions. But only 1 in 232 solutions allows ctrl to have the
We can add a construct that changes the approach to value 1 – practically never! Adding a solve ctrl before
how the solver chooses values. Figure 12 instructs the data construct lets ctrl have a uniform distribution, but
solver to choose a value for X evenly over all the pos- the probability of data==0 is now 50 percent. If we do
sible values for X in the solution set. It does not change not want that to happen, we can add a distribution
the total number of solutions. Now all three value constraint as figure 14 shows.
choices for X will each have a 33 percent chance of
being selected. Realize this affects the probabilities for class A;
the three value choices for Y, which now becomes rand bit ctrl;
slightly harder to calculate.
rand bit [31:0] data;
class A; constraint C0 {ctrl -> data == 0;
rand bit [1:0] X; ctrl dist {1:=10, 0:=90;}
rand bit [1:0] Y; endclass : A
constraint C1 { X < Y; solve X before Y;}
Figure 14: Correcting distribution.
Figure 12: Choose variable value selection order.
Many people expect distributions to come out exactly
The probability of choosing Y==1 is the way they specify. But the probability of getting
exactly the specified distribution is low until you
1 1
― * ― = 11% approach an infinite number of randomizations. If you
3 3 flip a coin 10 times, there is only a 25 percent chance of
getting exactly 5 heads and 5 tails, (105 )/210.
and choosing Y==3 is
1 1 1 1 1 1
― * ― + ― * ― + ― * ― = 61%
3 3 3 2 3 1
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White paper | SystemVerilog constraints: appreciating what you forgot in school to get better results
If you do need a specific distribution in a determinate
typedef enum {HEADS,TAILS} coin_t;
number of randomizations, the randc construct comes
class C;
in handy because it randomly cycles through all possible
values evenly before repeating a value. The example in rand coin_t toss;
figure 15 sets up an exact 50/50 distribution over the randc int scale;
course of 100 randomizations. constraint c {
scale inside {[0:99]};
(scale < 50) -> toss == HEADS;
(scale >=50) -> toss == TA I L S ; }
endclass : C
Figure 15: Fixed distribution.
Conclusion
To summarize, I’ve shown some simple examples of how work preventing you from seeing all the expected valid
Verilog expression evaluation rules affect the solution results. Analyzing these situations requires that you go
space of your SystemVerilog constraints, sometimes back to review your Verilog, Algebra and Statistics text-
giving you unexpected, but valid results. I’ve also shown books to appreciate all the factors involved in producing
examples of getting valid results, but how probabilities solution sets from your constraints.
References
1. The Top Most Common SystemVerilog Constrained Random Gotchas,
Ahmed Yehia, DVCon-Europe 2014.
2. IEEE Standard for SystemVerilog, Unified Hardware Design,
Specification, and Verification Language, IEEE Std 1800-2017.
https://ieeexplore.ieee.org/browse/standards/get-program/page/
series?id=80
3. UVM Random Stability: Don’t leave it to chance, Avidan Efody, DVCon
2012.
4. Verilog and SystemVerilog Gotchas: 101 Common Coding Errors and
How to Avoid Them, Stuart Suther-land and Don Mills, Springer.
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