PCM2704,, PCM2705

PCM2706, PCM2707
Burr-Brown Audio
www.ti.com....................................................................................................................................................... SLES081F – JUNE 2003 – REVISED JANUARY 2009

STEREO AUDIO DAC WITH USB INTERFACE,

SINGLE-ENDED HEADPHONE OUTPUT AND S/PDIF OUTPUT
1 FEATURES – External ROM Interface (PCM2704/6)
• On-Chip USB Interface:
2345 – Serial Programming Interface (PCM2705/7)
– No Need of Dedicated Device Driver – I2S Interface (Selectable on PCM2706/7)
– With Full-Speed Transceivers • Package:
– Fully Compliant With USB 1.1 Specification – 28-Pin SSOP (PCM2704/5)
– Certified by USB-IF – 32-Pin TQFP (PCM2706/7)
– Partially Programmable Descriptors
– Adaptive Isochronous Transfer for APPLICATIONS
Playback • USB Headphones
– Bus-Powered or Self-Powered Operation • USB Audio Speaker
• USB CRT/LCD Monitor
• Sampling Rate: 32, 44.1, 48 kHz
• USB Audio Interface Box
• On-Chip Clock Generator With Single 12-MHz
• USB-Featured Consumer Audio Product
Clock Source
• Single Power Supply: DESCRIPTION
– Bus-Powered: 5 V, Typical (VBUS)
The PCM2704/5/6/7 is TI's single-chip USB stereo
– Self-Powered: 3.3 V, Typical audio DAC with USB-compliant full-speed protocol
• 16-Bit Delta-Sigma Stereo DAC controller and S/PDIF. The USB-protocol controller
– Analog Performance at 5 V (Bus-Powered), works with no software code, but USB descriptors
3.3 V (Self-Powered): can be modified in some parts (for example, vendor
ID/product ID) through the use of an external ROM
– THD+N: 0.006% RL > 10 kΩ, (PCM2704/6), SPI (PCM2705/7), or on request. (1)
Self-Powered The PCM2704/5/6/7 employs SpAct™ architecture,
– THD+N: 0.025% RL = 32 Ω TI's unique system that recovers the audio clock from
– SNR = 98 dB USB packet data. On-chip analog PLLs with SpAct
enable playback with low clock jitter.
– Dynamic Range: 98 dB
– PO = 12 mW, RL = 32 Ω
– Oversampling Digital Filter
– Pass-Band Ripple = ±0.04 dB
– Stop-Band Attenuation = –50 dB
– Single-Ended Voltage Output
– Analog LPF Included
• Multiple Functions:
– Up to Eight Human Interface Device (HID)
Interfaces (Depending on Model and (1) The modification of the USB descriptor through external ROM
Settings) or SPI must comply with USB-IF guidelines, and the vendor
– Suspend Flag ID must be your own ID as assigned by the USB-IF. The
descriptor also can be modified by changing a mask; contact
– S/PDIF Out With SCMS your representative for details.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 SpAct is a trademark of Texas Instruments.
3 System Two, Audio Precision are trademarks of Audio Precision, Inc.
4 I2S is a trademark of NXP Semiconductors.
5 All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2003–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
PCM2704,, PCM2705
PCM2706, PCM2707
SLES081F – JUNE 2003 – REVISED JANUARY 2009....................................................................................................................................................... www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ABSOLUTE MAXIMUM RATINGS

(1)
over operating free-air temperature range unless otherwise noted
VBUS –0.3 V to 6.5 V
Supply voltage
VCCP, VCCL, VCCR, VDD –0.3 V to 4 V
Supply voltage differences VCCP, VCCL, VCCR, VDD ±0.1 V
Ground voltage differences PGND, AGNDL, AGNDR, DGND, ZGND ±0.1 V
HOST –0.3 V to 6.5 V
Digital input voltage D+, D–, HID0/MS, HID1/MC, HID2/MD, XTI, XTO, DOUT, SSPND, CK, DT,
–0.3 V to (VDD + 0.3) V < 4 V
PSEL, FSEL, TEST, TEST0, TEST1, FUNC0, FUNC1, FUNC2, FUNC3
VCOM –0.3 V to (VCCP + 0.3) V < 4 V
Analog input voltage VOUTR –0.3 V to (VCCR + 0.3) V < 4 V
VOUTL –0.3 V to (VCCL + 0.3) V < 4 V
Input current (any pins except supplies) ±10 mA
Ambient temperature under bias –40°C to 125°C
Storage temperature –55°C to 150°C
Junction temperature 150°C
Lead temperature (soldering) 260°C, 5 s
Package temperature (IR reflow, peak) 260°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range
MIN NOM MAX UNIT
VBUS 4.35 5 5.25
Supply voltage V
VCCP, VCCL, VCCR, VDD 3 3.3 3.6
Digital input logic level TTL compatible
Digital input clock frequency 11.994 12 12.006 MHz
Analog output load resistance 16 32 Ω
Analog output load capacitance 100 pF
Digital output load capacitance 20 pF
Operating free-air temperature, TA –25 85 C

2 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated

Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707

 PCM2704 and PCM2705 PCM2704,, PCM2705
Not Recommended For New Designs PCM2706, PCM2707
www.ti.com....................................................................................................................................................... SLES081F – JUNE 2003 – REVISED JANUARY 2009

ELECTRICAL CHARACTERISTICS
all specifications at TA = 25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz,16-bit data (unless otherwise noted)
PCM2704DB, PCM2705DB,
PARAMETER TEST CONDITIONS PCM2706PJT, PCM2707PJT UNIT
MIN TYP MAX
DIGITAL INPUT/OUTPUT
Host interface Apply USB revision 1.1, full-speed
Audio data format USB isochronous data format
INPUT LOGIC
VIH 2 3.3
VIL –0.3 0.8
Input logic level Vdc
VIH (1) 2 5.5
(1)
VIL –0.3 0.8
(2)
IIH VIN = 3.3 V ±10
(2)
IIL VIN = 0 V ±10
Input logic current µA
IIH VIN = 3.3 V 65 100
IIL VIN = 0 V ±10
OUTPUT LOGIC
VOH (3) IOH = –2 mA 2.8
(3)
VOL IOL = 2 mA 0.3
Output logic level Vdc
VOH IOH = –2 mA 2.4
VOL IOL = 2 mA 0.4
CLOCK FREQUENCY
Input clock frequency, XTI 11.994 12 12.006 MHz
fs Sampling frequency 32, 44.1, 48 kHz
DAC CHARACTERISTICS
Resolution 16 Bits
Audio data channel 1, 2 Channel
DC ACCURACY
Gain mismatch, channel-to-channel ±2 ±8 % of FSR
Gain error ±2 ±8 % of FSR
Bipolar zero error ±3 ±6 % of FSR
(4)
DYNAMIC PERFORMANCE
RL > 10 kΩ, self-powered,
0.006% 0.01%
(5)
VOUT = 0 dB
Line
Total harmonic RL > 10 kΩ, bus-powered,
THD+N 0.012% 0.02%
distortion + noise VOUT = 0 dB
RL = 32 Ω, self-/
Headphone 0.025%
bus-powered, VOUT = 0 dB
THD+N Total harmonic distortion + noise VOUT = –60 dB 2%
Dynamic range EIAJ, A-weighted 90 98 dB
S/N Signal-to-noise ratio EIAJ, A-weighted 90 98 dB
Channel separation 60 70 dB

(1) HOST
(2) D+, D–, HOST, TEST, TEST0, TEST1, DT, PSEL, FSEL, XTI
(3) FUNC0, FUNC1, FUNC2
(4) fIN = 1 kHz, using the System Two™ Cascade audio measurement system by Audio Precision™ in the RMS mode with a 20-kHz LPF
and 400-Hz HPF.
(5) THD+N performance varies slightly, depending on the effective output load, including dummy load R7, R8 in Figure 32.

Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 3

Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707
PCM2704,, PCM2705
PCM2706, PCM2707
SLES081F – JUNE 2003 – REVISED JANUARY 2009....................................................................................................................................................... www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

all specifications at TA = 25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz,16-bit data (unless otherwise noted)
PCM2704DB, PCM2705DB,
PARAMETER TEST CONDITIONS PCM2706PJT, PCM2707PJT UNIT
MIN TYP MAX
ANALOG OUTPUT
Output voltage 0.55 VCCL, 0.55 VCCR Vp-p
Center voltage 0.5 VCCP V
Line AC coupling 10 kΩ
Load impedance
Headphone AC coupling 16 32 Ω
–3 dB 140 kHz
LPF frequency response
f = 20 kHz –0.1 dB
DIGITAL FILTER PERFORMANCE
Pass band 0.454 fs Hz
Stop band 0.546 fs Hz
Pass-band ripple ±0.04 dB
Stop-band attenuation –50 dB
Delay time 20/fs s
POWER SUPPLY REQUIREMENTS
VBUS Bus-powered 4.35 5 5.25
Voltage range VCCP, VCCL, VCCR, Vdc
Self-powered 3 3.3 3.6
VDD
Line DAC operation 23 30
mA
Supply current Headphone DAC operation RL = 32 Ω) 35 46
Line/headphone Suspend mode (6)
150 190 µA
Line DAC operation 76 108
Power dissipation mW
Headphone DAC operation RL = 32 Ω) 116 166
(self-powered)
Line/headphone Suspend mode (6)
495 684 µW
Line DAC operation 115 158
Power dissipation mW
Headphone DAC operation RL = 32 Ω) 175 242
(bus-powered)
Line/headphone Suspend mode (6)
750 998 µW
Internal power-supply VCCP, VCCL, VCCR,
Bus-powered 3.2 3.35 3.5 Vdc
voltage (7) VDD
TEMPERATURE RANGE
Operating temperature –25 85 °C
28-pin SSOP
100
(PCM2704/5)
θJA Thermal resistance °C/W
32-pin TQFP
80
(PCM2706/7)

(6) Under USB suspend state.

(7) VDD, VCCP, VCCL, VCCR. These pins work as output pins of internal power supply for bus-powered operation.

4 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated

Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707

 PCM2704,, PCM2705
PCM2706, PCM2707
www.ti.com....................................................................................................................................................... SLES081F – JUNE 2003 – REVISED JANUARY 2009

PIN ASSIGNMENTS

PCM2704/PCM2705 PCM2706/PCM2707
DB PACKAGE PJT PACKAGE
(TOP VIEW) (TOP VIEW)

FUNC1
FUNC2
DGND

DOUT
VBUS
XTO 1 28 XTI

VDD
D+
D–
CK 2 27 SSPND
DT 3 26 TEST0
4 25 24 23 22 21 20 19 18 17
PSEL TEST1
DOUT 5 24 HID2/MD ZGND 25 16 PSEL
DGND 6 23 HID1/MC AGNDL 26 15 DT
VDD 7 22 HID0/MS VCCL 27 14 CK
D– 8 21 HOST VOUTL 28 13 XTO
D+ 9 20 VCCP VOUTR 29 12 XTI
VBUS 10 19 PGND VCCR 30 11 SSPND
ZGND 11 18 VCOM AGNDR 31 10 TEST
AGNDL 12 17 AGNDR VCOM 32 9 FSEL
VCCL 13 16 VCCR 1 2 3 4 5 6 7 8
VOUTL 14 15 VOUTR

HID1/MC
HID2/MD
HID0/MS
PGND

HOST
VCCP

FUNC3
FUNC0
P0020-01

Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 5

Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707
PCM2704,, PCM2705
PCM2706, PCM2707
SLES081F – JUNE 2003 – REVISED JANUARY 2009....................................................................................................................................................... www.ti.com

Terminal Functions (PCM2704DB/PCM2705DB)

TERMINAL
I/O DESCRIPTION
NAME NO.
AGNDL 12 — Analog ground for headphone amplifier of L-channel
AGNDR 17 — Analog ground for headphone amplifier of R-channel
CK 2 O Clock output for external ROM (PCM2704). Must be left open (PCM2705).
(1)
D+ 9 I/O USB differential input/output plus
(1)
D– 8 I/O USB differential input/output minus
DGND 6 — Digital ground
DOUT 5 O S/PDIF output
(1)
DT 3 I/O Data input/output for external ROM (PCM 2704). Must be left open with pullup resistor (PCM2705).
(2)
HID0/MS 22 I HID key state input (mute), active HIGH (PCM2704). MS input (PCM2705).
(2)
HID1/MC 23 I HID key state input (volume up), active HIGH (PCM2704). MC input (PCM2705).
(2)
HID2/MD 24 I HID key state input (volume down), active HIGH (PCM2704). MD input (PCM2705).
HOST 21 I Host detection during self-powered operation (connect to VBUS). Max power select during bus-powered
operation (LOW: 100 mA, HIGH: 500 mA). (3)
PGND 19 — Analog ground for DAC, OSC, and PLL
(1)
PSEL 4 I Power source select (LOW: self-power, HIGH: bus-power)
SSPND 27 O Suspend flag, active LOW (LOW: suspend, HIGH: operational)
(1)
TEST0 26 I Test pin. Must be set HIGH
(1)
TEST1 25 I Test pin. Must be set HIGH
VBUS 10 — Connect to USB power (VBUS) for bus-powered operation. Connect to VDD for self-powered operation.
(4)
VCCL 13 — Analog power supply for headphone amplifier of L-channel
(4)
VCCP 20 — Analog power supply for DAC, OSC, and PLL
(4)
VCCR 16 — Analog power supply for headphone amplifier of R-channel
VCOM 18 — Common voltage for DAC (VCCP/2). Connect decoupling capacitor to PGND.
(4)
VDD 7 — Digital power supply
VOUTL 14 O DAC analog output for L-channel
VOUTR 15 O DAC analog output for R-channel
(1)
XTI 28 I Crystal oscillator input
XTO 1 O Crystal oscillator output
ZGND 11 — Ground for internal regulator

(1) LV-TTL level

(2) LV-TTL level with internal pulldown
(3) LV-TTL level, 5-V tolerant
(4) Connect decoupling capacitor to GND. Supply 3.3 V for self-powered applications.

6 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated

Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707

 PCM2704,, PCM2705
PCM2706, PCM2707
www.ti.com....................................................................................................................................................... SLES081F – JUNE 2003 – REVISED JANUARY 2009

Terminal Functions (PCM2706PJT/PCM2707PJT)

TERMINAL
I/O DESCRIPTION
NAME NO.
AGNDL 26 — Analog ground for headphone amplifier of L-channel
AGNDR 31 — Analog ground for headphone amplifier of R-channel
CK 14 O Clock output for external ROM (PCM2706). Must be left open (PCM2707).
(1)
D+ 23 I/O USB differential input/output plus
(1)
D– 22 I/O USB differential input/output minus
DGND 20 — Digital ground
DOUT 17 O S/PDIF output/I2S™ data output
(1)
DT 15 I/O Data input/output for external ROM (PCM2706). Must be left open with pullup resistor (PCM2707).
2 (1)
FSEL 9 I Function select (LOW: I S DATA output, HIGH: S/PDIF output)
FUNC0 5 I/O HID key state input (next track), active HIGH (FSEL = 1). I2S LR clock output (FSEL = 0). (2)

2 (2)
FUNC1 19 I/O HID key state input (previous track), active HIGH (FSEL = 1). I S bit clock output (FSEL = 0).
2 (2)
FUNC2 18 I/O HID key state input (stop), active HIGH (FSEL = 1). I S system clock output (FSEL = 0).
FUNC3 4 I HID key state input (play/pause), active HIGH (FSEL = 1). I2S data input (FSEL = 0). (2)

(2)
HID0/MS 6 I HID key state input (mute), active HIGH (PCM2706). MS input (PCM2707)
(2)
HID1/MC 7 I HID key state input (volume up), active HIGH (PCM2706). MC input (PCM2707)
(2)
HID2/MD 8 I HID key state input (volume down), active HIGH (PCM2706). MD input (PCM2707)
HOST 3 I Host detection during self-powered operation (connect to VBUS). Max power select during bus-powered
operation. (LOW: 100 mA, HIGH: 500 mA). (3)
PGND 1 — Analog ground for DAC, OSC, and PLL
(1)
PSEL 16 I Power source select (LOW: self-power, HIGH: bus-power)
SSPND 11 O Suspend flag, active LOW (LOW: suspend, HIGH: operational)
(1)
TEST 10 I Test pin. Must be set HIGH
VBUS 24 — Connect to USB power (VBUS) for bus-powered operation. Connect to VDD for self-powered operation.
(4)
VCCL 27 — Analog power supply for headphone amplifier of L-channel
(4)
VCCP 2 — Analog power supply for DAC, OSC, and PLL
(4)
VCCR 30 — Analog power supply for headphone amplifier of R-channel
VCOM 32 — Common voltage for DAC (VCCP/2). Connect decoupling capacitor to PGND.
(4)
VDD 21 — Digital power supply
VOUTL 28 O DAC analog output for L-channel
VOUTR 29 O DAC analog output for R-channel
(1)
XTI 12 I Crystal oscillator input
XTO 13 O Crystal oscillator output
ZGND 25 — Ground for internal regulator

(1) LV-TTL level

(2) LV-TTL level with internal pulldown
(3) LV-TTL level, 5-V tolerant
(4) Connect decoupling capacitor to GND. Supply 3.3 V for self-powered applications.

Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 7

Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707
PCM2704,, PCM2705
PCM2706, PCM2707
SLES081F – JUNE 2003 – REVISED JANUARY 2009....................................................................................................................................................... www.ti.com

BLOCK DIAGRAM (PCM2704DB/PCM2705DB)

VCCP VCCL VCCR VDD PGND AGNDL AGNDR DGND ZGND

Power
SSPND
Manager
5-V to 3.3-V
Voltage Regulator
VBUS

VCOM USB
Protocol
Analog
VOUTL Controller
PLL
DAC

USB SIE
D+

XCVR
VOUTR Control
Endpoint
D–

DOUT S/PDIF Encoder

EEPROM CK
ISO-Out Interface (1) DT
FIFO
Endpoint HOST

HID0/MS
HID SPI
PSEL HID1/MC
Endpoint Interface (2)
HID2/MD
TEST0

TEST1

96 MHz Tracker
PLL (×8)
(SpAct)

XTI 12 MHz XTO

B0054-01

(1) Applies to PCM2704DB

(2) Applies to PCM2705DB

8 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated

Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707

 PCM2704,, PCM2705
PCM2706, PCM2707
www.ti.com....................................................................................................................................................... SLES081F – JUNE 2003 – REVISED JANUARY 2009

BLOCK DIAGRAM (PCM2706PJT/PCM2707PJT)

VCCP VCCL VCCR VDD PGND AGNDL AGNDR DGND ZGND

Power
SSPND
Manager
5-V to 3.3-V
Voltage Regulator
VBUS

VCOM USB
Protocol
Analog
VOUTL Controller
PLL
DAC

USB SIE
D+

XCVR
VOUTR Control
Endpoint
D–

S/PDIF
Encoder
DOUT

FSEL DOUT
LRCK
FUNC0
BCK
FUNC1 I2S I/F EEPROM CK
SYSCK
FUNC2 ISO-Out Interface (1) DT
DIN FIFO
FUNC3 Endpoint HOST

HID3: Next Track (1)

HID4: Previous Track (1)
HID0/MS
HID5: Stop (1) HID SPI
HID1/MC
HID6: Play/Pause (1) Endpoint Interface (2)
HID2/MD
PSEL

TEST

96 MHz Tracker
PLL (×8)
(SpAct)

XTI 12 MHz XTO

B0055-01

(1) Applies to PCM2706PJT

(2) Applies to PCM2707PJT

Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 9

Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707
PCM2704,, PCM2705
PCM2706, PCM2707
SLES081F – JUNE 2003 – REVISED JANUARY 2009....................................................................................................................................................... www.ti.com

TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER

All specifications at TA = 25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz, 16-bit data (unless otherwise noted).

DAC Digital Interpolation Filter Frequency Response

AMPLITUDE AMPLITUDE
vs vs
FREQUENCY FREQUENCY
0 0.05

0.04
−20
0.03
−40 0.02
Amplitude – dB

Amplitude – dB
0.01
−60
0.00
−80
−0.01

−100 −0.02

−0.03
−120
−0.04

−140 −0.05
0 1 2 3 4 0.0 0.1 0.2 0.3 0.4 0.5
f – Frequency [× fS] f – Frequency [× fS]
G001 G002

Figure 1. Frequency Response Figure 2. Pass-Band Ripple

DAC Analog Low-Pass Filter Frequency Response

AMPLITUDE AMPLITUDE
vs vs
FREQUENCY FREQUENCY
0.0 0

−0.5 −20
Amplitude – dB

Amplitude – dB

−1.0 −40

−1.5 −60

−2.0 −80
0.01 0.1 1 10 100 1 10 100 1k 10k
f – Frequency – kHz f – Frequency – kHz
G003 G004

Figure 3. Pass-Band Characteristics Figure 4. Stop-Band Characteristics

10 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated

Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707

 PCM2704,, PCM2705
PCM2706, PCM2707
www.ti.com....................................................................................................................................................... SLES081F – JUNE 2003 – REVISED JANUARY 2009

TYPICAL PERFORMANCE CURVES

All specifications at TA = 25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz, 16-bit data (unless otherwise noted).

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
0.05 0.05
THD+N – Total Harmonic Distortion + Noise – %

THD+N – Total Harmonic Distortion + Noise – %

Bus-Powered Self-Powered
VOUT = 0 dB VOUT = 0 dB

0.04 0.04

0.03 0.03
32 Ω 32 Ω

0.02 0.02

10 kΩ

0.01 0.01
10 kΩ

0.00 0.00
−50 −25 0 25 50 75 100 −50 −25 0 25 50 75 100
TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C
G005 G006

Figure 5. Figure 6.

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE
0.05 0.05
THD+N – Total Harmonic Distortion + Noise – %

THD+N – Total Harmonic Distortion + Noise – %

Bus-Powered Self-Powered
VOUT = 0 dB VOUT = 0 dB

0.04 0.04

0.03 0.03
32 Ω 32 Ω

0.02 0.02

10 kΩ
0.01 0.01
10 kΩ

0.00 0.00
4.0 4.5 5.0 5.5 3.0 3.1 3.2 3.3 3.4 3.5 3.6
VCC – Supply Voltage – V VCC – Supply Voltage – V
G007 G008

Figure 7. Figure 8.

Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 11

Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707
PCM2704,, PCM2705
PCM2706, PCM2707
SLES081F – JUNE 2003 – REVISED JANUARY 2009....................................................................................................................................................... www.ti.com

TYPICAL PERFORMANCE CURVES (continued)

All specifications at TA = 25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz, 16-bit data (unless otherwise noted).

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs
SAMPLING FREQUENCY SAMPLING FREQUENCY
0.05 0.05
THD+N – Total Harmonic Distortion + Noise – %

THD+N – Total Harmonic Distortion + Noise – %

Bus-Powered Self-Powered
VOUT = 0 dB VOUT = 0 dB

0.04 0.04

32 Ω
0.03 0.03
32 Ω

0.02 0.02
10 kΩ

0.01 0.01
10 kΩ

0.00 0.00
30 35 40 45 50 30 35 40 45 50
fS – Sampling Frequency – kHz fS – Sampling Frequency – kHz
G009 G010

Figure 9. Figure 10.

DYNAMIC RANGE and SNR DYNAMIC RANGE and SNR

vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
105 105
Bus-Powered Self-Powered

103 103
Dynamic Range and SNR – dB

Dynamic Range and SNR – dB

101 101

99 99

Dynamic Range Dynamic Range

97 97
SNR SNR

95 95
−50 −25 0 25 50 75 100 −50 −25 0 25 50 75 100
TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C
G011 G012

Figure 11. Figure 12.

12 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated

Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707

 PCM2704,, PCM2705
PCM2706, PCM2707
www.ti.com....................................................................................................................................................... SLES081F – JUNE 2003 – REVISED JANUARY 2009

TYPICAL PERFORMANCE CURVES (continued)

All specifications at TA = 25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz, 16-bit data (unless otherwise noted).

DYNAMIC RANGE and SNR DYNAMIC RANGE and SNR

vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE
105 105
Bus-Powered Self-Powered

103 103
Dynamic Range and SNR – dB

Dynamic Range and SNR – dB

101 101

99 99
Dynamic Range Dynamic Range

SNR SNR
97 97

95 95
4.0 4.5 5.0 5.5 3.0 3.1 3.2 3.3 3.4 3.5 3.6
VCC – Supply Voltage – V VCC – Supply Voltage – V
G013 G014

Figure 13. Figure 14.

DYNAMIC RANGE and SNR DYNAMIC RANGE and SNR

vs vs
SAMPLING FREQUENCY SAMPLING FREQUENCY
105 105
Bus-Powered Self-Powered

103 103
Dynamic Range and SNR – dB

Dynamic Range and SNR – dB

101 101

Dynamic Range
99 Dynamic Range 99

SNR
97 SNR 97

95 95
30 35 40 45 50 30 35 40 45 50
fS – Sampling Frequency – kHz fS – Sampling Frequency – kHz
G015 G016

Figure 15. Figure 16.

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TYPICAL PERFORMANCE CURVES (continued)

All specifications at TA = 25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz, 16-bit data (unless otherwise noted).

SUSPEND CURRENT SUSPEND CURRENT

vs vs
SUPPLY VOLTAGE FREE-AIR TEMPERATURE
200 200

150 150
Suspend Current – µA

Suspend Current – µA
100 100

50 50

0 0
4.0 4.5 5.0 5.5 −50 −25 0 25 50 75 100
VBUS – Supply Voltage – V TA – Free-Air Temperature – °C
G017 G018

Figure 17. Figure 18.

AMPLITUDE AMPLITUDE
vs vs
FREQUENCY FREQUENCY
0 0

−20 −20

−40 −40
Amplitude – dB

Amplitude – dB

−60 −60

−80 −80

−100 −100

−120 −120

−140 −140
0 5 10 15 20 0 20 40 60 80 100 120
f – Frequency – kHz f – Frequency – kHz
G019 G020

Figure 19. Output Spectrum (–60 dB, N = 8192) Figure 20. Output Spectrum (–60 dB, N = 8192)

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DETAILED DESCRIPTION

Clock and Reset

For both USB and audio functions, the PCM2704/5/6/7 requires a 12-MHz (±500 ppm) clock, which can be
generated by the built-in oscillator using a 12-MHz crystal resonator. The 12-MHz crystal resonator must be
connected to XTI (pin 28 for PCM2704/5, pin 12 for PCM2706/7) and XTO (pin 1 for PCM2704/5, pin 13 for
PCM2706/7) with one large (1-MΩ) resistor and two small capacitors, the capacitance of which depends on the
specified load capacitance of the crystal resonator. An external clock can be supplied from XTI (pin 28 for
PCM2704/5, pin 12 for PCM2706/7). If an external clock is supplied, XTO (pin 1 for PCM2704/5, pin 13 for
PCM2706/7) must be left open. Because no clock disabling pin is provided, it is not recommended to use the
external clock supply. SSPND (pin 27 for PCM2704/5, pin 11 for PCM2706/7) is unable to use clock disabling.
The PCM2704/5/6/7 has an internal power-on reset circuit, and it works automatically when VDD (pin 7 for
PCM2704/5, pin 21 for PCM2706/7) exceeds 2 V typical (1.6 V–2.4 V), which is equivalent to VBUS (pin 10 for
PCM2704/5, pin 24 for PCM2706/7) exceeding 3 V typical for bus-powered applications. Approximately 700 µs is
required until internal reset release.

Operation Mode Selection

The PCM2704/5/6/7 has the following mode-select pins.

Power Configuration Select/Host Detection

PSEL (pin 4 for PCM2704/5, pin 16 for PCM2706/7) is dedicated to selecting the power source. This selection
affects the configuration descriptor. While in bus-powered operation, maximum power consumption from VBUS is
determined by HOST (pin 21 for PCM2704/5, pin 3 for PCM2706/7). For self-powered operation, HOST must be
connected to VBUS of the USB bus with a pulldown resistor to detect attach and detach. (To avoid excessive
suspend current, the pulldown should be a high-value resistor.)

Table 1. Power Configuration Select

PSEL DESCRIPTION
0 Self-powered
1 Bus-powered

HOST DESCRIPTION
0 Detached from USB (self-powered)/100 mA (bus-powered)
1 Attached to USB (self-powered)/500 mA (bus-powered)

Function Select (PCM2706/7)

FSEL (pin 9) determines the function of FUNC0–FUNC3 (pins 4, 5, 18, and 19) and DOUT (pin17). When the I2S
interface is required, FSEL must be set to LOW. Otherwise, FSEL must be set to HIGH.

Table 2. Function Select

FSEL DOUT FUNC0 FUNC1 FUNC2 FUNC3
0 Data out (I2S) LRCK (I2S) BCK (I2S) SYSCK (I2S) Data in (I2S)
(1) (1) (1) (1)
1 S/PDIF data Next track (HID) Previous track (HID) Stop (HID) Play/pause (HID)

(1) Valid on the PCM2706; no function assigned on the PCM2707.

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USB Interface
Control data and audio data are transferred to the PCM2704/5/6/7 via D+ (pin 9 for PCM2704/5, pin 23 for
PCM2706/7) and D– (pin 8 for PCM2704/5, pin 22 for PCM2706/7). D+ should be pulled up with a 1.5-kΩ (±5%)
resistor. To avoid back voltage in self-powered operation, the device must not provide power to the pullup
resistor on D+ while VBUS of the USB port is inactive.
All data to/from the PCM2704/5/6/7 are transferred at full speed. The following information is provided in the
device descriptor. Some parts of the device descriptor can be modified through external ROM (PCM2704/6), SPI
(PCM2705/7), or internal mask ROM on request.

Table 3. Device Descriptor

DEVICE DESCRIPTOR DESCRIPTION
USB revision 1.1 compliant
Device class 0x00 (device defined interface level)
Device subclass 0x00 (not specified)
Device protocol 0x00 (not specified)
Max packet size for endpoint 0 8 bytes
Vendor ID 0x08BB (default value, can be modified)
0x2704/0x2705/0x2706/0x2707 (These values correspond to the model number, and the value can be
Product ID
modified.)
Device release number 1.0 (0x0100)
Number of configurations 1
Vendor strings Burr-Brown from TI (default value, can be modified)
Product strings USB Audio DAC (default value, can be modified)
Serial number Not supported

The following information is contained in the configuration descriptor. Some parts of the configuration descriptor
can be modified through external ROM (PCM2704/6), SPI (PCM2705/7), or internal mask ROM on request.

Table 4. Configuration Descriptor

CONFIGURATION DESCRIPTOR DESCRIPTION
Interface Three interfaces
0x80 or 0xC0 (bus-powered or self-powered, depending on PSEL; no remote wake up. This value can
Power attribute
be modified.)
0x0A, 0x32 or 0xFA (20 mA for self-powered, 100 mA or 500 mA for bus-powered, depending on
Max power
PSEL and HOST. This value can be modified.)

The following information is contained in the string descriptor. Some parts of the string descriptor can be modified
through external ROM (PCM2704/6), SPI (PCM2705/7), or internal mask ROM on request.

Table 5. String Descriptor

STRING DESCRIPTOR DESCRIPTION
#0 0x0409
#1 Burr-Brown from TI (default value, can be modified)
#2 USB Audio DAC (default value, can be modified)

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Device Configuration
Figure 21 illustrates the USB audio function topology. The PCM2704/5/6/7 has three interfaces. Each interface is
enabled by some alternative settings.

Endpoint #0

Default
Endpoint

FU
Endpoint #2
(IF #1) IT OT
Analog Out
TID1 TID2
Audio Streaming
Interface UID3

Standard Audio Control Interface (IF #0)

Endpoint #5
(IF #2)

HID Interface

PCM2704/5/6/7

M0024-01

Figure 21. USB Audio Function Topology

Interface #0 (Default/Control Interface)

Interface #0 is the control interface. Setting #0 is the only possible setting for interface #0. Setting #0 describes
the standard audio control interface. Audio control interface consists of a terminal. The PCM2704/5/6/7 has three
terminals:
• Input terminal (IT #1) for isochronous-out stream
• Output terminal (OT #2) for audio analog output
• Feature unit (FU #3) for DAC digital attenuator
Input terminal #1 is defined as a USB stream (terminal type 0x0101). Input terminal #1 can accept two-channel
audio streams constructed of left and right channels. Output terminal #2 is defined as a speaker (terminal type
0x0301). Feature unit #3 supports the following sound control features:
• Volume control
• Mute control
The built-in digital volume controller can be manipulated by an audio-class-specific request from 0 dB to –64 dB
in steps of 1 dB. Changes are made by incrementing or decrementing one step (1 dB) for every 1/fS time interval,
until the volume level reaches the requested value. Each channel can be set to a separate value. The master
volume control is not supported. A request to the master volume is stalled and ignored. The built-in digital mute
controller can be manipulated by an audio-class-specific request. A master mute control request is acceptable. A
mute control request to an individual channel is stalled and ignored. The digital volume control does not affect
the S/PDIF and I2S outputs (PCM2706/7).

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Interface #1 (Isochronous-Out Interface)

Interface #1 is for the audio-streaming data-out interface. Interface #1 has the following three alternative settings.
Alternative setting #0 is the zero-bandwidth setting. All other alternative settings are operational settings.
ALTERNATIVE TRANSFER SAMPLING RATE
DATA FORMAT
SETTING MODE (kHz)
00 Zero bandwidth
01 16-bit Stereo 2s complement (PCM) Adaptive 32, 44.1, 48
02 16-bit Mono 2s complement (PCM) Adaptive 32, 44.1, 48

Interface #2 (HID Interface)

Interface #2 is the interrupt-data-in interface. Interface #2 comprises the HID consumer control device.
Alternative setting #0 is the only possible setting for interface #2.
On the HID device descriptor, eight HID items are reported as follows for any model, in any configuration.

Basic HID Operation

Interface #2 can report the following three key statuses for any model. These statuses can be set by the
HID0–HID2 pins (PCM2704/6) or the SPI port (PCM2705/7).
• Mute (0xE2)
• Volume up (0xE9)
• Volume down (0xEA)

Extended HID Operation (PCM2705/6/7)

By using the FUNC0–FUNC3 pins (PCM2706) or the SPI port (PCM2705/7), the following additional conditions
can be reported to the host.
• Play/Pause (0xCD)
• Stop (0xB7)
• Previous (0xB6)
• Next (0xB5)

Auxiliary HID Status Report (PCM2705/7)

One additional HID status can be reported to the host though the SPI port. This status flag is defined by SPI
command or external ROM. This definition must be described as on the report descriptor with a three-byte usage
ID. AL A/V Capture (0x0193) is assigned as the default for this status flag.

Endpoints
The PCM2704/5/6/7 has three endpoints:
• Control endpoint (EP #0)
• Isochronous-out audio data-stream endpoint (EP #2)
• HID endpoint (EP #5)
The control endpoint is a default endpoint. The control endpoint is used to control all functions of the
PCM2704/5/6/7 by standard USB request and USB audio-class-specific request from the host. The
isochronous-out audio data-stream endpoint is an audio sink endpoint that receives the PCM audio data. The
isochronous-out audio data-stream endpoint accepts the adaptive transfer mode. The HID endpoint is an
interrupt-in endpoint. The HID endpoint reports HID status every 10 ms.
The HID endpoint is defined as a consumer-control device. The HID function is designed as an independent
endpoint from the isochronous-out endpoint. This means that the effect of HID operation depends on host
software. Typically, the HID function is used to control the primary audio-out device.

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DAC
The PCM2704/5/6/7 has a DAC that uses an oversampling technique with 128-fS second-order multibit noise
shaping. This technique provides extremely low quantization noise in the audio band, and the built-in analog
low-pass filter removes the high-frequency components of the noise-shaping signal. DAC outputs through the
headphone amplifier VOUTL and VOUTR can provide 12 mW at 32 Ω, as well as 1.8 VPP into a 10-kΩ load.

Digital Audio Interface—S/PDIF Output

The PCM2704/5/6/7 employs S/PDIF output. Isochronous-out data from the host are encoded to S/PDIF output
DOUT, as well as to DAC analog outputs VOUTL and VOUTR. Interface format and timing follow the IEC-60958
standard. Monaural data are converted to the stereo format at the same data rate. S/PDIF output is not
supported in the I2S I/F enable mode. The implementation of this feature is optional. Note that it is your
responsibility to determin whether to implement this feature in your product or not.

Channel Status Information

The channel status information is fixed as consumer application, PCM mode, copyright, and digital/digital
converter. All other bits are fixed as 0s, except for the sample frequency, which is set automatically according to
the data received through the USB.

Copyright Management
Digital audio data output always is encoded as original with SCMS control. Only one generation of digital
duplication is allowed.

Digital Audio Interface—I2S Interface Output (PCM2706/7)

The PCM2706 and PCM2707 can support the I2S interface, which is enabled by FSEL (pin 9). In the I2S interface
enabled mode, pins 4, 18, 19, 5, and 17 are assigned as DIN, SYSCK, BCK, LRCK, and DOUT, respectively.
They provide digital output/input data in the 16-bit I2S format, which also is accepted by the internal DAC. I2S
interface format and timing are shown in Figure 22, Figure 23, and Figure 24.
SYSCK
(256 fS)

1/fS

LRCK L-Channel R-Channel

BCK
(64 fS)

DOUT 1 2 3 14 15 16 1 2 3 14 15 16 1 2

MSB LSB MSB LSB MSB

DIN 1 2 3 14 15 16 1 2 3 14 15 16 1 2

T0009-04

Figure 22. Audio Data Interface Format

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LRCK (Output) 50% of VDD

t(BCL)
t(BCH) t(BL)

BCK (Output) 50% of VDD

t(BCY) t(BD) t(LD)

DOUT (Output) 50% of VDD

t(DS)
t(DH)

DIN (Input) 50% of VDD

T0010-05

SYMBOL PARAMETER MIN MAX UNIT

t(BCY) BCK pulse cycle time 300 ns
t(BCH) BCK pulse duration, HIGH 100 ns
t(BCL) BCK pulse duration, LOW 100 ns
t(BL) LRCK delay time from BCK falling edge –20 40 ns
t(BD) DOUT delay time from BCK falling edge –20 40 ns
t(LD) DOUT delay time from LRCK edge –20 40 ns
t(DS) DIN setup time 20 ns
t(DH) DIN hold time 20 ns

NOTE: Load capacitance of LRCK, BCK, and DOUT is 20 pF.

Figure 23. Audio Interface Timing

SYSCK
(Output)

t(SLL) t(SLH)

LRCK
(Output)

t(SBL) t(SBH)

BCK
(Output)

T0196-01

SYMBOL PARAMETER MIN MAX UNIT

t(SLL), t(SLH) LRCK delay time from SYSCK rising edge –5 10 ns
t(SBL), t(SBH) BCK delay time from SYSCK rising edge –5 10 ns

NOTE: Load capacitance is 20 pF.

Figure 24. Audio Clock Timing

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DESCRIPTOR DATA MODIFICATION

The descriptor data can be modified through I2C port by external ROM (PCM2704/6) or through our SPI port by
an SPI host such as an MCU (PCM2705/7) under a particular condition of PSEL pin and HOST pin. A condition
of PSEL pin = High and HOST pin = High is needed to modify the descriptor data, and D+ pull-up must not be
activated before completion of programming the descriptor data through external ROM or SPI port. The
descriptor data have to be sent from external ROM to PCM2704/6 or or from SPI host to PCM2705/7 in LSB first
with specified byte order. Also, the content of the power attribute and max power must be consistent with PSEL
setting and power usage from USB VBUS of actual application. Therefore, the descriptor data modification in
self-powered configuration (PSEL = Low) is not supported.

External ROM Descriptor (PCM2704/6)

The PCM2704/6 supports an external ROM interface to override internal descriptors. Pin 3 (for PCM2704)/pin 15
(for PCM2706) is assigned as DT (serial data) and pin 2 (for PCM2704)/pin 14 (for PCM2706) is assigned as CK
(serial clock) of the I2C interface when using the external ROM descriptor. Descriptor data is transferred from the
external ROM to the PCM2704/6 through the I2C interface the first time when the device activates after power-on
reset. Before completing a read of the external ROM, the PCM2704/6 replies with NACK for any USB command
request from the host to the device itself. The descriptor data, which can be in external ROM, are as follows.
String descriptors must be described in ANSI ASCII code (1 byte for each character). String descriptors are
converted automatically to unicode strings for transmission to the host. The device address of the external ROM
is fixed as 0xA0. The data must be stored from address 0x00 and must consist of 57 bytes, as described in the
following items. The data bits must be sent from LSB to MSB on the I2C bus. This means that each byte of data
must be stored with its bits in reverse order. Read operation is performed at a frequency of XTI/384
(approximately 30 kHz). The content of power attribute and max power must be consistent with actual application
circuit configuration (PSEL setting and actual power usage from VBUS of USB connector); otherwise, it may
cause improper or unexpected PCM2704/6 operation.
• Vendor ID (2 bytes)
• Product ID (2 bytes)
• Product string (16 bytes in ANSI ASCII code)
• Vendor string (32 bytes in ANSI ASCII code)
• Power attribute (1 byte)
• Max power (1 byte)
• Auxiliary HID usage ID in report descriptor (3 bytes)

DT

CK S 1−7 8 9 1−8 9 1−8 9 9 P

Device Address R/W ACK DATA ACK DATA ACK NACK

Start Condition R/W: Read Operation if 1; Otherwise, Write Operation Stop Condition
ACK: Acknowledgment of a Byte if 0
DATA: 8 Bits (Byte)
NACK: Not Acknowledgment if 1
T0049-02

M M M S S M S M S M M
S Device address R/W ACK DATA ACK DATA ACK ... NACK P

Figure 25. External ROM Read Operation

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Start Repeated Start Stop

t(D-HD) t(DT-F)
t(BUF) t(D-SU) t(DT-R) t(P-SU)

DT

t(CK-R) t(RS-HD)
t(LOW)

CK

t(S-HD) t(HI) t(RS-SU)

t(CK-F)
T0050-02

SYMBOL PARAMETER MIN MAX UNIT

f(CK) CK clock frequency 100 kHz
t(BUF) Bus free time between a STOP and a START condition 4.7 µs
t(LOW) Low period of the CK clock 4.7 µs
t(HI) High period of the CK clock 4 µs
t(RS-SU) Setup time for START/repeated START condition 4.7 µs
t(S-HD)
Hold time for START/repeated START condition 4 µs
t(RS-HD)
t(D-SU) Data setup time 250 ns
t(D-HD) Data hold time 0 900 ns
t(CK-R) Rise time of CK signal 20 + 0.1 CB 1000 ns
t(CK-F) Fall time of CK signal 20 + 0.1 CB 1000 ns
t(DT-R) Rise time of DT signal 20 + 0.1 CB 1000 ns
t(DT-F) Fall time of DT signal 20 + 0.1 CB 1000 ns
t(P-SU) Setup time for STOP condition 4 µs
CB Capacitive load for DT and CK lines 400 pF
VNH Noise margin at HIGH level for each connected device (including hysteresis) 0.2 VDD V

Figure 26. External ROM Read Interface Timing Requirements

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External ROM Example

Here is an example of external ROM data, with an explanation of the example following the data.
0xBB, 0x08, 0x04, 0x27,
0x50, 0x72, 0x6F, 0x64, 0x75, 0x63, 0x74, 0x20, 0x73, 0x74, 0x72, 0x69, 0x6E, 0x67, 0x73, 0x2E,
0x56, 0x65, 0x6E, 0x64, 0x6F, 0x72, 0x20, 0x73, 0x74, 0x72, 0x69, 0x6E, 0x67, 0x73, 0x20, 0x61,
0x72, 0x65, 0x20, 0x70, 0x6C, 0x61, 0x63, 0x65, 0x64, 0x20, 0x68, 0x65, 0x72, 0x65, 0x2E, 0x20,
0x80,
0x7D,
0x0A, 0x93, 0x01

The data are stored beginning at address 0x00.

Vendor ID: 0x08BB
Product ID: 0x2704
Product string: Product strings (16 bytes).
Vendor string: Vendor strings are placed here (32 bytes, 31 visible characters are followed by 1 space).
Power attribute (bmAttribute): 0x80 (Bus-powered).
Max power (maxPower): 0x7D (250 mA).
Auxiliary HID usage ID: 0x0A, 0x93, 0x01 (AL A/V capture).
Note that the data bits must be sent from LSB to MSB on the I2C bus. This means that each data byte must be
stored with its bits in reverse order.

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Serial Programming Interface (PCM2705/7)

The PCM2705/7 supports the serial programming interface (SPI) to program the descriptor and to set the HID
state. Descriptor data are described in the SubSec1 8.8External ROM Descriptor section.
t(MHH)

MS 50% of VDD

t(MLS) t(MCL)
t(MCH) t(MLH)

MC 50% of VDD

t(MCY)

LSB
MD 50% of VDD

t(MDS)
t(MDH)
T0013-04

SYMBOL PARAMETER MIN TYP MAX UNIT

t(MCY) MC pulse cycle time 100 ns
t(MCL) MC low-level time 50 ns
t(MCH) MC high-level time 50 ns
t(MHH) MS high-level time 100 ns
t(MLS) MS falling edge to MC rising edge 20 ns
t(MLH) MS hold time 20 ns
t(MDH) MD hold time 15 ns
t(MDS) MD setup time 20 ns

Figure 27. SPI Timing Diagram

(1) Single Write Operation

16 Bits

MS

MC

MD

MSB LSB MSB

(2) Continuous Write Operation

16 Bits y N Frames

MS

MC

MD

MSB LSB MSB LSB MSB LSB

N Frames
T0012-02

Figure 28. SPI Write Operation

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SPI Register (PCM2705/7)

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0 0 0 0 ST 0 ADDR 0 D0 D1 D2 D3 D4 D5 D6 D7

D[7:0] Function of the lower 8 bits depends on the value of the ST (B11) bit.
ST = 0 (HID status write)
D7 Reports MUTE HID status to the host (active high)
D6 Reports volume-up HID status to the host (active high)
D5 Reports volume-down HID status to the host (active high)
D4 Reports next-track HID status to the host (active high)
D3 Reports previous-track HID status to the host (active high)
D2 Reports stop HID status to the host (active high)
D1 Reports play/pause HID status to the host (active high)
D0 Reports extended command status to the host (active high)
ST = 1 (ROM data write)
D[7:0] Internal descriptor ROM data, D0:LSB, D7:MSB
The content of power attribute and max power must be consistent with the actual application circuit
configuration (PSEL setting and actual power usage from VBUS of USB connector); otherwise, it may cause
improper or unexpected PCM2705/7 operation.

ADDR Starts write operation for internal descriptor reprogramming (active high)
This bit resets descriptor ROM address counter and indicates following words should be ROM data (described
in the External ROM Example section). 456 bits of ROM data must be continuously followed after this bit has
been asserted. The data bits must be sent from LSB (D0) to MSB (D7).
To set ADDR high, ST must be set low. Note that the lower 8 bits are still active as an HID status write when
ST is set low.
ST Determines the function of the lower 8-bit data as follows:
0: HID status write
1: Descriptor ROM data write

Table 6. Functionality of ST and ADDR Bit Combinations

ST ADDR FUNCTION
0 0 HID status write
0 1 HID status write and descriptor ROM address reset
1 0 Descriptor ROM data write
1 1 Reserved

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PCM2704,, PCM2705
PCM2706, PCM2707
SLES081F – JUNE 2003 – REVISED JANUARY 2009....................................................................................................................................................... www.ti.com

USB Host Interface Sequence

Power-On, Attach, and Playback Sequence

The PCM2704/5/6/7 is ready for setup when the reset sequence has finished and the USB bus is attached. After
a connection has been established by setup, the PCM2704/5/6/7 is ready to accept USB audio data. While
waiting for the audio data (idle state), the analog output is set to bipolar zero (BPZ).

ÎÎÎ
When receiving the audio data, the PCM2704/5/6/7 stores the first audio packet, which contains 1 ms of audio

ÎÎÎ
data, into the internal storage buffer. The PCM2704/5/6/7 starts playing the audio data after detecting the next

ÎÎÎ
subsequent start-of-frame (SOF) packet.

ÎÎÎ
ÎÎÎ
3.3 V
(Typ.)

ÎÎÎ
VDD 2.0 V (Typ.)

ÎÎÎ ÎÎ Î Î Î ÎÎÎ Î ÎÎÎ ÎÎ

ÎÎÎ
0V

ÎÎÎ Î Î Î ÎÎÎ Î ÎÎÎ ÎÎ

ÎÎÎ
ÎÎÎ ÎÎ Î Î Î ÎÎÎ Î ÎÎÎ ÎÎ
ÎÎÎ
Bus Reset Set Configuration 1st Audio Data 2nd Audio Data

ÎÎÎ Î Î ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ

Bus Idle

ÎÎÎ
D+/D−
SOF SOF SOF

ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
SSPND

ÎÎÎ
ÎÎÎ
ÎÎÎ
BPZ
VOUTL

ÎÎÎ
VOUTR

ÎÎÎ
700 µs Device Setup 1 ms

Internal Reset
Ready for Setup Ready for Playback
T0055-01

Figure 29. Initial Sequence

26 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated

Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707

 PCM2704,, PCM2705
PCM2706, PCM2707
www.ti.com....................................................................................................................................................... SLES081F – JUNE 2003 – REVISED JANUARY 2009

Play, Stop, and Detach Sequence

When the host finishes or aborts the playback, the PCM2704/5/6/7 stops playing after completing the output of
the last audio data.

VBUS
ÎÎ ÎÎ Î ÎÎÎ ÎÎ
ÎÎÎ ÎÎ ÎÎ
ÎÎ ÎÎ Audio Data
Î ÎÎÎ ÎÎ
ÎÎÎ ÎÎ
Audio Data Last Audio Data
ÎÎ
ÎÎ ÎÎ Î ÎÎÎ ÎÎ
ÎÎÎ ÎÎ ÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
D+/D–
SOF SOF SOF SOF SOF

VOUTL
VOUTR

1 ms Detach
T0056-01

Figure 30. Play, Stop, and Detach

Suspend and Resume Sequence

Î ÎÎ
The PCM2704/5/6/7 enters the suspend state after the USB bus has been in a constant idle state for
approximately 5 ms. While the PCM2704/5/6/7 is in the suspend state, SSPND flag (pin 27 for PCM2704/5,

ÎÎ
pin 11 for PCM2706/7) is asserted. The PCM2704/5/6/7 wakes up immediately when detecting the non-idle state
on the USB bus. ÎÎ
ÎÎ
ÎÎ Idle
ÎÎ
ÎÎ
D+/D−

SSPND

5 ms Suspend

VOUTL
VOUTR

Active Active
2.5 ms
T0057-01

Figure 31. Suspend and Resume

Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 27

Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707
PCM2704,, PCM2705
PCM2706, PCM2707
SLES081F – JUNE 2003 – REVISED JANUARY 2009....................................................................................................................................................... www.ti.com

Typical Circuit Connection 1 (Example of USB Speaker)

Figure 32 illustrates a typical circuit connection for an internal-descriptor, bus-powered, 500-mA application.
X1
C1 C2

R1

(3)
PCM2704DB
External ROM
(Optional) 1 XTO XTI 28
SUSPEND
SCL 2 CK SSPND 27

SDA 3 DT TEST0 26
(2)
R9 4 PSEL TEST1 25

S/PDIF OUT 5 DOUT HID2/MD 24

VOLUME–
6 DGND HID1/MC 23
USB ’B’ R2 C7 VOLUME+
Connector 7 VDD HID0/MS 22
R3 (2)
MUTE
D– 8 D– HOST 21
R4 C4
D+ 9 D+ VCCP(3) 20

VBUS 10 VBUS PGND 19

C3 + C8
GND 11 ZGND VCOM 18

12 AGNDL AGNDR 17
C6 C5
13 VCCL VCCR 16 C9 C13
(1) (1) + +
14 VOUT L VOUTR 15
+ +

C11 C12 C10 C14 TPA200X

Power
Amp
R5 R6 R7 R8

NOTE: X1: 12-MHz crystal resonator. C1, C2: 10-pF to 33-pF capacitor (depending on load capacitance of crystal resonator). C3-C7: 1-µF
ceramic capacitor. C8: 10-µF electrolytic capacitor. C9, C10: 100-µF electrolytic capacitor (depending on tradeoff between required frequency
response and discharge time for resume). C11, C12: 0.022-µF ceramic capacitor. C13, C14: 1-µF electrolytic capacitor. R1: 1 MΩ resistor. R2,
R9: 1.5 kΩ resistors. R3, R4: 22 Ω resistors. R5, R6: 16 Ω resistors. R7, R8: 330 Ω resistors (depending on tradeoff between required THD
performance and pop-noise level for suspend).
(1) Output impedance of VOUTL and VOUTR during suspend mode or lack of power supply is 26 kΩ ±20%, which is the discharge path for C9
and C10.
(2) Descriptor programming through external ROM is only available when PSEL and HOST are high.
(3) External ROM power can be supplied from VCCP, but any other active component must not use VCCP, VCCL, VCCR, or VDD as a power
source.

Figure 32. Bus-Powered Application

NOTE:
The circuit illustrated in Figure 32 is for information only. The entire board design
should be considered to meet the USB specification as a USB-compliant product.

28 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated

Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707

 PCM2704,, PCM2705
PCM2706, PCM2707
www.ti.com....................................................................................................................................................... SLES081F – JUNE 2003 – REVISED JANUARY 2009

Typical Circuit Connection 2 (Example of Remote Headphone)

Figure 33 illustrates a typical circuit connection for a bus-powered, 100-mA headphone with seven HIDs.
C9 Headphone
+

+
C11 C12
C10

R5 R6 R7 R8 R9 R10
C6 C3 C4
+

32 31 30 29 28 27 26 25 USB ’B’
Connector

(1)

(1)

ZGND
VCOM

AGNDR

VCCR

AGNDL
VCCL
R2

VOUT R

VOUT L
C5
1 PGND VBUS 24 VBUS
R3
(3)
2 VCCP D+ 23 D+
(2)
3 HOST D– 22 D–
PLAY/PAUSE R4
4 FUNC3 VDD 21 GND
NEXT TRACK PCM2706PJT C8
5 FUNC0 DGND 20 C7
MUTE PREVIOUS TRACK
6 HID0/MS FUNC1 19
VOLUME+ STOP
7 HID1/MC FUNC2 18
VOLUME–
(2)

8 HID2/MD DOUT 17
SSPND

PSEL
TEST
FSEL

XTO

(3)
External ROM
XTI

CK

DT

91 10 11 12 13 14 5 16
(Optional)

SDA

SUSPEND
R1 R11
SCL
X1

C1 C2

NOTE: X1: 12-MHz crystal resonator. C1, C2: 10-pF to 33-pF capacitors (depending on load capacitance of crystal resonator). C3-C5, C7, C8:
1-µF ceramic capacitors. C6: 10-µF electrolytic capacitor. C9, C10: 100-µF electrolytic capacitors (depending on required frequency response).
C11, C12: 0.022-µF ceramic capacitors. R1: 1 MΩ resistor. R2, R11: 1.5 kΩ resistors. R3, R4: 22 Ω resistors. R5, R6: 16 Ω resistors. R7-R10: 3.3
kΩ resistors.
(1) Output impedance of VOUTL and VOUTR during suspend mode or lack of power supply is 26 kΩ ±20%, which is the discharge path for C9
and C10.
(2) Descriptor programming through external ROM is only available when PSEL and HOST are high.
(3) External ROM power can be supplied from VCCP, but any other active component must not use VCCP, VCCL, VCCR, or VDD as a power
source.

Figure 33. Bus-Powered Application

NOTE:
The circuit illustrated in Figure 33 is for information only. The entire board design
should be considered to meet the USB specification as a USB-compliant product.

Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 29

Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707
PCM2704,, PCM2705
PCM2706, PCM2707
SLES081F – JUNE 2003 – REVISED JANUARY 2009....................................................................................................................................................... www.ti.com

Typical Circuit Connection 3 (Example of DSP Surround Processing Amp)

Figure 34 illustrates a typical circuit connection for an I2S- and SPI-enabled self-powered application.
+
C8
Headphone
+
C10 C11
C9
C6 C3 C4
+ R6 R7 R8 R9 R10 R11

32 31 30 29 28 27 26 25 USB ’B’
Connector

ZGND
(1)
VCOM

(1)
AGNDR

VCCR

AGNDL
VCCL
(3)
R2

VOUT R

VOUT L
C5
1 PGND VBUS 24 VBUS(3)
T AS300X
(4) R3
I2S I/F Audio Device + 2 VCCP D+ 23 D+
(2)
3 HOST D– 22 D–
DIN (3) R4 R12
4 FUNC3 VDD 21
+ GND
LRCK PCM2707PJT C7
5 FUNC0 DGND 20
MS 6
(4) BCK
HID0/MS FUNC1 19
MC SYSTEM CLOCK
7 HID1/MC FUNC2 18
MD DOUT

(2)
8 HID2/MD DOUT 17
SSPND

PSEL
TEST
FSEL

XTO
XTI

CK

DT

91 10 11 12 13 14 51 6

R5
SUSPEND
R1

X1
Power

C1 C2 3.3 V

GND

NOTE: X1: 12-MHz crystal resonator. C1, C2: 10-pF to 33-pF capacitors (depending on load capacitance of crystal resonator). C3, C4: 1-µF
ceramic capacitors. C5, C7: 0.1-µF ceramic capacitor and 10-µF electrolytic capacitor. C6: 10-µF electrolytic capacitors. C8, C9: 100-µF
electrolytic capacitors (depending on required frequency response). C10, C11: 0.022-µF ceramic capacitors. R1, R12: 1 MΩ resistors. R2, R5:
1.5 kΩ resistors. R3, R4: 22 Ω resistors. R6, R7: 16 Ω resistors. R8-R11: 3.3 kΩ resistors.
(1) Output impedance of VOUTL and VOUTR during suspend mode or lack of power supply is 26 kΩ ±20%, which is the discharge path for C8
and C9.
(2) Descriptor programming through SPI is only available when PSEL and HOST are high.
(3) D+ pull-up must not be activated (HIGH: 3.3V) while the device is detached from USB or power supply is not applied on VDD and VCCx.
VBUS of USB (5V) can be used to detect USB power status.
(4) MS must be high until the PCM2707 power supply is ready and the SPI host (DSP) is ready to send data. Also, the SPI host must handle
the D+ pull-up if the descriptor is programmed through the SPI. D+ pull-up must not be activated (HIGH = 3.3 V) before programming of the
PCM2707 through the SPI is complete.

Figure 34. Self-Powered Application

NOTE:
The circuit illustrated in Figure 34 is for information only. The entire board design
should be considered to meet the USB specification as a USB-compliant product.

30 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated

Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707

 PCM2704,, PCM2705
PCM2706, PCM2707
www.ti.com....................................................................................................................................................... SLES081F – JUNE 2003 – REVISED JANUARY 2009

APPENDIX

Operating Environment
For current information on the PCM2704/2705/2706/2707 operating environment, see the Updated Operating
Environments for PCM270X, PCM290X Applications application report, SLAA374, available through the TI web
site at www.ti.com.

Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 31

Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707
PCM2704,, PCM2705
PCM2706, PCM2707
SLES081F – JUNE 2003 – REVISED JANUARY 2009....................................................................................................................................................... www.ti.com

REVISION HISTORY

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision E (November 2007) to Revision F ............................................................................................ Page

• Added new feature................................................................................................................................................................. 1

• Moved text to end of Digital Audio Interface-S/PDIF Output section................................................................................... 19
• Added Descriptor Data Modification paragraph................................................................................................................... 21
• Deleted HOST from list of circuit configuration terms.......................................................................................................... 21
• Deleted HOST from list of circuit configuration terms.......................................................................................................... 25
• Added notes to Figure 32, Figure 33, and Figure 34 for clarifying requirement of descriptor programing.......................... 28

Changes from Revision D (December 2006) to Revision E ........................................................................................... Page

• Deleted operating environment information from data sheet and added reference to application report ........................... 31

32 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated

Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707

 PACKAGE OPTION ADDENDUM

www.ti.com 14-Oct-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

PCM2704DB ACTIVE SSOP DB 28 47 RoHS & Green NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2704 Samples

PCM2704DBR ACTIVE SSOP DB 28 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2704 Samples

PCM2705DB ACTIVE SSOP DB 28 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2705 Samples

PCM2705DBG4 ACTIVE SSOP DB 28 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2705 Samples

PCM2705DBR ACTIVE SSOP DB 28 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2705 Samples

PCM2706PJT ACTIVE TQFP PJT 32 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2706 Samples

PCM2706PJTR ACTIVE TQFP PJT 32 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2706 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 14-Oct-2022

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 2-Mar-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PCM2704DBR SSOP DB 28 2000 330.0 17.4 8.5 10.8 2.4 12.0 16.0 Q1
PCM2704DBR SSOP DB 28 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
PCM2705DBR SSOP DB 28 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
PCM2706PJTR TQFP PJT 32 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 2-Mar-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCM2704DBR SSOP DB 28 2000 336.6 336.6 28.6
PCM2704DBR SSOP DB 28 2000 356.0 356.0 35.0
PCM2705DBR SSOP DB 28 2000 356.0 356.0 35.0
PCM2706PJTR TQFP PJT 32 1000 350.0 350.0 43.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 2-Mar-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
PCM2704DB DB SSOP 28 47 530 10.5 4000 4.1
PCM2704DB DB SSOP 28 47 500 10.6 500 9.6
PCM2705DB DB SSOP 28 50 530 10.5 4000 4.1
PCM2705DBG4 DB SSOP 28 50 530 10.5 4000 4.1

Pack Materials-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 2-Mar-2024

TRAY

L - Outer tray length without tabs KO -

Outer
tray
height

W-
Outer
tray
width
Text

P1 - Tray unit pocket pitch

CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

Device Package Package Pins SPQ Unit array Max L (mm) W K0 P1 CL CW
Name Type matrix temperature (mm) (µm) (mm) (mm) (mm)
(°C)
PCM2706PJT PJT TQFP 32 250 10 x 25 150 315 135.9 7620 12.2 11.1 11.25
PCM2706PJT PJT TQFP 32 250 10 x 25 150 315 135.9 7620 12.2 11.1 11.25
PCM2706PJTR PJT TQFP 32 1000 10 x 25 150 315 135.9 7620 12.2 11.1 11.25
PCM2706PJTR PJT TQFP 32 1000 10 x 25 150 315 135.9 7620 12.2 11.1 11.25

Pack Materials-Page 4
 PACKAGE OUTLINE
DB0028A SCALE 1.500
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

C
8.2
TYP
A 7.4
0.1 C SEATING
PIN 1 INDEX AREA
PLANE
26X 0.65
28
1

2X
10.5
8.45
9.9
NOTE 3

14
15
0.38
28X
0.22
5.6 0.15 C A B
B
5.0
NOTE 4

2 MAX
(0.15) TYP 0.25
SEE DETAIL A GAGE PLANE

0.95 0.05 MIN

0 -8 0.55

DETAIL A
A 15

TYPICAL

4214853/B 03/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.

www.ti.com
 EXAMPLE BOARD LAYOUT
DB0028A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

28X (1.85) SYMM

1 (R0.05) TYP

28X (0.45) 28

26X (0.65)

SYMM

14 15

(7)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4214853/B 03/2018
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DB0028A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

28X (1.85) SYMM

(R0.05) TYP
1
28X (0.45) 28

26X (0.65)

SYMM

14 15

(7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4214853/B 03/2018
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
PJT0032A SCALE 1.700
TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK

7.2
B
PIN 1 ID 6.8
32 25
A

1 24

7.2 9.2
TYP
6.8 8.8

8 17

9 16

0.45
32X
0.30 28X 0.8
0.2 C A B
4X 5.6

1.2
1.0
C

SEATING PLANE

0.09-0.20 0.1 C
TYP
SEE DETAIL A

0.25
GAGE PLANE (1)

0.75
0.15
0 -7 0.45
0.05
DETAIL A
DETAIL A
SCALE: 15

TYPICAL

4220861/A 07/2023
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MS-026.

www.ti.com
 EXAMPLE BOARD LAYOUT
PJT0032A TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK

SYMM
32 25
32X (1.5)

1
24

32X (0.55)

SYMM
(8.4)

28X (0.8)

8 17

(R0.05) TYP

9 16
SEE DETAILS

(8.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

EXPOSED EXPOSED
METAL METAL

METAL SOLDER MASK SOLDER MASK METAL UNDER

OPENING SOLDER MASK
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED

SOLDER MASK DETAILS

4220861/A 07/2023
NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PJT0032A TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK

32 25
32X (1.5)

1
24

32X (0.55)

SYMM
(8.4)

28X (0.8)

8 17

(R0.05) TYP

9 16
SYMM

(8.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:8X

4220861/A 07/2023
NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.

www.ti.com
 IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
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