FlexNoC Training

CLOCKS & RESET

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Job Title Job Title Job Title
FlexNoC clocking concept
Configurable for all industry-common clocking and reset schemes

SoC signals
• Defines synchronous / asynchronous domains in clock
the system enable
Clock • A parent of one or several clock managers reset
regime NoC
clock
manager
• Subset of one clock regime, at least one per
power domain
Clock sysNet
• Can generate divided clocks & clock enable
manager
g g g g
• Subset of clock manager
• Clock relationship with the root clock g g g g
Clock • Type : Root, static, dynamic, copy of u u u
domain u

g=gater u=unit

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In FlexNoC tool

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Clock gaters automatically infer by FlexNoC

Clock gaters for automatic unit level

clock gating

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Clock Gating Strategy
Level Which DFFs Enable Source
Local Gating Datapath register Synthesis tools

Global clock gating Control logic registers FlexNoC infers clock gating units from links, NIUs, and
(unit-level) pseudo-switches
An IP unit that is not processing a packet is completely
gated, it is ungated when a packet reaches the IP unit
« On the fly » clock gating
• Wake-up within cycle
• no throughput or latency impact

Root Clock Gating Clock domain level RTL – System level

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Smart Clock gating
• Smart Clock gating
• Only logic that is actively processing a packet is clocked.
• Gating is done “on-the-fly” and no extra latency is introduced.

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Enable signal part of the clock bundle
• Enable is a data signal synchronized with root clock
– HIGH for every rising edge of divided clock
– LOW for all edges of root clock not coincident with rising edge of divided clock.

• Enable only used in sub-edge clock adapters

– Otherwise removed at synthesis time.

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Clock adapter units automatically inferred
big
• No relationship between clocks
• Metastability handling
Asynchronous • gray coded read/write
counters
• Synchronizer cells

• Clock edges synchronized

HW cost

• Either clock may be enabled for

a cycle during which the other
Synchronous is not
• Minimal data buffering (simple
write and read counters)

• Clock edges synchronized

• All edges of lower frequency
small

clock are coincident with

SubEdge enabled edge of higher
frequency clock
• No buffering, no metastability

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Types of synthezised clock adapter units
Clock domain relationship Type of clock adapter generated

Regime 1 ↔ Regime 2 Asynchronous

Root ↔ Root No clock adapter
Root ↔ Static SubEdge
Root ↔ Dynamic SubEdge
Root ↔ Dynamic wihout Enable Synchronous

Static divX ↔ Static divY SubEdge if X%Y==0 or Y%X==0 else Synchronous

Static ↔ Dynamic Synchronous

Static ↔ Dynamic without Enable Synchronous

Synchronous unless one clock has been parameterized as having a

Dynamic ↔ Dynamic
subedge relationship to the other, in which case SubEdge

Dynamic ↔ Dynamic without Enable Synchronous

Dynamic without Enable ↔ Dynamic without Enable Synchronous

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FlexNoC Asynchronous bridge block diagram

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FlexNoC Asynchronous bridge block diagram

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 2 cycle path in downstream domain
because 2 cycles are required for
upstream write pointer settling downstream
domain domain
set_max_delay 2x
downstream clock period

likely critical
paths
DATA

encoder
Gray

decoder
Gray
write ctr

empty
full
decoder
Gray

encoder
Gray
read ctr

Gray set_max_delay = 1 launch clock period to

coded avoid skew in Gray coded pointers from
pointers exceeding a full sending clock cycle

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Synchronized clock domain crossing timing
constraints

fast clock Q to slow clock D:

1 fast clock period

slow clock Q to fast clock D:

1 fast clock period

FlexNoC automatically instantiates a forward/backward pipe stage register

in the slow clock domain for datapaths sent to and received from faster
clock domains

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Sys net bundle signals
The Sys net interface is universal between
SoC signals clock managers, gaters, and units
clock
enable Clk ↓ clock (gated)
reset Clk_ClkS ↓ source clock (ungated)
Clk_En ↓ enable (generated)
clock Clk_EnS ↓ source enable (ungenerated)
manager
Clk_RstN ↓ reset the flops required for NoC functionality
Sys nets Clk_RetRstN ↓ reset retention flops (not asserted when resetting logic
in a power domain after it is powered up)
Clk_Tm ↓ test mode – disables unit level clock gating for jtag
g g g gater scan test
Pwr_Idle ↑ no clock is needed - based on the state of the units,
anded from leaves, pipelined through gaters
g g g g
Pwr_WakeUp ↑ data is to be sent – triggers enables, orred from
u u u unit leaves, fully combinatorial
Async clock adapter signals
transport
signals a classic async clock adapter supporting
<n> parallel cycle-interleaved channels

Rx

Data_<n> ↓ data transport signals except for Vld, Rdy, and Press
async
RdPtr_<n> ↑ selection of stored word in Rx unit to be sent
clock
adapter RdCnt ↑ gray-encoded read counter
signals WrCnt ↓ gray-encoded write counter
Urgency ↓ configurable urgency of stored pending packets
Tx Press ↓ configurable pressure of Data transport

transport
signals
FlexNoC Reset strategy
• Configured in RTL export option
• ResetPolicy.resetRegisters
– ALL : all DFFs in the design are reset
– Minimal : only state machine DFFs ensuring a proper start of the design are reset

• ResetPolicy.resetDffPin
– Synchronous
• DFFs use synchronous reset pin
– Asynchronous
• DFFs use asynchronous reset pin

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Out of reset :
• Synchronous to the clock

• Asynchronous

• Reset de-assertion while clock is cut

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Out of reset :

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Thank you

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