ch8 DFT
ch8 DFT
Introduction
Ad-Hoc Approaches
Full Scan
Partial Scan
2
Design For Testability
Definition
Design For Testability (DFT) refers to those design
techniques that make test generation and testing cost-
effective
DFT deals with ways of improving
Controllability
Observability
DFT Methods
Ad-hoc methods
Cost of DFT
Pin count, area, performance, design-time, test-time
3
Testability
4
What limits application of DFT ?
5
DFT is Important for
Successful Production
Certain DFT techniques are widely and
successfully used
Scan
Boundary Scan
Test compression
BIST
6
Ad-Hoc Design For Testability
Design Guidelines
Avoid redundancy
Avoid asynchronous logic
Avoid clock gating (e.g., power control, ripple counter)
Avoid large fan-in
Disadvantages of ad-hoc methods
Circuit too large for manual inspection and test
generation.
Not too many testability experts to consult.
High fault coverage not guaranteed
7
Ad-Hoc DFT Techniques (I)
Test Points
Employ test points to enhance controllability and
observability
Initialization
Design circuit to be easily initialized
Monostable multivibrators
Disable internal one-shots during test
Delay
element
One-shot signal is hard to predict
8
Ad-Hoc DFT Techniques (II)
Partition counters / shift-registers
Partition large counters and SR into smaller units
9
Test Point Insertion
0 w
C1 MUX C2
1
CP
CP_enable
Inserted circuit for controlling line w
Problems of CP & OP
12
Shift Registers for Control
Point Insertion
13
Control Point Selection
Impact
The controllability of the fanout-cone of the
added point is improved
Possible candidates
Control, address, and data buses
Enable / Hold inputs
Enable and read/write inputs to memory
Clock and preset/clear signals of flip-flops
Data select inputs to multiplexers and
demultiplexers
14
Observation Point Selection
Impact
The observability of the transitive fanins of the added
point is improved
Common choice
Stem lines having high fanout
Global feedback paths
Redundant signal lines
Output of logic devices having many inputs
MUX, XOR trees
Output from state devices
Address, control and data buses
15
Example: Partitioning Counter
Introduction
Ad-Hoc Approaches
Full Scan
Partial Scan
17
What Is Scan ?
Objective
To provide controllability and observability
at internal state variables for testing
Method
Add test mode control signal(s) to circuit
Connect flip-flops to form shift registers in
test mode
Make inputs/outputs of the flip-flops in the
shift register controllable and observable
Types
Internal scan
Full scan, Partial scan, Random access, etc.
Boundary scan
18
Revisit Sequential Circuit
Model
PI PO
Combinational Parts
19
Scan Architecture
PI Combinational Parts PO
0
1 Scan in
Scan out
Normal/test clock Normal/test switch 20
Scan Architecture In Normal
Mode
PI Combinational Parts PO
0
1 Scan in
Scan out
Normal clock Switch=1 (Normal mode) 21
Scan Architecture In Scan
Mode
PI Combinational Parts PO
0
1 Scan in
Scan out
Test clock Switch=0 (Test mode) 22
Applying Tests for Scan
Circuits
Phase I (test the scan chain):
Shift test
Targets the scan flip-flops.
Phase II (applying test patterns for
combination circuits):
Target the single stuck-at faults in the
combinational circuit.
Test vectors are generated by a combinational
ATPG.
23
Phase I: Shift test
24
Phase II: Combinational Test
25
Scan Test Example
26
Scan Example (Assert PI)
0
X 1 Scan in=X
Scan out
Test clock Switch=0 (Test mode) 27
Scan Example (Scan In)
0
0 1 Scan in=0
Scan out=X
Test clock Switch=0 (Test mode) 28
Scan Example (Scan In)
0
1 1 Scan in=1
Scan out=X
Test clock Switch=0 (Test mode) 29
Scan Example (Scan In)
0
0 1 Scan in=0
Scan out=X
Test clock Switch=0 (Test mode) 30
Scan Example (Normal Mode)
0
1 1 Scan in
Scan out
Normal clock Switch=1 (Normal mode) 31
Scan Example (Scan Out)
0
1 1 Scan in=1
Scan out=0
Test clock Switch=0 (Test mode) 32
Scan Example (Scan Out)
0
0 1 Scan in=0
0
1 1 Scan in=1
1st vector
2nd vector
3rd vector
last vector
MUX
SI Q
CK D flip-flop
Q1
D Master latch Slave latch
D Q D Q Q2
SC
SI CK Q CK Q
CK1
CK2
38
Two-Port Dual-Clock Scan Flip-
Flop
Less performance degradation than MUXed scan FF
D Q1 Q2
CK1
SD
Normal
CK1
mode
CK2
CK2 CK1
mode
Scan
CK2
39
LSSD Single-latch Design
(1977 IBM)
LSSD: level-sensitive scan design
Can be used for latch designs
L*
D=D1 G1 G3
L1
C=CK1
L*
G4
SI=D2 G8 G7 L2
A=CK2 B=CK4
G2
G5
D*=D3
C*=CK3
G6
40
Symbol of LSSD Scan FF
L*
D D1 Q L1 (normal level-sensitive
SI D2
latch output)
C CK1
A CK2
L*
D1 Q L2
D* D2
B CK1
C* CK2
41
Comparing Three Scan Cell
Designs
Disadvantage Advantage
43
Tri-State Buses
Bus contention occurs
when two bus drivers
force opposite logic
values onto a tri-state
bus.
During the shift
operation, contention
can happen with
continuous 1’s as in
the example.
44
Tri-State Buses Fixes
when SE = 1
EN1=1, EN2=0 and EN3=0 (only D1 enabled).
The bus keeper is added to avoid uninitialized Z.
45
Bi-Directional I/O Ports
Fix
46
Gated Clocks
47
Derived Clocks
Fix
48
Combinational Feedback
Loops
Since the value stored in the loop cannot be
controlled or determined during test, this can
lead to an increase in test generation
complexity or fault coverage loss.
The best way is to rewrite the RTL code.
Fix
49
Asynchronous Set/Reset
Signals
Asynchronous set/reset signals of scan cells that are
not directly controlled from primary inputs can
prevent scan chains from shifting data properly.
To avoid this problem, these asynchronous set/reset
signals are forced to an inactive state during the shift
operation.
Fix
50
Scan Design Flow
Original Design
Testable Design
Scan synthesis
Scan configuration
Scan replacement
Scan Design
Scan verification
51
Scan Design Steps (I)
52
Scan Design Steps (II)
Scan Extraction
Is the process used for extracting all scan cell
instances from all scan chains specified in the
scan design
Scan Verification
A timing file in standard delay format (SDF) which
resembles the timing behavior of the
manufactured device is used to
Verifying the scan shift operation
Verifying the scan capture operation
53
Four Processes for Scan
Synthesis
Scan Configuration
The number of scan chains used
The types of scan cells used to implement these scan chains
Which storage elements to exclude from the process
How the scan cells are arranged
Scan Replacement
Replaces all original storage elements in the testable design with
their functionally-equivalent scan cells
Scan Reordering
The process of reordering the scan chains based on the physical
scan cell locations, in order to minimize the amount of
interconnect wires used to implement the scan chains
Scan Stitching
Stitch all scan cells together to form scan chains
54
Physical Design of Scan with
Standard Cells
scan in
scan out
TC
56
Scan-Chain Reordering
Scan-chain order is often decided at gate-level without
knowing the cell placement
Scan-chain consumes a lot of routing resources, and
could be minimized by re-ordering the flip-flops in the
chain after layout is done
Scan-In Scan-In
Scan-Out Scan-Out
Scan cell
Scan Synthesis
Scan Design
59
RTL Scan Design Repair – An
Example
Original design
60
RTL Scan Design Repair – An
Example
Atuomatic repair at the RTL using TM
always @(posedge clk)
if (q == 4'b1111)
clk_15 = 1;
else
begin
clk_15 = 0;
q = q + 1;
end
assign clk_test = (TM)? clk : clk_15;
always @(posedge clk_test)
d = start;
(a) Generated clock (RTL code) (b) Generated clock repair (Schematic)
61
Problems with Scan Design
Area overhead
Increased gate count
Increased routing area
Performance degradation
Extra gate delay due to the multiplexer
Extra delay due to the capacitive loading of
the scan-wiring at each flip-flop’s output
Long test application time.
Not applicable to all designs.
Must follow the scan design rules.
High power dissipation during testing. 62
Long Test Times for Scans
64
Scan Chain Debug
65
Outline
Introduction
Ad-Hoc Approaches
Full Scan
Partial Scan
Cycle Breaking Techniques
BALLAST approach
66
Partial Scan
Basic idea
Select a subset of flip-flops for scan
Lower overhead (area and speed)
Relaxed design rules
Storage elements on the data path are left out of the
scan cell replacement process
Cycle-breaking technique
Cheng & Agrawal, IEEE Trans. On Computers, April 1990
Select scan flip-flops to simplify sequential ATPG
Overhead is about 25% off than full scan
Timing-driven partial scan
Jou & Cheng, ICCAD, Nov. 1991
Allow optimization of area, timing, and testability
simultaneously
67
Full Scan vs. Partial Scan
scan design
primary
primary outputs
inputs 1 2 4 5 6
primary
inputs
3
Graph of the circuit
L=3
1 2 4 5 6
L=2
L=1
Depth D=4
70
Test Length In A Sequential
Circuit
Notations:
D: sequential depth (The distance along the longest
path in its graph)
L: maximum length of any cycle
Test Generation Complexity
For a cycle-free circuit (e.g., pipeline structure), the
complexity is similar to that of a combinational circuit
In a circuit with depth D, any single fault can be tested
by at most D vectors
The length of a test sequence ~ D·2L
71
Partial Scan For Cycle-Free
Structure
Select minimal set of flip-flops
To eliminate some or all cycles
72
Partial Scan Design
PI PO
PPI PPO
3
Scan Out
Scan In
1 2 4 5 6 Scan In
73
Clocking Schemes for Partial Scan
Circuits
Scheme I:
Use a separate scan clock
PO
NS
sys_clk
Comb.
scan in
Logic
scan_clk
scan out
PI PS
74
Scheme II:
Gate the system clock
PO
NS
gated clock
sys_clk
Comb.
scan in
Logic
en_scan
scan out
PI PS
75
Partial Scan w/ a Separate Scan
Clock or Gated Clock
Require multiple clock trees
Extra clock signal routing efforts
Test generation is easier
Scan FFs are fully controllable and observable.
Test generation procedure:
Scan FFs are removed and their I/O’s are added to the
PO/PI lists.
A sequential ATPG is used for test generation.
The vector sequences are then converted into scan
sequences
Each vector is preceded by a scan-in sequence to set
the states of the SFFs.
A scan-out sequence is added to each vector
sequence.
76
Test Generation Model – A Separate
Scan Clock or Gated Clock
PI PO
scan_in
PPI PPO
PS NS
78
Test Length Statistics For The
TLC Circuit
200
150
No. of Without Scan
100
Fault
50
0
0 50 100 150 200 250
Test length
200
150
No. of 9 scan flip-flops
100
Fault
50
0
0 5 10 15 20
Test length
200
150
No. of 10 scan flip-flops
100
Fault
50
0
0 5 10 15 20
Test length
79
Clocking Schemes for Partial Scan
Circuits
Scheme III:
Using the system clock as a scan clock but without
gating the the clock
PO
NS
sys_clk
Comb.
scan in
Logic
en_scan
scan out
PI PS
80
Using System Clock for Scan
Operation
81
Timing-Driven Partial Scan
Not B-structure !
C2 C3
register
83
Example: A Sequential Circuit
Combinational clouds: C1, C2, C3, C4
Registers: R1, R2, R3, R4, R5, R6
This example is not balanced !
B
A
R2 C2 R5
C1 C4
R1 C3 R4
R6
R3
84
BALLAST-based Partial Scan
This circuit becomes balanced after scanning registers R3 and R6
B
A
R2 C2 R5 PO
C1
C4
R1 C3 R4
Si
.....
.....
R 6
.....
.....
Become pseudo-PI .....
after scan R3 .....
R3
.....
..... HOLD control
(for test)
So
85
Test Procedure for B-Structure
Depth of a B-structure
The largest of number registers on any path between
any two combinational clouds
Test Procedure
Step 1: Scan in the test pattern for scan flip-flops
Step 2: Apply primary input pattern
Step 3: Clock the registers d times (where d is the
depth), while holding patterns at PI and scan flip-flops
Step 4: Place the scan flip-flops in normal mode for one
clock (capture results into scaned FFs)
Step 5: Observe the primary output response
Step 6: Simultaneously scan out the results in the scan
paths and scan in next scan pattern
86
Advantage of BALLAST
A
A
R2 C2 R5
C
2
C1
C4
C
1
C
R1 C3 R4 4
C
3
Depth = 2
87
Trade-Off of Area Overhead v.s.
Test Generation Effort
CPU
Time
Partial Scan
Allows the trade-off between test generation effort and
hardware overhead to be automatically explored
Breaking Cycles
Dramatically simplifies the sequential ATPG
Limiting The Length of Self-Loop Paths
Is crucial in reducing test generation effort for large
circuits
Performance Degradation
Can be minimized by using timing analysis data for flip-
flop selection
89