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This is the author's version which has not been fully edited and
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Digital Object Identifier 10.1109/ACCESS.2023.0322000

Application of Machine Learning in

FPGA EDA Tool Development
PINGAKSHYA GOSWAMI1 , (Student Member, IEEE), DINESH BHATIA2 , (Senior Member,
IEEE)
1
Department of Electrical and Computer Engineering, The University at Texas at Dallas, Richardson, TX 75080 USA (e-mail: [email protected])
2
Department of Electrical and Computer Engineering, The University at Texas at Dallas, Richardson, TX 75080 USA (e-mail: [email protected])
Corresponding author: Pingakshya Goswami (e-mail: [email protected]).

ABSTRACT With the recent advances in hardware technologies like advanced CPUs and GPUs and the
large availability of open-source libraries, machine learning has penetrated various domains, including
Electronics Design Automation (EDA). EDA consists of multiple stages, from high-level synthesis and
logic synthesis to placement and routing. Traditionally, estimating resources and areas from one level of
design abstraction to the next level uses mathematical, statistical, and analytical approaches. However, as the
technology node decreases and the number of cells inside the chip increases, the traditional estimation meth-
ods fail to correlate with the actual post-route values. Machine-learning (ML) based methodologies pave a
strong path towards accurately estimating post-route values. In this paper, we present a comprehensive
survey of the existing literature in the ML application field in EDA, emphasizing FPGA design automation
tools. We discuss how ML is applied in different stages to predict congestion, power, performance, and
area (PPA), both for High-Level Synthesis (HLS) and Register Transfer Level (RTL)-based FPGA designs,
application of design space exploration and application in Computer-Aided Design (CAD) tool parameter
settings to optimize timing and area requirements. Reinforcement learning is widely applied in both FPGA
and ASIC physical design flow, a topic of discussion in this paper. We also discuss various ML models like
classical regression and classification ML, convolution neural networks, reinforcement learning, and graph
convolution network and their application in EDA.

INDEX TERMS Machine Learning, Electronic Design Automation, FPGA

I. INTRODUCTION

S the technology node size decreases due to Moores basic estimations like congestion [3], [4] and wirelength [6].
A Law [1], and Dennard’s scaling [2], more and more
transistors are fitted per unit area inside the integrated cir-
These methods generally solve every problem from scratch
and do not utilize any experience or knowledge.
cuit (IC) than ever before. With the decrease in technology On the other side of the technology world, another domain
size, the tools used to design the ICs are becoming more is emerging pretty fast and has shown its application in
complex. Electronic Design Automation is the branch of almost every aspect of human life known as Machine Learn-
science or technology that deals with the tools used to design ing (ML). ML has seen its applications in various domains
integrated circuits. IC design is a highly complex process like image recognition [7], [8], natural language processing
consisting of multiple stages with an average turnaround time [9]–[11], audio and signal processing [12]–[14], etc. This
ranging from a few days to a few years. While designing is because the hardware used for training the models, like
an IC, it is always a good practice to estimate the power, GPUs, has progressed significantly with multiple processors
performance, area, congestion, and wirlength of the design fabricated inside one die along with easy availability of open
down the flow in an early stage. Traditionally, this is done source training frameworks like Tensorflow, Scikitlearn, and
using statistical, mathematical, or analytical methods [3]– Pytorch [15]–[17]. ML has also penetrated the EDA domain
[5]. Although the analytical and mathematical models get in the last five to six years. All the problems that were
pretty accurate estimates, these methods are computationally previously solved using analytical methods [3]–[6], [18] are
expensive and consume a lot of time (few hours) to perform now reframed as ML problems. The issues that took a few

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Goswami et al.: Application of Machine Learning in FPGA EDA tool development

ML in EDA

Congestion PPA CAD Tool Physical and

Prediction HLS DSE Logic Synthesis
Estimation Parameter

Image GCN Timing RL

ML Based
Based Based Recommender Synthesis

Regression Transfer RL
Analytical Based Learning
PPA Placement
Recommender
ML Based Cross ML + Meta RL
Platform Heuristics Routing

FIGURE 1. Different Categories in which ML is applied in FPGA EDA Flow

minutes to hours using analytical or mathematical methods parameter-tuning effort, Kwon et al. [32] propose a CAD
can now be solved using ML-based pre-trained models within tool parameter recommender system that involves learning a
a few seconds. Machine learning has found its application collaborative prediction model through tensor decomposition
in almost all stages of IC designs, which include timing, and regression. ML-based design space exploration of HLS
power, and area estimation; routing congestion estimation, designs is discussed in [33]–[36]. [30] uses Bayesian opti-
both using classical ML and deep learning methods; design mization to perform DSE to optimize an HLS-based CNN
space exploration; CAD tool parameter tuning; Wirelength architecture, while Carloni [35] uses transfer learning to
(WL) estimation and lithographic hotspot detection. For this optimize the designs during DSE. Congestion estimation is
paper, we have surveyed the literature in the ML application another problem that machine learning can solve accurately
domain in EDA tool design and optimization, focusing on and quickly. In [37], [38], the congestion estimation of RTL
FPGA EDA tools. We have clustered the application in the designs on FPGA uses classical regression-based ML modes.
following five categories: [39] predicts the routing congestion of HLS designs using
i. Power, performance and area prediction in RTL and ML, while [40], [41] uses convolution neural network(CNN)
HLS Designs methods to forecast the congestion on post-placed images of
ii. Design Space Exploration (DSE) logic netlists.
iii. CAD tool optimization using ML As shown in Fig. 1, ML can be applied at different stages
iv. Congestion estimation in HLS and RTL designs of the logical and physical design flow, from quality of
v. ML in FPGA Phyiscal Design Flow results (QoR) estimations to hyperparameter selection and
design space exploration. In this paper, we comprehensively
In Fig. 1, we have shown how ML is applied at various
reviewed how ML is applied in different stages of FPGA
stages of FPGA EDA flow. The figure also shows the various
physical design flow, along with some insights into future
subcategories and ML algorithms applied at each flow stage.
developments and open research areas. The rest of the paper
We have discussed both analytical and mathematical-based is organized as follows: Section II, we discuss the other
PPA estimators [19]–[21] and ML-based estimators [22]– works, where application of ML in EDA tool development
[26], where the design entry is either HLS or RTL input. for both ASICs and FPGAs have been studied; in Section
The prediction models use traditional ML methods like re- III, we discuss the various ML models applied in EDA tool
gression and classification and advanced methods like deep design, which includes classical regression and classification,
learning and graph convolution [26], [27] to estimate the CNN, reinforcement learning, transfer learning, and graph
PPA of a circuit. For autotuning and recommendation of convolution network (GCN). From Section IV to Section
CAD tool parameters [28]–[30]. Bayesian methods are used VIII, we discuss in detail the five categories in which ML is
to select the hyperparameters of the CAD tools. Yanghua applied for FPGA CAD. Finally, Section IX summarizes the
et al. perform the feature selection to reduce the number of paper’s contents and looks into future trends and directions.
FPGA CAD parameters to consider [31] from 80 to 8 features
without compromising the quality of results. To reduce the
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Goswami et al.: Application of Machine Learning in FPGA EDA tool development

II. RELATED SURVEYS IN ML BASED EDA TOOL is available that discusses the existing work of ML-based
DEVELOPMENT FPGA CAD tool design. To address these loopholes, we
There are few survey papers in which different works in created this detailed survey in which we exclusively review
the ML application domain in EDA have been studied [42]– various works in which ML has been applied to multiple
[48]. Most of these works are either too generic for ASIC FPGA CAD tool design stages. We discuss both ML-based
[42], [45] or too specific to a particular domain [43], [44], HLS tools and ML-based RTL tools for FPGAs. This paper
[48]. These papers discuss how ML has been applied to surveys the recent advancements in GNN and RL, which have
predict or improve the CAD tools’ performance to design been widely applied to the synthesis, placement, and routing
ASICs. Discussion of ML-based FPGA CAD tools has been of FPGA circuits.
neglected in survey papers. [42] is a comprehensive survey
in which they have performed a detailed analysis of how ML III. BASICS OF MACHINE LEARNING
can be applied to various stages of ASIC design flow. They ML algorithms are broadly divided into two classes:
discussed ML applications for ASIC physical design, power
(i) Supervised Learning
delivery network and IR drop analysis, lithography and mask
(ii) Unsupervised Learning
production, analog IC design, device sizing automation, and
verification and testing. As we can see here, in this work, all Most of the ML models used in EDA fall under supervised
the predictions are targeted for nanometer scale ASIC physi- learning, including regression, classification, Convolution
cal design flow. They have minimal discussion on the FPGA Neural Networks, and Graph Convolution Network. The
front, that too on the HLS part, but nothing has been dis- CAD tool optimization or Design Space Exploration tools
cussed about prediction in various stages of FPGA physical use Bayesian learning and the Gaussian process to set the
design. In [43], the authors surveyed exclusively on applying hyperparameters of the CAD tools. In Table 1, we have
graph neural network (GNN), ASIC physical design flow. mapped the different EDA applications to the ML models
The paper [43] discusses primarily the theoretical details of used.In this section, we have discussed the ML algorithms
GNN, and the discussion on applying GNN on EDA has mentioned in column 1 of Table 1 in detail.
been minimal. In another work, [44], the authors discussed (i) Linear Regression: Linear regression is a method to
explicitly the application of ML in analog circuit design. find relationship between two continuous variables; one
They mentioned the ANN ANN-based analog IC design is independent, and the other is dependent. Linear re-
process, the hybrid analog IC design automation process, and gression tries to create a statistical relationship that may
the application of ANN and RL in analog IC manufacturing. not always be deterministic. Linear regression tries to
In [45], the authors briefly discuss the application of ML obtain a straight line that shows the relationship between
in the placement and routing of ASIC designs. There is no the independent and the dependent variable. For most of
mention of FPGAs, HLS, and recent methods like CNN, the linear regression models, the error is measured using
GNN, and RL. They only discuss wirelength estimation in the least squared error. A linear regression line has an
placement and Design Rules Check (DRC) hotspot detection equation of Y = a + bX, where X is the explanatory
in post-routed circuits. Paper [46] and [49] discuss hotspot variable and Y is the dependent variable. The slope of
and DRC violation prediction using ML in ASIC circuits and the line is b, and a is the intercept, which is determined
static timing analysis using ML. These two papers are more during model training.
of a roadmap paper than a survey paper. These papers discuss (ii) Random Forest Regression(RF): Random forest is a
in what different domains ML can be applied to future IC supervised learning method that uses ensemble meth-
designs. Similar to [46], [47] is a roadmap that discusses ods for learning. Ensemble learning is a technique that
performance limitations of traditional compute and storage combines multiple weak learners to create a strong
systems and the systems and infrastructure considerations learner. In random forests, these weak learners are de-
for performing machine learning at scale. This paper also cision trees. The outputs from the individual learners
briefly discusses how ML can be applied to solve functional are averaged to generate the final output. Random forest
verification and debug problems. Even though [48] is not belongs to the bagging class of learners where, during
a proper survey paper, the authors discuss how RL can be training, data samples are selected at random without
applied to solve various circuit design problems like DRC replacement. Bagging makes each model run indepen-
violations, layout, and routing issues. This work profoundly dently and then aggregates the outputs at the end without
focuses on using Reinforcement Learning (RL) to solve post- preference for any model. Because of the introduction of
route violation issues. the bagging method, the chances of overfitting are less
As the above discussion shows, most existing surveys are in a random forest. Random forest is a very fast training
highly focused on IC development or EDA tools for ASICs. method because each tree can be trained in parallel, and
Even though there are many recent works in which ML the inputs and outputs of each tree are not related to
has been applied to solve various FPGA physical design one another. To summarize, Random Forest Algorithm
problems, their discussion has been limited to the "Related merges the output of multiple Decision Trees to generate
Works" section of the papers only. No comprehensive survey the final output.
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Goswami et al.: Application of Machine Learning in FPGA EDA tool development

TABLE 1. ML models and their applications in EDA flow

ML Model Application Reference

• Power Prediction
• HLS Area and Timing
• Congestion
Regression [22], [25], [37], [39], [36], [38], [50], [51],
• DSE
[52]
• Cross Platform
• Performance Estimation
Analytical Power, Performance and Latency estimation [19], [21] [20]
GCN HLS QoR Estimation [26], [27]
Transfer Learning DSE [35], [53]
Reinforcement Learning DSE [26]
Decision Tree DSE [33], [34]
GAN Routing congestion [40], [41]
Baysesian Opt CAD tool parameter [29], [30]
Classification CAD tool parameter [28], [54], [55]
Reinforcement Learning Place and Route [56]–[59] [57], [58], [60], [61]
Graph Neural Network Power [62], [63], [64]

(iii) Multivariate Adaptive Regression Splines (MARS): which fixes the error of the previous tree. The XGB
Multivariate adaptive regression splines [65], an al- uses a gradient decent algorithm on the loss function
gorithm that automatically creates a piecewise linear to minimize the error generated by the previous trees.
model which creates a nonlinear model by combin- The XGB method keeps adding trees one after another
ing multiple small linear functions known as steps. iteratively until there is no improvement in the loss. The
In MARS, non-linearity is introduced by using step loss function used is either sum of squared error (SSE)
functions. There are no polynomial terms in the MARS or mean square error (MSE) [66].
equation. Equation 1 shows the linear stepwise equa- (vi) Graph Convolution Network(GCN): With the wide
tion: application of deep learning, neural networks are an
effective and efficient model for tasks like classification
yi = β0 + β1 C1 (xi ) + β2 C2 (xi ) + . . . + βd Cd (xi ) + ϵi , and regression. However, neural networks like ANN
(1) and CNN only take vectors or tensors as input data,
MARS is an adaptive procedure for regression and is which makes it difficult to work on graphs. Defferrard
well-suited for high-dimensional problems (i.e., many et al. generalize convolutional neural networks from
inputs). The bends in the step functions are known as regular grids (e.g., images) to general graphs via graph
“knots”. If there are multiple knots present in the MARS convolutional filters [67]. Later, Kipf and Welling sim-
equation, it may lead to overfitting. plify the convolutional operator and propose a graph
(iv) Multi Layer Perceptron based Regression (MLP): convolutional network [68]. Graph learning techniques
MLP-based regression models comprise multiple per- can be categorized into transductive and inductive set-
ceptrons known as neurons. This type of model falls tings. Under the transductive setting, the embedding of
into the feedforward class of artificial neural networks. each node is directly optimized, and thus, the training
Generally, Artificial Neural Networks (ANN)s are used process requires seeing all the nodes. The original GCN
for classification. But they can be used for regression, [67] is one kind of transductive approach. The induc-
too. MLP-based models are trained using a backprop- tive approaches learn a general rule from the training
agation algorithm. Each network consists of an input graphs through sample and aggregation of structural
layer of neurons, a few hidden layers, and an output information and node attributes. The learned model can
layer. The output of each function is linear. To make the be applied to unseen data.
output non-linear and emulate the real-world behavior, (vii) Reinforcement Learning(RL): Reinforcement learning
activation functions like “tanh”, “RELU” and “sigmoid” is an ML algorithm in which the machine tries to learn
are added. by itself. The machine repeatedly uses trial and error to
(v) Gradient Boost Regression (XGB): Similar to random learn from its own experience. To program the machine,
forest regression, Gradient boost regression is also an the programmer sets rewards for correct actions and
ensemble class of ML model. Boosting is a method of penalizes the machine for wrong actions. The goal of the
converting weak learners into strong learners. Unlike machine is to maximize the rewards. Unlike supervised
random forest regression, where we use fully grown learning, the training data of reinforcement learning
trees, in XGB, the trees are weak learners; hence, have no labels. By leveraging the power of search and
shallow trees can also be used for fast learning. In many trials, reinforcement learning is currently the most
boosting, each new tree is fit on a modified version of the effective way to hint at a machine’s creativity [69], [70].
original data set. XGB uses multiple trees in sequence, (viii) Bayesian Optimization: Bayesian optimization is an

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Goswami et al.: Application of Machine Learning in FPGA EDA tool development

both time and energy for the designers. Since global routing-
based congestion estimation cannot be estimated accurately
RTL Code for smaller technology nodes, researchers have developed
ML-based congestion estimation methods for FPGAs and
ASICs. They have used traditional regression models on RTL
netlists [37], [38] and HLS designs [39]. Other researchers
Logic
have addressed the FPGA congestion prediction problem
Synthesis
as Generative Adversarial Network (GAN) and CNNs [27],
[41]. In these models, the authors apply image-based GAN
and CNN algorithms to detect congestion hotspots on the
2D images of post-placed netlists. This section discusses the
Mapping
ML-based works to predict congestion on FPGA netlists. In
Fig. 2, we have shown a conventional FPGA/ASIC design
flow starting from the RTL code to the routing congestion
Features map level. On the right side, we have shown how ML can be
Placement applied right after the placement stage to get a quick estimate
of the post-route congestion value. The applied ML model
can be traditional regression/classification methods or image-
based models like CNN and GAN (generative adversarial
AI based prediction
Routing network).
ML/GAN/DNN

A. ROUTING CONGESTION PREDICTION USING

Predicted Congestion CLASSICAL ML MODELS
Routing
Congestion There are three recent works in which FPGA recent works in
which the FPGA routing congestion prediction problem has
been addressed as a regression problem [37], [38], [71]. The
FIGURE 2. Conventional FPGA Routing Flow and the AI based flow shown in authors divided the FPGA architectures into global routing
dotted line on right
cells called gcells, which consist of one CLB and one switch
box, and predict the routing congestion in each gcell. In
optimization technique that uses Bayes Theoram to [37], [38], the authors considered various intrinsic properties
find the global maxima or global minima of a non- of post-placed FPGA netlists like pin density, Wirelength
convex, non-linear, multi-dimensional function. It is Per Area (WLPA), Net Cut Per Region (NCPR) etc., as
highly suitable for optimizing functions consisting of their features to the regression model. Goswami et al. [71]
less than twenty dimensions. Bayesian optimization considered a total of nine features for their model, which
consists of two parts: a Surrogate Function, which uses include LUT and Flipflop utilization, incoming/outgoing and
the Bayesian model to model the objective function, and fully local nets in each gcells and relative location of each
an Acquisition Function to decide what dimension value gcell inside the FPGA device. All three works tested and
to sample next. Gaussian Process Regression is an ex- verified their models on ISPD 2016 [72] benchmarks. While
ample of an acquisition function. Bayesian optimization [37], [38] divided their dataset into 70% train and 30% test
is used in hyperparameter tuning of ML models and dataset, [71] predicted on individual benchmarks. To create
hyperparameter of CAD tools [29]. their models, the three works used conventional regression
methods like linear regression, random forest, and gradient
In the rest of the paper, we will discuss the various appli-
boost.
cations of ML in EDA flow.

IV. ML IN ROUTING CONGESTION ESTIMATION B. ROUTING CONGESTION PREDICTION IN HLS

Detailed routing is the most time-consuming stage in VLSI DESIGN
or FPGA design flow. Generally, the routing in VLSI is One of the major limitations of the current commercial HLS
divided into two stages: a) Global Routing and b) Detailed tools is that it cannot estimate routing estimation, even inac-
Routing. Congestions generally occur in the detailed routing curately. In [39], Zhao et al. address this issue by creating
stage, which results in a violation of DRC rules, and the an ML model that predicts routing congestion after the C-
circuit sometimes becomes unroutable. Routing congestion synthesis stage, i.e., before actual RTL synthesis. If high
can be measured accurately only after detailed routing has congestion is detected for a certain portion of the code, they
been completed, which takes a lot of time. Because of suggested methods to modify the high-level C/C++ code,
these reasons, predicting the approximate value of routing reducing congestion after routing. To do so, they converted
congestion before the actual detailed routing stage can save the HLS code into LLVM-IR [73] and backtracked each of
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TABLE 2. Classification of ML algorithms and their application in Congestion Estimation

Paper [37] [38] [39] [71] [40] [41]

Design Entry RTL RTL HLS RTL RTL RTL
ML Category Regression Regression Regression Regression GAN GAN
MAPE % 4.62 12.8 10.57 3.61 14.6 10.7
ML Model Used MLP Global Linear XGB RF GAN CGAN
Feature source Placed NL Placed NL LLVM IR Placed NL Image encoded Image encoded
Dataset ISPD2016 ISPD2016 Image processing IP ISPD2016 Custom VPR IP ISPD2016

the instructions on the IR code to the actual layout after the six works. Since post-route congestion is estimated after
routing. The back tracing is done in the following way: the placement stage of the FPGA physical design process,
Congested CLB → gate level netlist → RTL code → IR for RTL-based designs, features are extracted from the post-
code → HLS code placement netlists. Even for GAN-based designs, placement
Once the source of the instruction for the congested CLB is netlists are converted to images, and features are extracted
determined in the HLS code, features are extracted to create from those images. For example, in [41], encoded feature
a regression model. The regression model is later used to maps in high-definition images are created for pin density
predict the post-route congestion from the high-level C/C++ vertical and horizontal routing congestion from post-placed
and LLVM IR codes. netlists. Similarly, in [40], different color schemes are used
in post-placement images to represent routing channels, CLB
C. ROUTING CONGESTION PREDICTION USING GAN spots, multipliers, memories, IO blocks, and connectivity
BASED METHOD matrices. Row 6 in Table 2 represents the feature sources,
The work described in [41] and [40] addressed the routing while row 7 represents the datasets. Although all the work
congestion estimation problem as a conditional generative discussed in this section can accurately estimate the routing
adversarial network (CGAN) problem. In both works, the congestion, almost all the estimation is done only for CLB
authors transfer the routing congestion problem in large-scale levels. No work estimates routing congestion for DSPs or
FPGAs to an image-to-image problem and then use condi- BRAM, even though they consume a significant amount of
tional GAN to solve it. In [41], proposed a new placement- resources in modern designs. Also, none of the work is
based routing congestion prediction approach for large-scale properly integrated with open-source or commercial imple-
FPGA designs. The proposed approach adopts a new CGAN mentation tools. Easy integration of the prediction models
model, namely pix2pixHD, which performs high-definition with existing physical implementation tools is still an open
(HD) image translations for large high-resolution images. research direction.
With HD image translation, this approach can achieve high
prediction accuracy for large FPGA designs while relying V. ML BASED DESIGN SPACE EXPLORATION OF HLS
on well-engineered features that encode the placement and DESIGNS
connectivity information for large-scale designs. The main In High-Level Synthesis, there are various methods that the
contributions of [40] include selecting features only from designer can use to optimize their design in terms of area,
post-placed netlist image, estimation of the routing channel latency, and timing. The process by which the designer
utilization by forecasting the full congestion heat map instead achieve the best set of designs in term of area and latency by
of hotspots only, and integration with placement tool to esti- changing the parameters of the HLS tool is called “Design
mate routing congestion on the fly during placement. Both Space Exploration” (DSE). In HLS designs, there are three
tools can be easily integrated with open-source academic different ways known as “knobs”, which the designer can
placers like UTPLace and GPlace [74], [75] and achieve very use to optimize their designs [76]. The three knobs of HLS
high accuracy. designs are:
D. SUMMARY OF ROUTING CONGESTION WORK AND 1) Pragma-based local synthesis
FUTURE DIRECTIONS 2) Global Synthesis Options
The application of ML to solve congestion estimation can 3) Functional Unit Constraints
be broadly classified into two classes: (a) Using traditional The main challenge HLS users face is setting these knobs
regression methods and (b) Using image-based GAN meth- to obtain a design with the desired characteristics, consider-
ods. Also, the design entry to the tool can be either RTL- ing that the total number of knob settings is extremely large.
based or HLS-based. In Table 2, we have summarized all the There are both traditional optimization methods like simu-
ML-based congestion estimation tools for FPGAs and the lated annealing based, genetic algorithm based, ant colony
models used for prediction. In most cases, the performance optimization and gradient decent [33], [77], [78] based meth-
of the post-route congestion estimation tool is measured in ods and machine learning based methods to perform DSE
terms of mean absolute percentage error (MAPE). In row 4 [33]–[36], [79], [80]. Some of the works combine both tradi-
of Table 2, we present the average error reported in each of tional methods and ML-based methods [33]. Thus, the goal of
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points, thereby reducing the design space significantly.

Active Learning
Initial Training
Training B. DESIGN SPACE EXPLORATION USING TRANSFER
ML Predictor
LEARNING
Initial Samples Predicting Transfer learning is widely applied in DSE of HLS. In
results for all
designs
Refinement transfer learning, the model is trained on one set of designs,
Samples
and with minor modifications, the model can be deployed on
another new set of designs for inference. In [35], [82] [53],
ML Predictor Explorer/Sampler the authors apply transfer learning to move knowledge from
a set of previously explored source designs to an unexplored
target design. In [53], ML is not used, but the authors use
a novel method, where mapping from the source design to
FIGURE 3. High Level diagram of ML based DSE [36]
the target design is done analytically for selecting the source
design and the source directives. Here, the authors propose
a code similarity matching model using string-similarity al-
HLS DSE is not to find a single solution but a set of designs, gorithms to quantify the similarity in terms of computational
typically called Pareto optimal designs or microarchitectures, patterns that exist between a source design (from a library
which form the Pareto frontier (P̄ ). P̄ can be defined as a capturing prior knowledge) and the target design. After iden-
set of dominating designs P̄ = d1 , d2 , ..., dn such that for tifying similar designs, the next step is selecting the designs
any design di ∈ P̄ ; A(di ) ≤ A(dq ) and L(di ) ≤ L(dq ) with similar pragma settings. The authors select the Pareto-
[76]. There are twelve (Table 3) very recent works in which optimal curve among the pragma settings in a source design
ML is applied to find the Pareto optimal curve in DSE for and translate the Pareto-optimal curve from the source design
HLS. The researchers mostly use regression and transfer and to the corresponding ones in a target.
active learning-based methods to perform DSE. In Fig. 3, we In [35], Kwon et al. apply transfer learning (TL) to speed
have shown the high-level flow of ML application to solve up the DSE process in HLS designs. The main theme of
the DSE problem, which is common to most of the discussed this paper is to extract the knowledge obtained from the
papers. As shown in Fig. 3, most of the ML-based DSE previously explored spaces of source designs and apply it
tools initially synthesize a portion of the designs in real-time, to the early stage of DSE of a new target design. In [82],
which becomes the sample training dataset (shown in gray the authors train a set of DSE points on ASIC, and using
can in Fig. 3) and the rest are done using ML-based approach ML, they predicted the performance of the same designs
(shown in green can in Fig. 3) on FPGA. They have transformed the learning model from
ASIC DSE to predict on FPGA DSE.
A. DESIGN SPACE EXPLORATION USING STANDALONE
ML C. DESIGN SPACE EXPLORATION USING
In [36] and [79], the authors use traditional ML algorithms to COMBINATION OF ML AND METAHEURISTICS
find the Pareto optimal curve. While [36], the authors have METHODS
proposed a transductive experimental design (TED) based There are a few works [33], [34], which is a fusion of
learning method to speed up the design space exploration both metaheuristics-based methods like Simulated Annealing
process, which can judiciously sample representative and (SA), genetic algorithm (GA), gradient descent, Ant Colony
hard-to-predict micro architecture choices and use them for Optimization (ACO) etc. and machine learning models. In
training the learning model; in [79], the authors use ML [33], the authors use decision trees to speed up the simulated
to eliminate those points from the design space, which are annealing algorithm. Here [33], the authors use a decision
almost certainly non-optimal. To do so, in [79] the authors tree to reduce the design space to speed up the DSE time
propose a framework called Adaptive Threshold Non-Pareto and achieve comparable results to a non-pruned standard
Elimination (ATNE). Instead of improving the learner’s con- simulated annealing-based DSE. In the initial phases, stan-
ventional accuracy, this work focuses on understanding and dard simulated annealing generates designs based on the
estimating the risk of losing “good” designs due to learning previous design’s cost function. The initial designs are used
inaccuracy. Both these works use regression models to pre- to generate a decision tree to decide which of the attributes
dict the area and latency requirement of the HLS designs contributes to maximizing the cost function. The attributes
and result in very fast exploration time. One drawback of from the decision tree, which shows high correlations, are
[36] is they tested their model only on 242 designs, which fixed, while the less important attributes are selected pseudo-
is a very small subset of the actual design space of their randomly. This considerably reduces the design space and
tested design. Sohrabizadeh et. al [81] proposed a bottleneck- allows finding the Pareto-front faster than a regular simulated
guided gradient optimizer to find a better design point later annealer. In [34], the authors use ML to select the hyperpa-
used in DSE systematically. They use a heuristic for ordering rameters of the metaheuristic algorithms used in the DSE.
the parameters, which can eliminate the redundant design Some of the meta-heuristic parameter examples selected in
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Goswami et al.: Application of Machine Learning in FPGA EDA tool development

TABLE 3. Machine learning based Design Space Exploration Works

Paper ML Model QoR Metrics Average ADRS Dataset Max. Design Space
[36] TED+RF ADRS 3.38 Custom DFT design 119
[35] Transfer Learning ADRS 4.27 Spector OpenCL 1173
[53] Transfer Learning ADRS 0.28 Machsuite 21952
[82] Linear Regression ADRS 27.47 S2Cbench NA
[33] Decision Tree Run Time/Dominance 0.90a S2Cbench NA
[83] XGB Prediction Accuracy 1.95b CNN architectures 744
[80] XGB ADRS 0.161 S2Cbench/Chstone 120,000
[34] Decision Tree ADRS 3.03 S2Cbench NA
[79] RF Run Time 0.0155 Custom OpenCL BM 1527
[81] Analytical Run Time 5.04c Xilinx Vitis Library NA
[26] GNN Resource/Latency 2.54xd /6xc Machsuite/Poly/Chstone 4700(synth) /800(real)
[20] Analytical Run Time 215.12c Polybench 95
Note: a Average Dominance; b Average MAPE; c Average Speedup; d Average DSP Usage; NA: Not Available

this work are the initial and final temperature, the descent try to generate their dataset [35], [36], [79], [81], [83]. Even
rate, the exit condition in simulated annealing, and, in the if they use the existing benchmarks, they generate their own
GA case, the number of parent pairs and the mutation and design versions. Hence, a fair comparison of the works is
crossover rate. The authors also proposed a combined SA, difficult to perform. Generating datasets to train ML models
GA, and ACO concurrent multiheuristic design space ex- for PPA estimation or DSE is an extremely time-consuming
plorer. In [80] Goswami et al. combined heuristics-based process, which can take weeks and months. To address this
Simulated annealing and ML regression model to design a issue, [88], [89] and [90] benchmarks have been created,
fast design space explorer in real designs. The initial part specifically curated for ML training. These are large datasets
of the DSE algorithm runs on logic synthesis-based results, similar to computer vision datasets like Imagenet [91], or
and once a sufficient amount of data (design points) has been Cifar10 [92], which are off-the-shelf datasets that the ML-
generated, they create an ML model and switch to fast ML- based EDA researchers can directly use for training purposes.
based predictive DSE. They used this work to run DSE on Another new direction of research is to eliminate the synthe-
different CNN architectures [83]. In [26], the authors created sis tools from the loop by using methods like LLVM [93] or
a fast DSE by applying GNN on LLVM IR graphs, which MLIR [94] methods, which was used in [26] and [80].
predicts a design’s resource and latency requirements. .

D. SUMMARY AND FUTURE DIRECTIONS FOR ML VI. MACHINE LEARNING IN FPGA CAD TOOL
BASED DSE PARAMETER SELECTION
One of the figures merits of measuring the performance of As the technology node decreases, the CAD tools used to
a DSE tool is called “Average Distance to Reference Set” design the ICs are also becoming very complex. Many pa-
(ADRS). This parameter measures how close the predicted rameters are involved in EDA tools, which results in a huge
DSE points are to the exhaustive search-based DSE points. design space. The runtime complexity of the CAD tools is
If the value of ADRS is close to zero, it is a very good also very large, and designs take multiple weeks to synthesize
design space explorer. The larger this value is, the worse the at each design point. Modern CAD tools used for logical
performance of the explorer. An explorer aims to minimize synthesis and physical design have hundreds of parameters
the ADRS or runtime. This is done by either minimizing the in them, which are set to meet various timing and area re-
design space [35], [79] or by applying transfer learning from quirements of the designs. The design space of these tools is
a different set of designs [35], [53] or from another platform humongous, and manually selecting the tool parameters will
like ASIC [82]. Most of the papers [34]–[36], [53], [80], take ages and may not always generate the optimum design
[82] measure the performance of their DSE tool in terms of in terms of power, performance, and area. To recommend
ADRS. In Table 3, column 3, we show what QoR measures tool parameters and minimize design space in EDA tools,
are being used to measure the performance of the DSE tools researchers have used Bayesian optimization [29], [30], [95],
as discussed in the papers, while in column 4, we reported classification [28], [31], [54], Principal component analysis
the average ADRS values of the various designs used in each for design space pruning [95] and tensor decomposition and
paper. For papers where QoR is measured using some other regression [32]. Researchers minimized the tools’ runtime
parameters like runtime, resource or latency requirements, and generated area and timing-efficient designs using these
the average of those values is reported. In columns 5 and methods. This section discusses seven recent works in which
6, the benchmarks’ names and the design space’s maximum ML is applied to minimize search space in EDA tools and
size are shown, respectively. Although there are few standard generate optimized designs. In Fig. 4, we have shown the
benchmarks like Chstone [84], Machsuite [85], Polybench high-level diagram of how ML can recommend CAD tool
[86] and S2Cbench [87] are available, most of the researchers parameters for FPGA design. The input to the recommender
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Goswami et al.: Application of Machine Learning in FPGA EDA tool development

Recommended
RTL Code ML Based Parameters
Recommender
System Parameter 1

Tool Parameters
• WLDrivenBlockPlacement
• ExtraNetDelay_low
• Bayesian Parameter 2
• . Optimization
• . • Regression
• RuntimeOptimized
• Classification Parameter 3
• Active Learning
Desired Specs
Area Timing Power
--- --- ---
--- --- ---
--- --- ---

FIGURE 4. High Level diagram showing how ML is used to recommend CAD tool parameters

system is generally the RTL code, a set of logic synthesis Random Forest (rf), Support Vector Machine (SVM)
and physical design parameters that need to be tuned, and (svmRadial) and Neural Network (nnet). Here also,
the desired specs in terms of area and performance. The the authors minimized the clock period using the suggested
recommender system considers the specs and the RTL code, CAD parameters.
and using ML, it suggests the best set of tool parameters to Similar to [28] and [31], LAMBDA [55] also tries to
be used. All the works discussed in this section use a variant maximize TNS. In [28] and [31], parameters of single stage
of this flow. are tuned, i.e only for logic synthesis, placement or routing.
But in [55], parameters of multiple stages are tuned simul-
A. RECOMMENDER SYSTEM TO SUGGEST taneously. They combine the features from multiple stages
PARAMETERS TO MEET TIMING to predict post route QoR of the designs. They addressed
the problem as a regression problem and used gradient boost
The works discussed in [28], [31], [55] propose methods
regression to solve it.
to suggest CAD tool parameters to maximize total negative
slack (TNS). InTime [28] is a plugin for FPGA CAD tools
that can automatically select tool parameter assignments for B. GENERALIZED PPA RECOMMENDER SYSTEM
each design by using machine learning heuristics and cheap There are few other works [29], [30], [32], [54] which are
cloud computing resources. While modern CAD tools have much more generalized than those discussed in Section VI-A.
hundreds of parameters, InTime uses only 25 parameters These works suggest parameters not only to optimize timing
to suggest the best timing solutions. InTime is an iterative but also to optimize other metrics like power, timing, and
algorithm organized as a series of concurrent CAD runs. area. [29] proposed a method that is used to automate the
Each round, which consists of multiple concurrent runs, is flow selection in IC design using the Bayesian optimization
an opportunity to generate candidate CAD parameter com- method. Their optimization function optimizes a cost func-
binations and acquire data for analysis. Within each round, tion consisting of power, performance, and area values. They
InTime uses a supervised learning approach to train classi- automate the flow selection at logic synthesis and the place
fiers that evaluate the effectiveness of a given combination of and route stage. They have used Gaussian process regression
CAD parameter selections toward increasing timing slack. as the surrogate function for the Bayesian model. Using
[31] is an extension of Intime [28]. In this paper, the au- Bayesian optimization, the authors tuned six parameters, four
thors proposed a method to select the best CAD tool param- of which are during the logic synthesis stage and two during
eters using a classification problem. They have minimized the place and route stage. Similar to [29], [32] also suggests
the search space using the Principal Component Analysis tool parameters both at logic synthesis and place and route
method. To train the model, they used the shelf ML mod- stage, using a two-step process. In the first stage, an ML
els like Logistic regression (glm), Bagging (treebag), model is trained offline. They have used macros and small
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partitions of large-scale, high-performance server processor VII. MACHINE LEARNING TO PREDICT POWER,
chips for training. Once the model is trained, in the second PERFORMANCE AND AREA ESTIMATION IN FPGA
stage, the tool inputs the macro name whenever a new macro DESIGNS
comes. Suppose it is previously seen macro, set of cost func- Power, performance, and area estimation are crucial in any
tions to be optimized, or some baseline synthesized results VLSI physical design flow. The earlier we predict the post-
for new macro and recommends the set of tool parameters route QoR of design, the better it is so that the designer
to meet the objective function. Although the paper presents can go back and set the tool parameters to meet the specs.
a nice idea about the recommendation system, nothing has Few recent works use analytical or mathematical models
been mentioned about the ML model or feature sets. Also, or machine learning models to predict the post-route QoR
the paper does not discuss the accuracy of the resultants QoR of both HLS and RTL designs. Works like COMBA [20],
of the recommendation system. LinAnalyzer [19] and Aladdin [21] use analytical methods
[54] proposes a totally new approach compared to the to estimate the post route PPA of HLS designs, whole “Fast
already discussed ones. Instead of suggesting hyperparam- and Accurate” [22], Pyramid [25], XPPE [23], HLSPredict
eters for CAD tools, this work suggests which will be the [23] and Powergear [63] use ML-based methods to estimate
best tool to use to meet the specs of a particular design. the post route QoR of HLS designs. In [51] and [50] ML
They address the problem as a binary classification problem; has been used to predict timing in RTL-based FPGA design,
for placement purposes, they selected two popular academic while in [62] and [63], GNN is used to predict power in
placers, gplace3.0 [75] and UTPlacef [74]. This work does FPGA designs..
not discuss the quality of the generated placed circuits in
terms of timing, area, or power. A. ANAYTICAL METHODS FOR PPA ESTIMATION OF
HLS DESIGNS
Aladdin [21], Comba [20], and Lin Analyzer [19] are three
C. SUMMARY AND FUTURE DIRECTIONS recent works that estimate power, performance, or area for
In Table 4, we have summarized the work done in the HLS designs either individually or together using analyti-
ML-based CAD tool parameter optimization domain. Except cal and mathematical approaches without the need of any
[29], all the other works are classification or regression. In ML models. Aladdin [21] is a pre-RTL power performance
the classification ones discussed in [28], [31], the authors simulator designed to enable rapid design space exploration
predict whether the QoR (area/timing, etc.) will be met or of accelerator-centric systems. This framework takes high-
not met using a certain set of tool parameters. Similarly, level language descriptions of algorithms as inputs and uses
in [54], a binary classification method is used to suggest dynamic data dependence graphs (DDDG) to represent an
which of the two academic placers is suitable to place and accelerator without generating RTL. Starting with an uncon-
route a certain design; most of the work [28], [29], [31] strained program DDDG, which corresponds to an initial
work only at one stage of the physical design flow; i.e., representation of accelerator hardware, Aladdin applies op-
either at synthesis, placement or routing. They cannot opti- timizations and constraints to the graph to create a realistic
mize parameters parallelly in multiple stages. This issue is model of accelerator activity. Alladin generates different
addressed in LAMBDA [55], where they try to simultane- optimized DDDG graphs and applies various mathematical
ously autotune the hyperparameters in multiple stages, from calculations to estimate the cycle-wise power, timing, and
logic synthesis to routing. Bayesian optimization is a popular area requirement.
hyperparameter optimization method which is widely used in COMBA [20] is an analytical engine that is used to suggest
ML frameworks to select optimal parameters. More research pragmas during DSE. To generate the pragma recommen-
can be done in using Bayesian optimization methods for rec- dations, COMBA uses a database called recursive data col-
ommending automatic parameters in EDA flow at different lector (RDC) and a metric-guided design space exploration
stages. (MGDSE) algorithm. In input to the tool is a high-level HLS
code written in C/C++. COMBA converts the HLS code
into LLVM IR [73] codes and corresponding control and
TABLE 4. Summary of CAD tool autotuning works dataflow graphs (CDFG). By running analysis on the LLVM
IR code and the CDFGs, they create a mathematical model to
ML Method Stage Recommendation References estimate an FPGA design’s latency and resource requirement.
Bayesian LS, PR Tool Parameters [29], [30]
Classification LS, PR CAD flow [54] Based on the estimated resource and latency requirement, the
Classification LS, PR Tool Parameters [28], [31] MGDSE suggests pragmas for the next iteration. One major
Regression LS, PR Tool Parameters [32], [55] drawback of this work is that it compares their estimates
concur-
rent
against the estimation done by Xilinx Vivado HLS after the
Note: LS: Logic Synthesis; PR: Place and Route C-synthesis stage. Since the value reported by Vivado HLS
is highly inaccurate [22], [25], [96], hence the estimation of
COMBA is also wrong. However, their latency estimation is
very good as compared to post-HLS estimation by the Vivado
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Goswami et al.: Application of Machine Learning in FPGA EDA tool development

HLS tool. also created an intermediate stage called Code Transformer

(CT), which converts the high-level HLS code into CDFGs.
B. ML BASED METHODS In this work, they proposed a transformation methodology
In [22], [25], the authors predicted post-route resource and that maps the multiplication operation to LUT or DSPs in
timing requirements of HLS designs by using regression an optimized manner depending on the latency and resource
models based on post-synthesis log files. Generally, the QoR requirement. They tested on eight real and synthetic bench-
reported by an HLS tool after the C-synthesis stage varies sig- marks from CHstone and Machsuites benchmark suites and
nificantly compared to post-route results. In [22], the authors achieved less than 10% Mean Absolute Percentage Error
analyzed the log files generated after the C-synthesis stage (MAPE) for both resource and timing requirements. Even
to extract various features to minimize the error. Later, they though they discussed a DSE, nothing has been mentioned
created regression models, which include Artificial Neural about the ADRS values as compared to metaheuristics-based
Networks, Linear Regression, and XGBoost, to predict the approaches like SA and GA. The strategy for DSE is also not
post-route area and performance of the designs. The work de- properly discussed in the paper.
scribed in Pyramid [25] is very similar to [22]. Although the [62] and [63] are two recent works in which GNN has been
prediction results are good, a major drawback of this work is applied to predict power in RTL and HLS designs. In this
we have to run C-synthesis on the designs to extract features. work [63], the authors predicted early-stage power estimation
Also, they did not report the error/accuracy on individual in HLS design using GNN. They considered the impact of
benchmarks. The details of the used features are also missing interconnects in power modeling to model their predictor
in the work. In [96], the authors created regression models accurately. Here, they have created their graph from the HLS
to predict post-route resource, timing, and latency of HLS design. The HLS design is converted into graphs, where
designs based on features from the high-level C++ code and the nodes are represented as operations, and node features
LLVM IR codes, in, [97] the authors constructed a regression indicate micro-architectures. The edges are interconnected,
model using four different regression models. They extracted and edge features are represented as netlist activities. They
the features from the post-high-level synthesis log files and later created a customized GNN to predict dynamic and
the labels from a customized activity generator. They later total power in an HLS design. Traditionally, in RTL-based
used the model to create a design space explorer for latency designs, power is estimated using gate-level simulation of
vs power consumption and achieved very low ADRS values. the synthesized netlist, switching activity estimation (SAE),
However, the work does not mention the details at which and input-output register toggle rates. This method is very
stage the labels are generated. A random forest-based ML slow and can take months. In [62], the authors used gate-
is explored to predict net delay in FPGA placement was level netlists and corresponding input port and register toggle
proposed in [51]. Most of the features are extracted from the rates over a power window from simulation as input as the
post-synthesized netlist, which includes fanout, Half Perime- training graph and the toggle rates from gate-level simulation
ter Wirelenth (HPWL), congestion, critical path length etc. as labels. They used the model to predict SAE, which can
They later applied the Recursive Feature Elimination (RFE) later be converted to power.
method to reduce the number of features to 20 and used it to
predict delay in RTL-based designs. D. CROSS PLATFORM BASED METHODS
In [23] and [24] use a methodology in which training is done
C. GRAPH LEANING BASED METHODS on one set of architecture/platforms but prediction is done on
[27] and [26] use graph learning methods to predict the post- FPGAs only. Unlike RTL code, HLS code written in high-
route timing of HLS designs. In this work [27], the authors level languages like C/C++ can run on any architectures like
proposed a graph-based learning method to measure the CPU, GPU and microcontrollers. The authors leveraged this
delay of post-mapped arithmetic operations in HLS designs. in [23] and [24]. In [23], the authors run multiple designs
They used Graph Neural Networks (GNN) to do so. Since on different Xilinx FPGA devices and predict the perfor-
GNNs can be used to predict the property of nodes and edges, mance or speedup on Arm A9 devices. To create the model,
they leveraged this property to predict the delay of mapped they have extracted features from the post-C-synthesis log
arithmetic operations. They convert the HLS code into LLVM files, which are very similar to "Fast and Accurate" [22]
IR and corresponding Control and Dataflow Graphs (CDFG) and Pyramid [25]. This model helps designers to create a
to generate the graphs. They created a bunch of microcircuits heterogeneous system to divide which portion of a design to
from the CHstone [84] benchmark suite to test their model run on the FPGA part and which part to run on Arm part. The
and achieved 72% reduction in root-mean-square error com- major drawback of this work is the authors did not consider
pared to operation delay estimation in Vivado HLS. the effects of pragmas on their HLS designs.
Ironman [26] is a unified HLS PPA predictor and DSE In [24], the power and performance of an HLS design
tool that uses ML in both stages. In the first stage, they running on FPGA is predicted by creating a ML model
use a graph neural network to estimate the LUT require- based on features generated after running the design on
ment and timing of the HLS designs. In the second stage, CPUs. HLSPredict ensures time synchronicity between the
Reinforcement Learning is used to create the DSE. They host CPU and the target FPGA accelerator by using sub-
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Goswami et al.: Application of Machine Learning in FPGA EDA tool development

TABLE 5. Summary of Machine Learning based Power, Performance and Area prediction tools

Machine Feature Average

Paper Design Entry Predicted Parameters Dataset
Learning Model Source Error (%)
LUT 4.05
FF 3.8
Chstone/Machsuite
[22] XGB C-synthesis files HLS BRAM 0.2
/S2Cbench
DSP 2.5
Performance 6.4
LUT 11
Ensemble Transfer LLVM, Synthesis FF 12
[52] HLS Multiple ML kernels
Learning and PR Files BRAM 2
DSP ∼0
[20] Analytical LLVM IR HLS Latency 0.5 Polybench
[19] Analytical DDDG HLS Latency 2.52 Polybench
[23] ANN C-synthesis files HLS Performance 5 Custom designs
LUT 13.33
FF 18.33
CHStone/ Machsuite/
[25] RF C-synthesis files HLS BRAM 13.33
S2CBench/Rosetta
DSP 16.66
Performance 15.66
C-synthesis &
[97] CNN HLS Power 4.67 Polybench
Switching Activities
Latency 9.8
[24] RF CPU subtraces HLS Polybench
Power 7.8
LUT 8.3
LLVM IR Chstone/Machsuite
[26] GNN HLS DSP 3.8
CDFG /Polybench
Performance 4.4
LLVM IR
[27] GNN HLS Interconnect Delay 0.93 Machsuite
CDFG
LUT 10.32
Chstone/
[96] XGB LLVM IR HLS Performance 6.29
S2Cbench
Latency 10.22
[63] GNN LLVM IR HLS Power 6.20 Polybench
[62] GNN Gate Level NL RTL Power 4.35 Custom designs
[51] RF Gate Level NL RTL Timing 6% ISPD2016
Performance 0.9
[21] Analytical DDDG RTL Power 4.9 GEMM design space
Area 6.6

traces for model training: sub-traces are epochs of workload the work in [96], [98] is a comprehensive one that can
execution time in the form of CPU countermeasures for the predict all the four post route QoR metrics of a design viz.,
host, and FPGA cycle counts for the target. The authors Latency, Resource Requirement, Timing, and Power. There
perform a detailed analysis of a design running on x86 CPU is no work in which more advanced ML models like BERT,
by identifying the CPU microarchitectural subsystems and Transformer, or Autoencoders are being used to enhance and
correlating them with the post-route performance and power predict the performance of EDA tools. Using these modern
when the same design runs on FPGA. techniques, post-route PPA estimations can be made faster
and more accurate simultaneously. In a very recent work [99]
E. SUMMARY AND FUTURE DIRECTIONS
(August 2023), the Large Language Model (LLM) has been
used to generate Verilog code based on design description
In Table 5, we have summarized the works done to predict in pure English language. These codes can be synthesized
FPGA designs’ PPA using analytical methods and ML-based on both FPGA and ASIC design tools. In another work, the
models. Most of the work discussed in Table 5 predicts authors present their work, which, for the first time, shows
the post-route behavior of HLS designs. Models like XPPE, how to generate hardware security properties using LLMs au-
“Fast and Accurate” and Pyramid [22], [23], [25] rely on tomatically. They created their own BERT model, Hardware
post-C-synthesis log files to extract features; hence they are security-BERT, which can read SoC design documentation
slower as compared to LLVM-based models like [20], [26], and generate pertinent hardware security-relevant properties
[27], [96]. Most of the works discussed here use their design [100]. Even though these two works are not directly applied
entry as HLS because of the fast synthesis, implementation to predict PPA in FPGA CAD tools, these two are promising
time, and large availability of benchmarks. In the RTL-based works to show how technology is advancing towards LLM
works shown in Table 5 [21], [51], [62] they use features and other language models.
from synthesized gate-level netlists to predict a design’s
power and timing requirements. While most of the works
discussed here predict either resource or timing or latency,
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Goswami et al.: Application of Machine Learning in FPGA EDA tool development

EDA Environment A. MACHINE LEARNING IN FPGA SYNTHESIS

(SA moves/random
moves/ Synthesis Scripts) ML has not been widely applied in the Synthesis or mapping
stage of FPGA physical synthesis since these stages are too
Stage St+1
Action At early to predict QoR down the flow. In [50] , the authors
Reward proposed a methodology to predict the timing characteristics
of a circuit right after the technology mapping stage. Similar
Self learning
to [51] discussed in Section VII, in [50], the authors extracted
Reinforcement
Learning Environment features from the post-synthesized netlist. They used a gradi-
ent boost algorithm to train their regression model. However,
FIGURE 5. A generalized diagram of application of Reinforcement Learning in they created the labels from the post-mapped netlist, not
Physical design
from the post-placed or post-route stage. However, this work
is after the synthesis stage, right before mapping. There
are few works in which RL is applied in Synthesis. In
[121], Zhou and Anderson combined RL with ABC synthesis
VIII. MACHINE LEARNING IN FPGA LOGICAL AND [122] to design a RL-guided synthesis optimization. They
PHYSICAL DESIGN FLOW used eight different optimization parameters provided by
For decades, both FPGA and ASIC physical design has been resyn2 script to define their action state space, and the
dominated by evolutionary algorithms like genetic algorithm, reward function is calculated as the difference between the
simulated annealing, and gradient descent algorithms [101]– number of LUTs in the current state and the initial state (first
[107]. More recently, these heuristic-based algorithms are stage). Among other RL-based synthesis works, Zhu et al.
replaced by analytical solvers for improved timing [74], [75], [123] propose the use of a graph convolutional network on a
[108]–[110]. Similarly, most routing algorithms use either circuit AIG (And-inverter-graph) to leverage graph structural
heuristic-based or analytical methods [103], [104], [111]– information for an RL agent to select which optimization
[114]. But similar to any other EDA algorithms discussed commands to use. The action space of [123] is very similar
previously, the analytical and heuristic-based methods are to [121] based on ABC resyn2. Drills [124] is an RL-based
very slow for large designs, taking days to run one design. design space explorer in the synthesis space where they used
A few works [115]–[118] improve the runtime by invoking advantage actor-critic (A2C) to guide their RL agent. The
simulated annealing in multiple CPUs and GPUs. However, reward function used in this work is to find a minimum design
this work needs a very large runtime to converge a solution. area subject to delay constraints.
To improve the runtime of simulated annealing or analytical
methods, the researchers accelerate the SA or analytical B. MACHINE LEARNING IN FPGA PLACEMENT
placement using reinforcement learning (RL). Kamakoti and Reinforcement learning has been widely used either stan-
Bhatia’s work [119] was one of the first works in which RL dalone [60] or in combination with metaheuristic algorithms
is combined with a Support Vector Machine (SVM) to speed like simulated annealing [56]–[59]. Most of these works use
up the FPGA place and route process. Recently, researchers VTR [125] as their base placement algorithm and use RL
combined heuristics and reinforcement learning (RL) in to guide the annealer. In [56], Elgammal et al. combines
FPGA placement stage [56]–[59]. In [120], the authors used simulated annealing (SA) with reinforcement learning. In
a convolution neural network to improve placement, while SA, all the moves may not always result in improved timing
RL has been applied to synthesis and routing in [121] and or wirelength. The authors want their algorithm to “learn”
[61] respectively. In this section, we will discuss how ML is the most effective perturbations using reinforcement learn-
applied to the three crucial stages of FPGA physical design ing RL. The RLPlace algorithm uses seven directed moves
flow viz., (i) Synthesis, (ii) Placement, and (iii) Routing. In to optimize both wirelength and critical path delay. Here,
Fig. 5, we have shown a high-level common flow of how RL RL guides the annealer to select the most effective moves
is applied in different FPGA/ASIC physical design stages. throughout the placement to explore large placement solution
In RL-based IC design, a vector of performance features space and achieve high-quality results quickly. This work
represents the state of a circuit. The RL agent takes this [57] is very similar to [56] with several moves less than
vector as the input, executes an action by changing the design [56]. The proposed algorithm (directed moves + RL) explores
parameter values, computes the reward, and then moves to the solution space more efficiently than traditional random
the new state (S(t+1) ) (Fig. 5), if the reward has increased, moves, yielding better QoR for all tested designs. [58] is a
else it explores different available actions otherwise. The precursor to [56] and [57] by Betz and his team. In [58],
reward is computed from the EDA environment results like the authors combine SA and RL to guide the placement
simulated annealing or genetic algorithm (shown in the top algorithm. But unlike [56] and [57], only one state is used to
box of Fig. 5) [44]. Most works discussed in this section use guide the agent instead of using two state spaces at different
a variant of the flow shown in Fig. 5. temperatures of SA annealing. Also, in [56] and [57], seven
directed moves were used for the annealer. In [58], only
one move is selected: the Random Move in [56]. Here, they
VOLUME 4, 2016 13

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Goswami et al.: Application of Machine Learning in FPGA EDA tool development

guide the RL agent based on four resource types in place TABLE 6. Summary of ML based Physical Design Tools
of moves. [59] is quite similar to [56], [60] and [57]. Here
Stage ML Algorithm Papers
also, the authors applied RL to optimize moves of SA-based RL [121], [123], [124]
placer in VTR [101], [125]. But the details of the moves are Logic Synthesis RL+GCN [123]
not discussed in the work, nor are the results shown very Regression [50]
RL [56]–[59]
prominently here. Placement
CNN [120]
In this paper [60], Malappa et al. applied RL in the detailed Routing RL+GCN [61]
placement stage. They addressed the detailed placement
problem as two staged hierarchical problems: (i) Coarse-
grained refinement and (ii) Fine-grained refinement. They for routing on the placed circuit in the future. In Table 6, we
applied RL in Stage 1 to select the optimal sliding window classified the three stages of physical design and what are the
size and the order in which the sliding windows must be ML algorithms applied in each stage.
rearranged. In Stage 2, Satisfiability Modulo Theories (SMT)
are applied for fine-grain refinement. This work is purely RL- IX. CONCLUSION
based, and they did not combine with any meta-heuristics- ML is a growing field in the current technology domain, with
based methods like SA or Genetic Algorithm. In [120], the many applications in computer vision, image processing,
authors addressed the placement problem as a CNN problem audio and video processing, NLP, etc. This field is currently
based on electrostatic density. The authors proposed a CNN- being applied in the EDA domain. CAD-based IC design
inspired analytical global placement algorithm for large- technology has been there since the 1980s, and we have lots
scale FPGAs. A novel density framework was constructed and lots of data available at various stages of the physical
to remedy the high computation time by casting the 2D design flow for various technology nodes. If we can utilize
electrostatic-based density constraints into CNN. This first the data from past IC designs for ASIC and FPGA, we
and one of the only known works where CNN has been can make great tools using ML, resulting in fast IC design
directly applied to the placement problem. tools. Another challenge of ML-based IC design tools is
the availability of specialists. The designer must have ex-
C. MACHINE LEARNING IN FPGA ROUTING ceptionally good knowledge of VLSI design flow and ML
Although ML has been widely applied to predict congestion, technologies. As discussed in this chapter, almost all the
routing violations, or DRC violations in routing, as discussed available ML algorithms are now being applied in EDA tool
in Section IV, very few works are where ML is directly design. However, most of the work discussed in this paper
applied to guide the routing algorithm. RL has been applied is still nascent in academic labs, and commercially making
to optimize the routing algorithm in one such work. In [61], them available with vendor-supplied tools may take some
the authors applied RL to optimize the routing algorithm and time. Two recent tools from AMD Xilinx Vitis AI [126] and
compared it against the conventional negotiated congestion Synopsys DSO [127] use ML as part of their implementation
routing method used in Pathfinder [111] routing algorithm. algorithms.
They used the cost function similar to [111] and optimized it
using RL. However, the paper does not discuss the details of
the RL algorithm and how the state table is created. This is Acronyms
the only work where the authors tried to apply ML in routing ADRS : Average Distance to Reference Set
instead of merely prediction congestion or routing violation ANN : Artificial Neural Network
[37], [38], [41], [71]. CAD : Computer Added Design
CDFG : Control and Dataflow Graph
D. SUMMARY AND FUTURE DIRECTION CNN : convolution Neural Network
In Table 6, we have summarized the application of ML in DRC : Design Rules Check
different stages of FPGA physical design flow. Reinforce- DSE : Design Space Exploration
ment Learning is very similar to human learning. Just like EDA : Electronics Design Automation
humans learn from their mistakes and retrain themselves, GA : Genetic Algorithm
RL also does so. Hence, RL is very suitable for physical GAN : Generative Adversarial Network
synthesis optimization in EDA. Based on different reward GCN : Graph convolution Network
functions, which are generally the cost functions of heuristic HLS : High Level Synthesis
algorithms, the RL agent guides the optimizer. Hence, it HPWL : Half Perimeter Wirelength
is widely used in placement [56], [57], [59], [60] although IC : Integrated Circuit
application in routing and synthesis is limited. Future works IR : Intermediate Representation
in this direction may include generative AI like GAN, which MAPE : Mean Absolute Percentage Error
will generate the placed circuit based on description like the MARS : Multivariate Adaptive Regression Splines
requirement for timing and area. Just like GAN is used to ML : Machine Learning
create virtual congestion in [40], [41], GAN can also be used MLP : Multi Layer Perceptron
14 VOLUME 4, 2016

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 This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and
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Goswami et al.: Application of Machine Learning in FPGA EDA tool development

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PINGAKSHYA GOSWAMI (Student Member,

IEEE) received the B.Tech degree in Electron-
ics and Communication Engineering from Tezpur
University, India in 2012 and M.S. and PhD de-
grees in Electrical Engineering from the Uni-
versity of Texas, Dallas, in 2016 and 2022 re-
spectively. He is currently working as a software
engineer in Lattice Semiconductor. His research
interest include EDA tool development for FPGAs
and ASICs and hardware accelerator design on
FPGAs.

DINESH BHATIA (SM’00) received the Bach-

elor’s degree in electrical engineering from the
Regional Engineering College, Suratkal, India, in
1985, and the Master’s and Ph.D. degrees in com-
puter science from the University of Texas at Dal-
las, TX, USA, in 1987 and 1990, respectively. He
is a faculty member at the Erik Jonsson School of
Engineering and Computer Science, University of
Texas at Dallas, where he directs research activi-
ties within the IDEA Lab. He has served on techni-
cal program committees of several international conferences related to field-
programmable gate arrays (FPGAs), field-programmable technology, and
system-level design using FPGAs. His research interests include the system-
level design, power and energy systems, and architecture and computer-
aided design for FPGAs. Dr. Bhatia has served on the Editorial Board of
the IEEE TRANSACTIONS ON COMPUTERS. He was a Distinguished
Lecturer of the IEEE Circuits and Systems Society for 2007–2008.

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