VLSI DESIGN FLOW: RTL TO

GDS

Lecture 5
Overview of VLSI Design Flow: III
Sneh Saurabh
Electronics and Communications
Engineering
IIIT Delhi
Lecture Plan
Overview of VLSI Design Flow

▪ RTL to GDS Implementation

➢ Logic Synthesis

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 2

Overview of RTL to GDS Flow

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 3

VLSI Design Flow: RTL to GDS Flow

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 4

Overview of RTL to GDS Flow

Logic Synthesis

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 5

RTL to GDS flow: Logic Synthesis
▪ Logic Synthesis: process by which RTL is converted to an equivalent circuit as
interconnection of logic gates

▪ RTL: given design (Verilog, VHDL)

▪ Library: standard cells and macros

(Liberty)

▪ Constraints: design goals, expected

timing behavior, environment (SDC)

▪ Netlist:
➢ Interconnection of logic gates
➢ Usually represented using
Verilog constructs or schematic

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 6

Logic Synthesis: Illustration
module top(a, b, clk, select, out);

input a, b, clk, select;

output out;
reg out;
wire y;

assign y = (select) ? b : a;

always @(posedge clk) module top(a, b, clk, select, out);

begin input a, b, clk, select;
out <= y; output out;
end wire y;

endmodule MUX2 INST1(.A(a), .B(b), .S(select), .Y(y));

DFF INST2(.D(y), .CP(clk), .Q(out));

endmodule

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 7

Logic Synthesis: Inputs and Outputs

Netlist
module …..
……. module top(a, b, clk, select, out);
endmodule
Logic input a, b, clk, select;
RTL Synthesis output out;
wire y;
library
cell(MUX2) MUX2 INST1(.A(a), .B(b), .S(select),
… Library .Y(y));
cell(DFF)
DFF INST2(.D(y), .CP(clk), .Q(out));

create_clock –name clock – endmodule

period 10 [get_ports clk]
set_input_delay ….
Constraints

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 8

 Netlist Terminologies

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 9

Netlist Terminologies: Design and Ports

Design: Top level entity that represents the circuit. Example: MYDESIGN

Ports: The interfaces of the Design through which it communicates with the external world.
Example: in1, in2, CLK, out1, out2
▪ Input Ports: Signals going inside the design. Example: in1, in2, CLK
▪ Output Ports: Signals going outside from the design. Example: out1, out2

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 10

Netlist Terminologies: Cells

▪ Cells: basic entity delivering combinational or sequential function contained in libraries.

Examples: AN2, NOT, BUF, DFF
▪ Design is composed of multiple cells connected together

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 11

Netlist Terminologies: Instances

▪ Instances: cells when used inside a design are called instances.

Examples: I1, I2, I3, out1_reg, out2_reg.
▪ Using a cell in a design is called instantiation.
▪ The same cell can be instantiated multiple times.
Example: out1_reg and out2_reg are instances of the same cell DFF.

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 12

Netlist Terminologies: Pins

▪ Pin: An interface of a library cell or instance through which it communicates with the other
components is called a pin.
▪ Examples: A, B, Y are the pins of the cell AN2 and the instance I1
▪ Library Pin and Instance Pin (if we want to be explicit)
➢ Often apparent from the context
▪ Input Pin or Output Pin based on direction of flow of signal to cell/instance
VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 13
Netlist Terminologies: Pin Names

▪ Instance pin name: typically specified as combination of instance name and pin name
separated by /
▪ Examples: I1/A, I1/B , out1_reg/Q

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 14

Netlist Terminologies: Nets

▪ Net: The wire that connects different instances and ports is a called net.
Examples.: N1, N2, N3, …N8

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 15

Logic Synthesis Tasks

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Logic Synthesis Tasks: RTL Synthesis
RTL synthesis:
▪ Initial part of logic synthesis consisting of translating
an RTL to a netlist of generic logic gates

Generic Logic Gates

▪ A generic logic gate has a well-defined Boolean
function.
➢ AND, NAND, XOR, multiplexer, demultiplexer etc.
➢ Latches and flip-flops.
▪ Does not have a fixed transistor-level
implementation
➢ Does not have a well-defined area, delay, and
power attributes

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 17

Logic Synthesis Tasks: Logic Optimization

Logic Optimization:

▪ Optimizations on a generic gate netlist

▪ Typically area-driven

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 18

Logic Synthesis Tasks: Technology Mapping and
Optimization
Technology Mapping:
▪ Map a netlist consisting of generic logic gates to the
standard cells in the given technology library
▪ Obtain a netlist consisting of standard cells

Technology-dependent optimization:
▪ PPA can be estimated more accurately after
technology mapping
▪ Perform timing, area, and power optimizations over
netlist consisting of standard cells

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 19

 References
▪ G. D. Micheli. “Synthesis and Optimization of Digital Circuits”. McGraw-Hill Higher Education,
1994.

▪ S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge: Cambridge University Press,

2023.

soprotection.com VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 20

VLSI DESIGN FLOW: RTL TO
GDS

Lecture 6
Overview of VLSI Design Flow: IV
Sneh Saurabh
Electronics and Communications
Engineering
IIIT Delhi
Lecture Plan

▪ RTL to GDS Implementation

➢ Physical Design

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 2

Overview of RTL to GDS Flow

Physical Design

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 3

VLSI Design Flow: Physical Design
Physical Design: Process by which a design in the form of a netlist is converted to an
equivalent design in the form of layout or GDS (geometrical patterns of masks)

Netlist: input design (output of logic synthesis)

Library:
▪ Similar as in logic synthesis (Liberty)
▪ Abstract physical information of cells and
technology-specific information (LEF)

Constraints: design goals, expected timing

behavior, environment (similar as in logic synthesis)
(SDC)

Floorplan: designer’s intent about the physical

design (size and shape of die, predefined
placement information)

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 4

Physical Design: Major Tasks

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 5

Physical Design: Chip Planning

Chip Planning

▪ First step in physical design in

which we take major decisions

▪ Partitioning into subsystems or

blocks

▪ Arrange the blocks on the

chip/die

▪ Allocation of area for the

standard cells, macros,
memory

▪ Includes IO cell planning and

Power Planning

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 6

Physical Design: Placement

Placement

▪ Decides location of standard cells in the design

Objectives:

▪ Total wire length minimization: based on estimates

▪ Ensure timing is met: reduce the delay of the critical path

▪ Ensure no congestion
VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 7
Physical Design: Clock Tree Synthesis
Clock Tree Synthesis (CTS)

▪ Decides topology of clock network and

how clock reaches each clocked
element

▪ CTS also performs wiring of clock

network (avoids detour since majority of
routing resources still unused)

Objectives:

▪ Ensure minimum skew: symmetric

structure

▪ Minimize power dissipation: clock

network consumes large fraction of total
power

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 8

Physical Design: Routing

Routing

▪ Creates wire layout for all the nets (other than clock
and power supply) satisfying certain constraints

▪ Objective: Use minimum wire-length, routing area, vias

▪ Very complicated process (too many nets and routing

constraints)

▪ It is typically done in two steps:

➢ Global Routing
➢ Detailed Routing

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 9

Physical Design: Global Routing
Global Routing

▪ Planning stage for routing

▪ Actual layout of wires not

created

▪ A routing plan for a given net is

created

▪ Entire routing region is partitioned

into rectangular tiles or global
bins

▪ Global routing assigns a set of

global bins that will be used for
making connections for a given
net

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 10

Physical Design: Detailed Routing
Detailed Routing

▪ Decides actual layout of each net

in the pre-assigned global bins

▪ The detailed router decides the

actual physical interconnections
of nets by:
▪ Allocating wires on each
metal layer
▪ Vias for switching between
metal layers

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 11

Physical Design: ECO and GDS Writing
Engineering Change Order (ECO)

▪ Make small final fixes in the

design

Write GDS

▪ Dump the layouts of each layer in

a GDS file

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 12

Physical Design: Optimizations
▪ Between each physical design task there are optimization steps:
➢ Small changes in the design to improve PPA
➢ Example of changes in the design:
✓ Buffer insertion on a given net
✓ Changes in the size of a given cell
✓ Changes in the placement of a given cell
✓ Changes in routing for a given net

▪ Incremental refinements to the design

▪ Changes are kept to be small and restricted to a small portions

of a design
➢ Do not create large disruptions in the design
➢ Design flow should converge

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 13

Physical Design: Iterative flow
▪ Physical design implementation tasks performed along with
verification tasks (timing, power, signal integrity, etc.)

▪ Physical design implementation should ensure design closure

(including timing closure) [all constraints are satisfied]

▪ Achieving design closure is challenging

➢ Design tasks do not have the full information and works
with estimates that can be wrong

▪ Physical design flow is typically iterative

▪ One task may require that previous tasks retract some design
decisions
➢ This creates loops in the physical design flow

▪ Achieving design closure with minimum number of iterations is

the goal of a physical design flow

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 14

 References
▪ S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge: Cambridge University Press,
2023.
▪ M. J. S. Smith. “Application-Specific Integrated Circuits,” vol. 7. Addison-Wesley Reading,
MA, 1997.

soprotection.com VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 15

VLSI DESIGN FLOW: RTL TO
GDS

Lecture 7
Overview of VLSI Design Flow: V
Sneh Saurabh
Electronics and Communications
Engineering
IIIT Delhi
Lecture Plan
Overview of VLSI Design Flow
▪ Verification
▪ Testing

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 2

Overview of VLSI Design Flow

Verification

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 3

VLSI Design Flow: Verification
Verification:

We perform verification to ensure that the design

works as per given functionality

▪ Verification is done multiple times throughout a

VLSI design flow
➢ Whenever design undergoes some changes,
verification must be done
➢ If verification fails remedial action can be
taken immediately

▪ Significant effort of VLSI design flow is spent on

verification

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 4

Functional Verification: Simulation
Is design (RTL) producing the same results as given in the specification?
Simulation: technique for ensuring the functional correctness of the RTL using test vectors
▪ Test vectors: sequence of zeroes/ones and the associated timing information

▪ Obtain the response for the

given RTL using a simulator

▪ Expected output is computed

using another model (C, C++,
MATLAB, etc.)

▪ Compare output response

and expected response

▪ Merits of simulation:-based verification: fast and versatile

▪ Demerit of simulation-base verification: incompleteness

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 5

Functional Verification: Model Checking
Is design (RTL) producing the same results as given in the specification?
Model checking: technique for ensuring the functional correctness of the RTL using formal
methods
▪ Formal methods: establish the proof Property Checking/Model Checking
of a given property using formal
mathematical tools such as ▪ Define properties that must be satisfied for a
deductions given specification

▪ Once we have proven a property ▪ Check whether properties are being satisfied in
mathematically, it is guaranteed to the implemented design RTL using formal
hold for all test stimuli. methods
Verification using formal methods: Example:

▪ Merits: completeness ▪ A traffic controller should generate signals such

that “Not more than one light should be green”
▪ Demerits: computationally difficult
▪ In a resource sharing environment: “Request for a
resource should be granted eventually”
VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 6
Combinational Equivalence Checking
Will the RTL and the netlist generated by a logic
synthesis tool always produce the same (equivalent)
output?

Combinational equivalence checking (CEC):

establishes the functional equivalence of two models
using formal methods

▪ CEC required whenever non-trivial design changes

occur

▪ Carried out multiple times in a design flow

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 7

Static Timing Analysis
How to ensure the synchronicity of data
transfer between flip-flops in a synchronous
design?

Synchronicity: data launched by a flip-flop

gets captured in the sequentially adjacent
flip-flop in the next clock cycle

Static Timing Analysis (STA): ensures

deterministic synchronous timing behavior in
a circuit

▪ STA tools consider the worst-case

behavior (may be pessimistic), but will
always ensure the timing safety

▪ Carried out multiple times in a design flow

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 8

Physical Design Verification
How to ensure that the layout does not have manufacturing and connectivity issues and the
yield for a design remains high?
Physical verification:

▪ Check a set of rules during physical design before sending the layout to the foundry.
Design rule check (DRC):

▪ Rules are defined by the foundries and depend on the manufacturing technology

▪ All DRC violations must be fixed before sending it to the foundry for fabrication.
Electrical rule check (ERC):

▪ Rules are defined to ensure proper connectivity (for e.g.: no short circuit between distinct
signal lines).
Layout vs. schematic (LVS) check:

▪ Ensure that the layout is functionally equivalent to the original netlist

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 9
Rule Checking
Rules are some restrictions imposed on the design entity such as RTL, constraints, netlist,
layout etc. such that there are no issues in using that design entity downward in the VLSI
design flow

RTL: Ensure that RTL constructs used in

the design have no synthesis/simulation
issue down the flow

Constraints: Ensure that no conflicting

constraints are applied or any
constraint is missing
Netlist: Ensure that connectivity of
instances do not cause any issue down
the flow

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 10

Overview of VLSI Design Flow

Testing

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 11

VLSI Design Flow: Testing
▪ Verification : Ensures that GDS represents
the circuit correctly such that original
specification is met.

▪ Testing : Ensures that fabricated chip does

not have any manufacturing defect

Why testing is important during designing?

▪ RTL to GDS flow ensures that the chip that is

manufactured can be easily tested
(Testability)

▪ RTL to GDS flow ensures that if some defect

is found then the problem can be easily
diagnosed (debugged) and fixed

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 12

Manufacturing Defects: Origin
Defects
▪ Physical imperfections in a fabricated chip that are of permanent nature

Origin of defects
▪ Statistical deviations in material properties
▪ Finite tolerances in process parameters
▪ Airborne particles, and undesired chemicals
▪ Deviations in mask features

Large area and Spot defects

▪ Large area defects: simpler to eliminate
▪ Small area defects, of random nature
➢ Inevitably appears in chip fabrication
➢ Increases with increase in die area
Source:
https://commons.wikimedia.org/wiki/File:Clean_room.jpg ➢ Primary concern for testing
Uploaded by Duk 08:45, 16 Feb 2005 (UTC), Public domain, via
Wikimedia Commons

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 13

Manufacturing Defects: Manifestation
Manifestation of defects Faults:
▪ Short-circuit and open-circuit (functional failure)
▪ Testing focuses on
▪ Change in circuit parameters (such as delay) finding defects that
can be problematic for
a circuit behavior

▪ We model defect
(physical phenomenon)
using faults (circuit
model)

Distortions Inconsequential flaws

▪ Photolithography can produce distorted ▪ Deviations of a fabricated circuit from
features on a die the ideal, but not causing any
measurable change
▪ These are inevitable due to optical effects, etc.
▪ E.g.: if the size of particle is too small
▪ Needs to be handled using suitable techniques
▪ Testing does not detect these
▪ Testing does not detect these distortions inconsequential flaws
VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 14
Quality of Process: Yield

Yield Factors affecting yield

▪ Fraction of die on a wafer that are good 1. Die area: when area increases, yield
or without any fatal manufacturing defect falls
▪ Usually expressed in percentage
▪ E.g.: If 300 dies are good out of 400 dies 2. Defect density: average number of
manufactured, then yield is: defects per unit of chip area
300 (depends on process)
= 400 × 100% = 75%
3. Clustering: distribution of defects on
the chip area

Yield and process technology

▪ Function of complexity and maturity of the

process

▪ Desirable > 50%, and often > 90%

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 15

Yield: Dependency on clustering
Which is better for yield, when defects are clustered (defects lying in small region) or
unclustered (same number of defects distributed over a larger region)?

Let us compute the yield in two

cases shown.

Unclustered defects
24
Yield=34 × 100 = 71%

Clustered defects
26
Yield=34 × 100 = 76%

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 16

Yield Model
Yield model:
▪ Required to estimate yield (and hence
profitability of IC manufacturing)
▪ Various models have been proposed with
varying accuracy and complexity

▪ We can assume that the probability of having

a defect in a given area increases linearly
with the number of defects already present in
that area
▪ One of the models
Yield 𝒀 = (𝟏 + 𝑨𝒅/𝜶)−𝜶 × 𝟏𝟎𝟎%
where
➢ 𝐴 is die area, Clustering parameter
➢ 𝑑 is defect density, • 0<𝛼<∞
➢ 𝛼 is the clustering parameter • 𝛼 → ∞ ⇒ 𝑤𝑒𝑎𝑘 𝑐𝑙𝑢𝑠𝑡𝑒𝑟𝑖𝑛𝑔

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 17

Testing Technique
Automatic Test Equipment (ATE)
▪ Consists of test head, probe cards with probe
needles
➢ Probe needles make contact with the test pads
on the design under test (DUT)
▪ Test program controls all operation

▪ Test Patterns are applied to the manufactured chip

▪ Actual responses are compared with the expected
response
▪ If comparison FAILs ⇒ The chip has some defect(s)

▪ The failed chip can be diagnosed to find the root

cause of the problem
▪ After diagnosis corrective measures can be taken to
reduce the defects
VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 18
Fault Coverage and Defect Level
We measure the quality of testing using a ▪ Perceived quality of a chip strongly
parameter called fault coverage depends on: fault coverage and
yield
▪ Fault coverage: measures the ability of the set of ▪ Quality of chip is measured by a
test patterns to detect a class of faults quantity called defect level
# 𝑓𝑎𝑢𝑙𝑡𝑠 𝑑𝑒𝑡𝑒𝑐𝑡𝑎𝑏𝑙𝑒
▪ 𝐹𝑎𝑢𝑙𝑡 𝑐𝑜𝑣𝑒𝑟𝑎𝑔𝑒 = # 𝑓𝑎𝑢𝑙𝑡𝑠 𝑝𝑜𝑠𝑠𝑖𝑏𝑙𝑒 Defect Level (DL)
▪ Fault coverage is a measure of quality of testing ▪ Ratio of chips that are “bad” or faulty
among the chips that have PASSED
the tests
▪ Practically achieving 100% fault coverage is ▪ Measured in parts per million (ppm)
challenging
▪ We try to attain more than 99% coverage ▪ DL is a measure of effectiveness of
▪ Some faulty products can reach the end user the tests (if test is fully effective,
because the employed set of test patterns may then 𝐷𝐿 = 0)
not cover/test all possible faults ▪ For commercial chips 𝐷𝐿 < 500 𝑝𝑝𝑚

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 19

Design For Test (DFT)

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 20

 References
▪ S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge: Cambridge University Press,
2023.

soprotection.com VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 21

VLSI DESIGN FLOW: RTL TO
GDS

Lecture 8
Overview of VLSI Design Flow: VI
Sneh Saurabh
Electronics and Communications
Engineering
IIIT Delhi
Lecture Plan

VLSI Design Flow: S. Saurabh Overview of VLSI Design Flow 2

 Post-GDS Processes

VLSI Design Flow: S. Saurabh Overview of VLSI Design Flow 3

Mask Fabrication
▪ Mask is the replica of the patterns on a given layer of
the layout created on a substrate (glass) for transferring
pattern during photolithography

▪ We need to fabricate mask before fabricating the

corresponding IC

Mask fabrication typically involves following steps:

▪ Data preparation
▪ Mask writing and chemical processing
▪ Quality checks and adding protections
Source:
https://commons.wikimedia.org/wiki/File:Se
miconductor_photomask.jpg Peellden, CC BY-
SA 3.0
<https://creativecommons.org/licenses/by-
sa/3.0>, via Wikimedia Commons

VLSI Design Flow: S. Saurabh Overview of VLSI Design Flow 4

Mask Writing, Quality Checks and Protection
Data preparation: Mask Writing
▪ Translate the layout-specified mask information to ▪ Start with chromium and photoresist
a format comprehended by a mask writing tool coated on glass or quartz (blank)
➢ Convert complicated polygons to simpler ▪ Pattern written on the blank by
rectangles and trapeziums (fracturing) exposing to LASER or electron beam
▪ Augment mask data to enhance resolution ▪ Photoresist is developed, chromium is
etched and then photoresist is
stripped

Quality checks and protection

▪ Inspect for defects by scanning its
surface and comparing it with the
reference image
▪ If a defect is beyond tolerance, we
repair it with the help of LASER
▪ Finally, protective cover called
pellicle is applied
VLSI Design Flow: S. Saurabh GDS to Chip: Overview 5
Resolution Enhancement Techniques (RET)
▪ If mask is patterned exactly as in GDS, then
features obtained on silicon is distorted
➢ Due to physical effects such as
diffraction

▪ Resolution Enhancement Techniques (RET):

mask is pre-compensated such that the
features obtained on the mask is same as
is desired
➢ Examples: Optical Proximity Correction
(OPC) and Double/Multi-Patterning

VLSI Design Flow: S. Saurabh Overview of VLSI Design Flow 6

RET: Optical Proximity Correction (OPC)

▪ Printing mask patterns

smaller than the light
wavelength produces
distortions

▪ E.g.: rounding of corners

and line-end pullback.

Optical Proximity Correction

(OPC)
▪ Add appropriate serifs,
hammerheads, and mouse
bites to the mask
▪ Improves the resolution of
photolithography by
compensating errors due to
diffraction etc.
VLSI Design Flow: S. Saurabh Overview of VLSI Design Flow 7
RET: Double- or Multiple-patterning
▪ Limited resolution of photolithography, pose problems in printing closely spaced features on
a die (leads to overlaps)

▪ We can solve the problem by increasing the spacing between features printed at a time

Double- or Multi-patterning

▪ Decompose a closely spaced layout into

two or more layouts (assign colors to
features)

▪ We use different masks and different

exposures for layout features of different
colors.

▪ Each exposure needs a lower resolution

due to decreased feature or pattern
density.

VLSI Design Flow: S. Saurabh Overview of VLSI Design Flow 8

Wafer Fabrication and Die Testing
Wafer Fabrication ▪ Fabrication is done layer by layer
▪ Actual fabrication of design on the ➢ Front End Of the Line (FEOL) processes:
silicon wafer is carried out fabricate circuit elements such as
▪ Based on photolithography resistors, capacitors, diodes, and
transistors on the lower layers
▪ Consist of hundreds of individual
process steps ➢ Back End Of the Line (BEOL) processes:
make interconnections using metallic
layers at the top of the wafer

Die Testing
▪ Each die is tested and compared with the expected pattern
▪ Bad dies are marked and not packaged

VLSI Design Flow: S. Saurabh Overview of VLSI Design Flow 9

Packaging
Packaging Various types and materials are
used for package
▪ We encapsulate a die in a supporting case known as a
package to form a chip. Dual in-line
package
Functions of a package (DIP)
Source:
https://commons.wi
1. Package provides pins for connecting to external kimedia.org/wiki/File
environment :Three_IC_circuit_chi
ps.JPG
➢ Characteristics of the package have great impact
on the delay of the signal entering/leaving the
chip Ball grid
➢ Needs to be carefully designed array (BGA)

2. Package allows dissipation of heat and must be

carefully designed
Source:
3. Package prevents from mechanical damage and https://commons.wikimedia.org/wiki/File:Solder_ball
_grid.jpg Janke at English Wikipedia, CC BY-SA 3.0
corrosion <https://creativecommons.org/licenses/by-sa/3.0>,
via Wikimedia Commons
VLSI Design Flow: S. Saurabh Overview of VLSI Design Flow 10
Final Testing and Binning
Final Testing Finished/Tested chips
▪ Final testing is done to check if packaging is ▪ Can be sent to market directly for sale
fine ▪ Can be integrated with other chips to form
▪ Burn-in testing: infant mortality a product and then sent to market for sale

Binning
▪ Classification based on characteristics such
as maximum frequency and power dissipation
▪ Statistical variations in performance
▪ On-chip delay measurement circuitry
▪ Assign performance-based price points to
different bins.

VLSI Design Flow: S. Saurabh Overview of VLSI Design Flow 11

 References
▪ S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge: Cambridge University Press,
2023.
▪ R. Seisyan. “Nanolithography in microelectronics: A review.” Technical Physics 56, no. 8
(2011), p. 1061.

inprotected.com VLSI Design Flow: S. Saurabh Overview of VLSI Design Flow 12