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Tcl API Overview Lab 1-1

Custom Compiler P-2019.06 Copyright © 2021 Synopsys, Inc. All rights reserved.
1 Tcl API Overview

Learning Objectives

The main goal of this lab is to use Custom Compiler TCL

commands to create and edit different types of objects.

After completing this lab, you should be able to:

• Become familiar with Custom Compiler TCL
commands
• Use Custom Compiler TCL help
• Create different objects by TCL
• Setup the created object properties by TCL

Lab Duration:
30 minutes

Lab 1-2 Tcl API Overview

Copyright © 2021 Synopsys, Inc. All rights reserved. Custom Compiler P-2019.06
Introduction
In this lab, you are provided with the OpenAccess database library, technology database library
and a lib.defs file.
Use command -help option to see usage of the command and command option descriptions . For
detailed information run de::help -command <ns>::<commandName>.

Tcl API Overview Lab 1-3

Custom Compiler P-2019.06 Copyright © 2021 Synopsys, Inc. All rights reserved.
File Locations

Directory Structure
Tcl_API_Overview_Lab1 Current working directory
PLL OpenAccess Design library
getInstPinOrigin.tcl TCL procedure to return
instance pin origin
lib.defs Library Definitions file

Relevant Files
../PDK Technology Library

Lab 1-4 Tcl API Overview

Copyright © 2021 Synopsys, Inc. All rights reserved. Custom Compiler P-2019.06
Instructions

Task 1. Start Custom Compiler

1. In the Unix terminal window change your current working directory to
Tcl_API_Overview_Lab1. This will be your working directory for this lab.

Unix% cd Tcl_API_Overview_Lab1

2. Start Custom Compiler from the Unix prompt.

Unix% custom_compiler &

Task 2. Creating new library

1. Create new library “SampleLib” in your current working directory using
dm::createLib command.
1.1. Open lib.defs file by text editor and observe updates
2. Attach reference40nm technology to the new created library using db::attachTech
command.
2.1. Open Library Attributes form Library Manager and observe. Select the
SampleLib library from Library Manager "Right Click" > "Library
Attributes".

Task 3. Creating cellViews

1. Create new schematic cellView for vco_tb cell using dm::createCellView command,
in newly created library. Following options should be specified for
dm::createCellView command:
• -viewType : schematic
• -cell : [dm::findCell vco_tb –libName SampleLib]
Note: The dm::findCell command returns the cell with the specified name
residing in the specified library. The cell might, or might not yet exist on
the disk.

Task 4. Copying Cells

1. Copy PLL/vco cell hierarchically into the new created SampleLib library using
dm::copyCells command with following options:

Tcl API Overview Lab 1-5

Custom Compiler P-2019.06 Copyright © 2021 Synopsys, Inc. All rights reserved.
 • sourceCells : [dm::findCell vco –libName PLL]
• -libDestName : SampleLib
• -cellDestName : vco
• -hier : true
• -update: true
• -updateSearch : destinationLib
• -excludeLibs : {analogLib sheets basic reference40nm }
2. Library Manager window for the SampleLib should look like as shown in the
image:

3. Open schematic or layout views of the copied vco cell and observe the hierarchy.

Task 5. Creating design objects: Layout Editor

1. Source getInstPinOrigin.tcl TCL script in CD console. It will load getInstPinOrigin
procedure which gets the instance pin origin.
Note: Open getInstPinOrigin.tcl by text editor and observe the routine.

Lab 1-6 Tcl API Overview

Copyright © 2021 Synopsys, Inc. All rights reserved. Custom Compiler P-2019.06
 2. Open PLL/test/layout design by de::open command.
• To be able to the cellView we first of need to find that cellView. To find the
cellView use dm::findCellView command.
• After finding the cellView object, pass that object to de::open command.
Note: de::open command returns context object. You can open cellView in
headless mode, if you want to work in batch mode.

Note: If you press tab after de::open command a list of available libraries is
brought up. Using successive tabs you can select the required cellView

3. Uses the following command to return deFigure objects of instances.

set bbox [db::getAttr bBox -of [ed]]

set fig0 [de::getFigures $bbox -design [ed] -filter {%object.name == "I0"}]
set fig1 [de::getFigures $bbox -design [ed] -filter {%object.name == "I1"}]

4. Align instances by le::align command using the following options:

Tcl API Overview Lab 1-7

Custom Compiler P-2019.06 Copyright © 2021 Synopsys, Inc. All rights reserved.
 • Object to align: $fig1
• Source object: $fig0
• Direction: right
• Side: top
• Distance: 0
5. The layout view should look like as shown in the image:

6. Make sure that view depth (leStopLevel) is greater than 0. Generate shapes on {m1
drawing} lpp they should overlap shapes on {m1 pin} lpp in 1x level of hierarchy for
each deFigure, using le::generateShapes command.
7. Create Path connecting I0:Z terminal with I1:A terminal using le::createPath
command.
• Lpp: {m1 drawing}
• Width: 0.12
• Points: To get start/end points use getInstPinOrigin procedure.

Example:
set startPoint [getInstPinOrigin I0 Z]

Lab 1-8 Tcl API Overview

Copyright © 2021 Synopsys, Inc. All rights reserved. Custom Compiler P-2019.06
 Task 6. Creating design objects: Schematic Editor
1. Open SampleLib/vco_tb/schematic by de::open command. Save the de::open
command returned context in variable names ctx i.e. set ctx [de::open …..]
2. Add SampleLib/vco/symbol instance in opened design by se::createInst command.
• instName : vco
• -origin : {1 1}
3. Add analogLib/vpulse/symbol instance in opened design by se::createInst
command
• Origin : {0.5 0.5}
• instName : v1
• Params : {v1 1 pw 500n per 1500n tr 50n tf 50n}
➢ Voltage1 : v1 = 1
➢ Pulse Width : pw = 500n
➢ Period : per = 1500n
➢ Rize Time : tr = 50n

Tcl API Overview Lab 1-9

Custom Compiler P-2019.06 Copyright © 2021 Synopsys, Inc. All rights reserved.
 ➢ Fall Time : tf = 50n
4. Create wire connecting vco:LFIN pin to the v1:PLUS pin, by se::createWire
command.
a. To get start/end points use getInstPinOrigin procedure.

Example:
set startPoint [getInstPinOrigin vco LFIN]

Lab 1-10 Tcl API Overview

Copyright © 2021 Synopsys, Inc. All rights reserved. Custom Compiler P-2019.06
Answers and Solutions

Task 2. Creating new library

dm::createLib SampleLib -path sampleLib

db::attachTech SampleLib -refLibName reference40nm

Task 3. Creating cellViews

set cell [dm::findCell vco_tb -libName SampleLib]

dm::createCellView schematic -cell $cell \
-viewType schematic}

Task 4. Copying Cells

set srcCell [dm::findCell vco -libName PLL]

set excludeLibs [list analogLib sheets basic
reference40nm]
dm::copyCells $srcCell -cellDestName vco \
-libDestName SampleLib -hier true -update true \
-updateSearch destinationLib \
-excludeLibs $excludeLibs

Task 5. Creating Design Objects: Layout Editor

1. source getInstPinOrigin.tcl
2. set ctx [de::open [dm::findCellView layout -
cellName test -libName PLL]]
set design [db::getAttr editDesign –of $ctx]
3. set bbox [db::getAttr bBox -of $design]

Tcl API Overview Lab 1-11

Custom Compiler P-2019.06 Copyright © 2021 Synopsys, Inc. All rights reserved.
 set fig0 [de::getFigures $bbox -design $design -
filter {%object.name == "I0"}]
set fig1 [de::getFigures $bbox -design $design -
filter {%object.name == "I1"}]

4. le::align $fig1 -src $fig0 -direction right -side

top -distance 0
5. le::generateShapes $fig0 -lpp1 {m1 pin} -lpp2 {m1
pin} -lpp {m1 drawing} -levels 1 -operation and
le::generateShapes $fig1 -lpp1 {m1 pin} -lpp2 {m1
pin} -lpp {m1 drawing} -levels 1 -operation and
6. set p1 [getInstPinOrigin I0 Z]
set p2 [getInstPinOrigin I1 A]
le::createPath [list $p1 $p2] -design $design -lpp
{m1 drawing} -width 0.12

Task 6. Creating Design Objects: Schematic Editor

set ctx [de::open [dm::findCellView schematic -cellName

vco_tb -libName SampleLib] ]
set design [db::getAttr editDesign -of $ctx]
se::createInst vco -design $design -origin {1 1} -
libName SampleLib -cellName vco -viewName symbol
se::createInst v1 -design $design -origin {0.5 0.5} -
libName analogLib -cellName vpulse -viewName symbol -
params {v1 1 pw 500n per 1500n tr 50n tf 50n}
set sp [getInstPinOrigin vco LFIN]
set ep [getInstPinOrigin v1 PLUS]
se::createWire [list $sp $ep] -design $design

Lab 1-12 Tcl API Overview

Copyright © 2021 Synopsys, Inc. All rights reserved. Custom Compiler P-2019.06