Synchronous Sequential Logic

Sequential Circuits

Every digital system is likely to have combinational

circuits, most systems encountered in practice also
include storage elements, which require that the
system be described in term of sequential logic.

1
 Synchronous Clocked
Sequential Circuit
A sequential circuit may use many flip-flops to store
as many bits as necessary. The outputs can come
either from the combinational circuit or from the flip-
flops or both.

2
 Latches SR Latch

The SR latch is a circuit with two cross-coupled NOR

gates or two cross-coupled NAND gates. It has two
inputs labeled S for set and R for reset.

3
SR Latch with NAND Gates

4
 SR Latch with Control Input
The operation of the basic SR latch can be modified
by providing an additional control input that
determines when the state of the latch can be
changed. In Fig. 5-5, it consists of the basic SR latch
and two additional NAND gates.

5
 D Latch
One way to eliminate the undesirable condition of
the indeterminate state in SR latch is to ensure that
inputs S and R are never equal to 1 at the same time
in Fig 5-5. This is done in the D latch.

6
 Graphic Symbols for latches

A latch is designated by a rectangular block with

inputs on the left and outputs on the right. One
output designates the normal output, and the other
designates the complement output.

7
 Flip-Flops

The state of a latch or flip-flop is switched by a

change in the control input. This momentary change
is called a trigger and the transition it cause is said to
trigger the flip-flop. The D latch with pulses in its
control input is essentially a flip-flop that is triggered
every time the pulse goes to the logic 1 level. As long
as the pulse input remains in the level, any changes
in the data input will change the output and the state
of the latch.

8
 Clock Response in Latch

In Fig (a) a positive level response in the control

input allows changes, in the output when the D
input changes while the clock pulse stays at logic 1.

9
Clock Response in Flip-Flop

10
 Edge-Triggered D Flip-Flop

The first latch is called the master and the second

the slave. The circuit samples the D input and
changes its output Q only at the negative-edge of the
controlling clock.

D 110011…
Y 110011…
Q ? 1 1 0 0 1 ….
CLK

11
 D-Type Positive-Edge-Triggered Flip-
Flop

Another more efficient construction of an edge-

triggered D flip-flop uses three SR latches. Two
latches respond to the external D(data) and
CLK(clock) inputs. The third latch provides the outputs
for the flip-flop.

Ref. p.175 texts

12
Graphic Symbol for Edge-Triggered D Flip-
Flop

13
 Other Flip-Flops JK Flip-
Flop
There are three operations that can be performed
with a flip-flop: set it to 1, reset it to 0, or
complement its output. The JK flip-flop performs all
three operations. The circuit diagram of a JK flip-flop
constructed with a D flip-flop and gates.

14
 JK Flip-Flop
The J input sets the flip-flop to 1, the K input resets it
to 0, and when both inputs are enabled, the output is
complemented. This can be verified by investigating
the circuit applied to the D input:
D = J Q` + K` Q

15
 T Flip-Flop
The T(toggle) flip-flop is a complementing flip-flop
and can be obtained from a JK flip-flop when inputs
J and K are tied together.

16
 T Flip-Flop

The T flip-flop can be constructed with a D flip-flop

and an exclusive-OR gates as shown in Fig. (b). The
expression for the D input is

D=T Q = TQ` + T`Q

17
 Characteristic
Equations
D flip-flop Characteristic Equations

Q(t + 1) = D

JK flip-flop Characteristic Equations

Q(t + 1) = JQ` + K`Q

T flip-flop Characteristic Equations

Q(t + 1) = T Q = TQ` + T`Q

18
 Direct Inputs

Some flip-flops have asynchronous inputs that are

used to force the flip-flop to a particular state
independent of the clock. The input that sets the flip-
flop to 1 is called present or direct set. The input that
clears the flip-flop to 0 is called clear or direct reset.
When power is turned on a digital system, the state
of the flip-flops is unknown. The direct inputs are
useful for bringing all flip-flops in the system to a
known starting state prior to the clocked operation.

19
 D Flip-Flop with Asynchronous
Reset

A positive-edge-triggered D flip-flop with

asynchronous reset is shown in Fig(a).

20
D Flip-Flop with Asynchronous
Reset

21
 Analysis of Clocked Sequential Circuits

The analysis of a sequential circuit consists of

obtaining a table or a diagram for the time sequence
of inputs, outputs, and internal states. It is also
possible to write Boolean expressions that describe
the behavior of the sequential circuit. These
expressions must include the necessary time
sequence, either directly or indirectly.

22
 State Equations

The behavior of a clocked sequential circuit can be

described algebraically by means of state equations.
A state equation specifies the next state as a
function of the present state and inputs. Consider
the sequential circuit shown in Fig. 5-15. It consists
of two D flip-flops A and B, an input x and an output
y.

23
Fig. Example of Sequential Circuit

24
 State Equation
A(t+1) = A(t) x(t) + B(t)
x(t)

B(t+1) = A`(t) x(t)

A state equation is an algebraic expression that
specifies the condition for a flip-flop state transition.
The left side of the equation with (t+1) denotes the
next state of the flip-flop one clock edge later. The
right side of the equation is Boolean expression that
specifies the present state and input conditions that
make the next state equal to 1.
Y(t) = (A(t) + B(t)) x(t)`

25
 State Table

The time sequence of inputs, outputs, and flip-flop

states can be enumerated in a state table
(sometimes called transition table).

26
 State Diagram

The information available in a state table can be

represented graphically in the form of a state
diagram. In this type of diagram, a state is
represented by a circle, and the transitions between
states are indicated by directed lines connecting the
circles.

1/0 : means input =1

output=0

27
 Flip-Flop Input
Equations
The part of the combinational circuit that
generates external outputs is descirbed algebraically
by a set of Boolean functions called output equations.
The part of the circuit that generates the inputs to
flip-flops is described algebraically by a set of
Boolean functions called flip-flop input equations. The
sequential circuit of Fig. 5-15 consists of two D flip-
flops A and B, an input x, and an output y. The logic
diagram of the circuit can be expressed algebraically
with two flip-flop input equations and an output
equation: DA = Ax + Bx
DB = A`x
y = (A + B)x`
28
 Analysis with D Flip-
Flop

The circuit we want to analyze is described by the

input equation DA = A x y
The DA symbol implies a D flip-flop with output A.
The x and y variables are the inputs to the circuit.
No output equations are given, so the output is
implied to come from the output of the flip-flop.

29
 Analysis with D Flip-
Flop
The binary numbers under Axy are listed from 000
through 111 as shown in Fig. 5-17(b). The next state
values are obtained from the state equation A(t+1)
=A x y
The state diagram consists of two circles-one for
each state as shown in Fig. 5-17(c)

30
Analysis with JK Flip-Flops

31
 Analysis with JK Flip-
Flop

The circuit can be specified by the flip-flop input

equations JA = B KA = Bx`
JB = x` KB = A`x + Ax` = A x

32
 Analysis with JK Flip-
Flops
A(t + 1) = JA` + K`A
B(t + 1) = JB` + K`B
Substituting the values of JA and KA from the input
equations, we obtain the state equation for A:

A(t + 1) = BA` + (Bx`)`A = A`B + AB` +Ax

The state equation provides the bit values for the

column under next state of A in the state table.
Similarly, the state equation for flip-flop B can be
derived from the characteristic equation by
substituting the values of JB and KB:

33
 Analysis with JK Flip-
Flops

The state diagram of the sequential circuit is shown

in Fig. 5-19.

34
 Analysis With T Flip-
Flops
Characteristic equation
Q(t + 1) = T Q = T`Q +
TQ`
00/0 : means
state is 00
output is 0

35
 Analysis With T Flip-Flops
Consider the sequential circuit shown in Fig. 5-20.
It has two flip-flops A and B, one input x, and one
output y. It can be described algebraically by two
input equations and an output equation: Use present state
as inputs

TA = Bx
TB = x
y = AB

A(t+1)=(Bx)’A+(Bx)A’
=AB’+Ax’+A’Bx

B(t+1)=xB

36
 Mealy and Moore Models
(1)

• The most general model of a sequential circuit has

inputs, outputs, and internal states. It is customary to
distinguish between two models of sequential circuits:

the Mealy model and the Moore model

• They differ in the way the output is generated.

- In the Mealy model, the output is a function of both
the present state and input.
- In the Moore model, the output is a function of the
present state only.

37
 Mealy and Moore Models
(2)

When dealing with the two models, some books and

other technical sources refer to a sequential circuit as
a finite state machine abbreviated FSM.

- The Mealy model of a sequential circuit is referred to

as a Mealy FSM or Mealy machine.

- The Moore model is refereed to as a Moore FSM or

Moore machine.

38
 5-6 State Reduction and
Assignment

• The analysis of sequential circuits starts from a

circuit diagram and culminates in a state table or
diagram.

• The design of a sequential circuit starts from a

set of specifications and culminates discusses
certain properties of sequential circuits that may
be used to reduce the number of gates and flip-
flops during the design.

39
 State Reduction

• The reduction of the number of flip-flops in a

sequential circuit is referred to as the state-
reduction problem. State-reduction algorithms are
concerned with procedures for reducing the number
of states in a state table, while keeping the external
input-output requirements unchanged.

• Since m flip-flops produce 2m states, a reduction

in the number of states may result in a reduction in
the number of flip-flops. An unpredictable effect in
reducing the number of flip-flops is that sometimes
the equivalent circuit may require more
combinational gates.
40
 State Reduction

Example :

state a a b c d e f f g f ga
input 0 1 0 1 0 1 10 10 0
output 0 0 0 0 0 1 1 0 1 0 0

Initial point

41
 State Reduction
We now proceed to reduce the number of states for
this example. First, we need the state table; it is
more convenient to apply procedures for state
reduction using a table rather than a diagram. The
state table of the circuit is listed in Table 5-6 and is
obtained directly from the state diagram.

42
 State Reduction
States g and e are two such states: they both go to
states a and f and have outputs of 0 and 1 for x=0 and
x=1, respectively. Therefore, states g and e are
equivalent and one of these states can be removed.
The procedure of removing a state and replacing it by
its equivalent is demonstrated in Table 5-7. The row
with present g is
removed and state
g is replaced by state
e each time it occurs
in the next-state
columns.

43
 State Reduction
Present state f now has next states e and f and
outputs 0 and 1 for x=0 and x=1, respectively. The
same next states and outputs appear in the row with
present state d. Therefore, states f and d are
equivalent and state f can be removed and replaced
by d. The final reduced table is shown in Table 5-8. The
state diagram for the reduced table consists of only
five
states and is shown
in Fig. 5-23.

44
State Reduction

45
State Assignment

46
 Design Procedure

The procedure for designing synchronous

sequential circuits can be summarized by a list of
recommended steps.
1. From the word description and specifications of the
desired
operation, derive a state diagram for the circuit.
2. Reduce the number of states if necessary.
3. Assign binary values to the states.
4. Obtain the binary-coded state table.
5. Choose the type of flip-flops to be used.
6. Derive the simplified flip-flop input equations and
output equations.
7. Draw the logic diagram.
47
Design Procedure

48
Synthesis Using D Flip-Flops
A(t + 1) = DA(A, B, x) = ∑ (3, 5,
7)
B(t + 1) = DB(A, B, x) = ∑ (1, 5,
7)
y(A, B, x) = ∑ (6, 7)

49
Synthesis Using D Flip-Flops
DA = Ax +Bx
DB = Ax + B`x
y = AB

50
Synthesis Using D Flip-Flops

51
 Synthesis Using JK Flip-Flops

Different from Table 5-11 !!

Ref. Table 5-1

52
Synthesis Using JK Flip-Flops

53
Synthesis Using JK Flip-Flops

54
 Synthesis Using T Flip-Flops
The synthesis using T flip-flops will be demonstrated
by designing a binary counter. An n-bit binary
counter consists of n flip-flops that can count in
binary from 0 to 2n-1. The state diagram of a 3-bit
counter is shown in Fig. 5-29.

Ref. Table 5-1

55
Synthesis Using T Flip-Flops

56
Synthesis Using T Flip-Flops

57
Synthesis Using T Flip-Flops

58