001.

Which instruction group is NOT in the data manipulation category D

A Arithmetic Instructions B Bit manipulation instructions
C Shift instructions D Branch instruction
002. Internal interrupts are also called as ___________ C
A Interrupt handlers B Interrupt service routines
C Traps D Service interrupts
003. Identify the instruction which is NOT in the group of Data Transfer Instructions D
A LOAD B STORE
C EXCHANGE D NEGATE
004. In which addressing mode the operand is specified in the instruction itself? A
A Immediate Addressing Mode B Register Addressing Mode
C Register Indirect Addressing Mode D Direct Addressing Mode
005. In which addressing mode the effective address is the part of the instruction D
A Immediate Addressing Mode B Register Addressing Mode
C Register Indirect Addressing Mode D Direct Addressing Mode
006. In Which addressing mode the effective address is calculated as follow:Effective C
address = address part of the instruction + content of CPU register
A Immediate Addressing Mode B Register Addressing Mode
C Indirect Addressing Mode D Direct Addressing Mode
007. In which addressing mode the content of the Program Counter is added to the address C
part of the instruction in order to obtain the effective address?
A Register Addressing Mode B Register Indirect Addressing Mode
C Relative Addressing Mode D Direct Addressing Mode
008. What is the another Name of the Next address generator present in micro-programmed A
control unit
A Sequencer B Address calculator
C Address Decoder D Program generator
009. In how many way the next micro instruction address is determined by the next address C
generator
A 2 B 3
C 4 D 5
010. Which among the following does NOT determine the state of the CPU at the end of the C
execution cycle?
A The content of the program counter. B The content of all processor register.
C The content of memory location. D The content of certain state condition.
011. An interrupt arises from illegal or erroneous use of the instruction B
A Software Interrupt B Internal Interrupt
C External Interrupt D Vector interrupt
012. Identify the Program control instruction among the following instructions B
A PUSH B CMP
C XOR D COM
013. Which is NOT the similarity between interrupt procedure and subroutine call B
A It is initiated by internal or external B It stores all registers of processor.
signal or execution of instruction
C It resume backs to earlier program D It supports nested structure
from where it was suspended
014. Which unit among the following is NOT the part of Micro-programmed Control Unit C
A Next address generator B Control Address Register
C Main Memory D Control Memory
015. The following is the symbolic micro-program for which B
 routine
A Add routine B Fetch routine
C Indirect routine D Store routine
016. For decoding of micro-operation fields what size decoder was used? A
A 3X8 Decoder B 4X16 Decoder
C 2X8 Decoder D 5X32 Decoder
017. What are the registers present in the Control unit of micro-programmed control unit B
A PC and DR B SBR and CAR
C AR and PC D CAR and AR
018. A Control Unit whose binary control variable are stored in the memory is called B
________
A Hardwired Control unit B Micro-programmed Control unit
C Programmers Control Unit D Binary Control Unit
019. Each word in the control memory consists of _____ B
A Micro-program B Micro-Instruction
C Control Word D Data Word
020. The micro instruction code format consists of how many micro operation fields: A
A 3 B 7
C 11 D 20
021. How many mapping bits are used during mapping from instruction code to C
microinstruction address
A 2 B 3
C 4 D 5
022. The devices that provide backup storage are called as __________ C
A Main memory B Cache Memory
C Auxiliary Memory D Random Access Memory
023. The memory unit that communicates directly with CPU is: A
A Main memory B Cache Memory
C Auxiliary Memory D Random Access Memory
024. Control Address register is how many bit register B
A 8-bit B 12-bit
C 16-bit D 20-bit
025. What group of letters the CD field in microinstruction uses? B
A U, A, C, S B U, I, S, Z
C A, C, O, S D A, C, S, Z
026. Which is NOT the part of the address sequencer in the micro-program sequencer for D
control memory block diagram
A Multiplexer B Incrementer
C Control Address Register(CAR) D Decoder
027. Control Memory CANNOT be implemented by D
A Volatile Memory B RAM
C Non-Volatile memory D Registers
028. Which is CANNOT be the input to the multiplexer in design of micro-programmed C
control unit
A From SBR B From incrementer
C From CAR D From Address filed in the micro-
instruction of control memory
029. A program whose function is to start the computer software operating when the power C
is turned ON is called__________
 A Operating System B Application software
C Bootstrap loader D Compiler
030. A memory unit accesses by the content is called D
A Read Only Memory B Random Access Memory
C Cache Memory D Associative memory
031. For the size of the RAM 128X8, how many address lines and data lines are required? A
A 128 address lines and 8 data lines B 7 address lines and 8 data lines
C 128 address lines and 3 data lines D 7 address lines and 3 data lines
032. A very high speed memory which is sometimes used to increase the speed of the B
processing by making current programs and data available to the CPU at a rapid rate
is:
A Main memory B Cache Memory
C Auxiliary Memory D Random Access Memory
033. The ________ manages the data transfer between auxiliary memory and main memory C
A Cache Memory B CPU
C I/O processor D DMA
034. The part of the computer system that supervises the flow of the information between B
auxiliary memory and main memory is called _______
A Hard disk unit B Memory management unit
C Execution unit D Instruction unit
035. The device which stores the binary information in the form of electric charges that are D
applied to the capacitors is
A ROM B EPROM
C SRAM D DRAM
036. An n-bit direct map address for cache memory having k-bits for index field and n-k bits B
for tag field can address how many words in a cache memory?
A 2n-k B 2k
C 2n D 2n+k
037. When a new word is loaded from the main memory in to the cache memory its B
corresponding valid bit in cache memory is
A Cleared to 0 B Set to 1
C Removed D Stored
038. Which of the following does NOT support principle of locality of reference . B
A Loops B Interrupts
C Subroutines D Array of numbers
039. What is the significance of key register in Associative memory B
A It holds the searching data B It provides mask for the searching
data
C It holds the matched data word D The comparisons are done in it.
040. Which register is NOT the part of the Associative memory D
A Argument Register B Key Register
C Match register D Shift register
041. Suppose that an Argument register A contains: 101111100 and the Key register K A
contains: 111000000. Which of the following word, the match bit is set?
A 101111111 B 100111100
C 110000000 D 111000000
042. In which write policy, the main memory always contains the same data as cache A
memory?
A Write through policy B Write Back policy
C Write again policy D Write after read policy
043. Each address that is referenced by the CPU goes through an address mapping from B
_______ address to a _______ address in main memory.
A Physical , Virtual B Virtual, Physical
C Physical, Local D Local, Virtual
044. Which among the following is NOT the replacement algorithm for the cache? D
A Lest Recently Used B First-In First-Out
C Random replacement D Last-In First-Out
045. Each cell of the circuit for matching one word in the associative memory requires A
_______
A Two AND gates and One OR gate B One AND gate and One OR gate
C Two AND gates and Two OR gates D One AND gate and Two OR gates
046. For which cache memory mapping technique this advantage Each word of the cache D
can store more than two words of memory under the same index address.
A Direct mapping B Associative mapping
C Two way set associative mapping D Four way set associative mapping
047. In direct mapping of cache memory, the address is divided in to how many fields? A
A 2 B 3
C 4 D 5
048. The input output interface provides a method for transferring information between B
what?
A Peripherals and external I/O devices B Internal storage and external I/O
devices.
C Cache memory and external I/O D Peripherals and Cache memory
devices
049. The efficient method of transferring the data from and to peripherals C
A Programmed I/O B Interrupt-Initiated I/O
C Direct Memory Access. D Serial I/O
050. Which of the following results in a page fault? B
A Errors in the page. B Page not found in the main memory.
C Page not found in the auxiliary D Page not found in the cache memory.
memory.
051. A ________ refers to the organization of address space while ______ refers to the C
organization of the memory space.
A Block, Page B Page frame, Block
C Page, Block D Block, page frame
052. Which is the more efficient way to organize the page table in which the number of B
words equal to the number of blocks in main memory?
A A random memory page table B An associative memory page table
C A direct memory page table D Translation Look-aside Buffer
053. The memory mapping in a paged system, the page number and block number A
respectively are specified by what?
A Address in the page table and B Content in the page table and
Content in the page table Address in the page table
C Page number in the virtual address D Line number in the virtual address
and line number in the virtual address and Page number in the virtual
address
054. Identify the operation performed during bus stealing in DMA B
A The data is transferred directly from B The data is transferred directly from
I/O Processor into the Processor I/O Processor into the Memory
C The data is transferred directly from D The data is transferred directly from
Memory to Memory I/O Processor into the another I/O
Processor
055. Which is the first device to initiate the communication in CPU-IOP communication A
A CPU B I/O Processor
C I/O Device D Memory
056. In parallel priority interrupt, how is the priority decided? C
A According to the position of the B According to the position of the
devices connected in serial order devices connected in parallel order
 C According to the position of the bits in D According to the position of the bits in
the interrupt register. the mask register.
057. Which mechanism transfers data directly into the memory? C
A Programmed I/O B Interrupt-Initiated I/O
C Direct Memory Access. D Serial I/O
058. Which one in the following is NOT done when the interrupt Cycle is executed? A
A SET the Interrupt Enable bit B PC pushed in to the stack
C Transfer interrupt vector address to D Acknowledge the interrupt by
PC enabling the INTACK line
059. The daisy-chaining method of establishing interrupt priority consists of a A
A Serial connection of all the devices B Parallel connection of all the devices
C Serial and parallel combination D Random connection of all the devices
connection of all the devices
060. Which is Asynchronous data transmission method uses two control signals for data C
transmission
A Source initiated strobe control method B Destination initiated strobe control
method
C Handshaking method. D Daisy chaining method
061. What is the disadvantage of strobe method of asynchronous data transfer? A
A It uses one control signal B It uses two control signals
C It uses three control signals D It uses no control signal
062. Which is one of the method for Implementing the priorities for the interrupts A
A Daisy chaining B Locality of reference
C DMA D Handshaking
063. The instructions that are read from memory by the I/O processor are sometimes called B
as
A Objectives B Commands
C Directives D Routines
064. What are software Routines B
A System software in the memory B Program residing in the memory for
handling interrupts
C Application software in the memory D Program residing in the memory for
handling data
065. Which is NOT the part of the parallel priority interrupt hardware D
A Mask Register B Interrupt Register
C Priority Encoder D Address Decoder
066. Who takes care about all data transfers between several I/O units and the memory C
while the CPU is processing another program?
A ALU B Control unit
C I/O processor D Peripheral devices
067. Identify the WRONG reason that explains the need for the Input output interface C
between CPU and the each peripheral
A Data codes and formats in peripheral B Data transfer rate of the peripherals
differ with that of words in CPU and are usually slower than CPU
memory
C Peripherals synchronously transmit D Peripherals manner of operation is
data to CPU and memory different from that of CPU
068. Which is the method for determining the priority of simultaneous interrupts by software B
means?
A Daisy chaining method B Polling method
C Parallel priority interrupt method D Priority encoder method
069. In asynchronous serial data transmission, what is the bit pattern of transmission? D
A {1-Start bit(1)}, {8-character bits} and B {2-Start bits(0)}, {8-character bits} and
{1 or 2-stop bits(0)} {1 or 2-stop bits(1)}
 C {2-Start bits(1)}, {8-character bits} and D {1-Start bit(0)}, {8-character bits} and
{1 or 2-stop bits(0)} {1 or 2-stop bits(1)}
070. The operation of the asynchronous communication interface is initialized by the CPU B
by sending a byte to which register.
A Status register B Control register
C Transmitter register D Receiver register
071. The CPU can transmit next character using asynchronous communication interface by A
reading which register in it.
A Status register B Control register
C Transmitter register D Receiver register
072. Multiprocessors are classified into which group? C
A Multiple instruction stream, Single B Single instruction stream, Multiple
data stream systems(MISD-systems) data stream systems(SIMD-systems)
C Multiple instruction stream, Multiple D Single instruction stream, Single data
data stream systems(MIMD-systems) stream systems(SISD-systems)
073. Which one is NOT the similarity between multiprocessor and multicomputer? B
A supports Concurrent operations B controlled by one Operating system
C handles I/O devices D supports interrupts
074. Identify the device which is neither an Input device nor an Output device. B
A Digital incremental plotter. B Virtual memory
C Optical and magnetic character D Data acquisition equipment
reader
075. Which of the following statement is related to the Non-vectored interrupt? A
A Branch address is assigned to a fixed B Branch address is supplied by the
location in the memory interrupted source
C Branch address is kept in the D Branch address is pushed in to the
separate register stack after interrupt
076. How does CPU finds out the condition of the IOP and I/O devices for data transfer A
A Bits in the status word kept in the B Acknowledgement signal sent by the
memory by the IOP I/O device to the CPU
C Interrupt caused by the CPU D Switching ON and OFF the I/O
device.
077. The data access time in which of the following peripheral device is very slow B
A Magnetic disks B Magnetic tapes
C Compact Disks D Memory sticks
078. In which interconnection network, Each processor bus is connected to each memory C
module
A Cross bar switch B Time shared common bus
C Multiport memory D Hyper cube system.
079. The cross bar switch organization consists of a number of __________ that are placed C
at intersections between processor buses and memory module paths.
A Routers B Gateways
C Cross points D Switches
080. Which of the following correctly defines data dependency? B
A Data stored in memory is used by B Data of one instruction output is used
other processors by next instruction
C Data from I/O device is depends on D Data copied to the registers depends
the device type on the type of the processor.
081. Which can be called as a tightly coupled multiprocessor system? A
A A global common memory that all B An On-chip memory on different
CPUs can access. CPUs
C Read only memory meant for only D Random Access Memory meant for
one processor only one processor
082. Which can be called as a loosely coupled multiprocessor system? D
 A A global common memory that all B Read only memory meant for only
CPUs can access. multiprocessor
C Random Access Memory meant for D All processors have their own local
only multiprocessor memory
083. In omega network, there are exactly how many paths from source to destination? B
A 0 B 1
C 2 D 3
084. In 8X8 omega switching networks, how many destinations can be connected from one C
source node
A 1 B 3
C 8 D 16
085. A cross bar switch organization supports what kind of transfers from all memory B
modules?
A Time slot transfer B Simultaneous transfer
C Multiplexed transfer D Decoded transfer
086. Which of the following is NOT the Disadvantage of Multiprocessor Systems? D
A Multiprocessor systems is quite B All the processors in the
expensive multiprocessor system share the
memory. So a much larger pool of
memory is required as compared to
single processor systems.
C More complex and complicated D Improves the reliability of the system.
operating system is required in
multiprocessor systems.
087. Multiprocessors are mainly classified in to how many types based on their memory A
organization
A 2 B 3
C 4 D 5
088. How the processors relay programs and data to other processors in loosely coupled A
multiprocessors environment?
A Using packets B Using common memory
C Using RAM D Using cache memory
089. The typical control bus control signal does NOT include C
A Memory Read and write B Interrupt request
C Data transfer from memory to CPU D Bus request and bus grant
090. Daisy chain arbitration is also referred to as A
A Serial arbitration B Parallel arbitration
C Dynamic arbitration D branch arbitration
091. The component which is NOT connected to the system bus is___________ D
A CPUs B I/O Processors
C Main Memory D I/O devices
092. Which is NOT the characteristics of Loosely Coupled System/Distributed Memory A
A Tasks and/or processors B Communicates by message passing
communicate in a highly packets consisting of an address, the
synchronized fashion data content, and some error
detection code.
C Overhead for data exchange is high D Distributed memory system
093. Identify the data conflict in the following table( Assume: I - Instruction fetch, A-ALU B
 operation, E-Execute instruction)
A During clock cycle-3 B During clock cycle-4
C During clock cycle-5 D During clock cycle-6
094. The speed of the pipeline processing over an equivalent non-pipeline processing is A
defined by the ratio: (n-no. of tasks, tn time required for n tasks, tp-clock cycle time, k-
no of segments in pipeline)
A B

C D

095. Which algorithm gives the highest priority to the requesting device that has not used B
the bus for longest interval?
A FIFO B LRU
C Polling D Rotating Daisy chain
096. Which is NOT TRUE regarding the serial arbitration A
A The device close to the priority line is B Multiple devices can concurrently
assigned the lowest priority request the use of the bus.
C All devices are connected in serial D It is also known as daisy chain
order arbitration
097. Identify the one which do NOT belong to the dynamic arbitration algorithm D
A FIFO B LRU
C Polling D Serial arbitration
098. Which is the block NOT found in parallel arbitration circuit B
A Bus arbiter B Serial shift register
C Priority encoder D decoder
099. What is the operation performed by bus arbiter? B
A Reduces the bus cycle B Resolves multiple contentions for the
bus access
C Increases the bus width D Allows all devices to access the bus
simultaneously
100. Routing procedure in which interconnection structure is developed by computing the D
XOR of the source node address with the destination node address.
A Cross bar switch B Time shared common bus
C Multiport memory D Hyper cube system.
101. Which is NOT the solution for the data dependency problem in pipeline C
A Hardware interlocks B Operand forwarding
C Branch target Buffer D Delayed loading
102. Which is NOT the solution for the Branch difficulties problem in pipeline A
A Hardware interlocks B Pre-fetch target instruction
C Branch target Buffer D Branch prediction
103. Which of the following is not a Pipeline Conflicts? D
A Resource conflicts B Data dependencies
C Branch difficulties D Load balancing
104. Routing message through an n-cube structure hypercube interconnection may take B
from one to _______ links from the source node to a destination node.
A (n-1) B (n)
C (n+1) D n(n-1)
105. In Flynns classification, which system is not practically constructed and is of only A
theoretical interest.
A Multiple instruction stream, Single B Single instruction stream, Multiple
data stream systems(MISD-systems) data stream systems(SIMD-systems)
C Multiple instruction stream, Multiple D Single instruction stream, Single data
data stream systems(MIMD-systems) stream systems(SISD-systems)
106. This is one type of parallel processing that does not fit into Flynns classification. A
A Pipelining B Instruction stream
C Data stream D Instruction flow
107. The name pipelining implies what? A
A Flow of information analogous to an B Flow of information analogous to an
industrial assembly line random assembly line
C Flow of information analogous to an D Flow of information analogous to an
linear assembly line non-linear assembly line
108. The area of pipeline where the pipeline organization is applicable B
A Decode pipeline and instruction B Arithmetic pipeline and instruction
pipeline pipeline
C Arithmetic pipeline and Decode D Control pipeline and instruction
pipeline pipeline
109. How is the instruction fetch segment of the instruction pipeline is is implemented? A
A In FIFO B In LIFO
C In stack D In Buffers
110. In which procedure, the compiler detects the branch instructions and rearranges the C
machine language code sequence by inserting useful instructions that keep the
pipeline operating without interruption.
A Loop buffer B Branch prediction
C Delayed branch D Branch target buffer
111. Which of the following is NOT the sub operation in instruction cycle? D
A Instruction fetch B Execute instruction
C ALU operation D I/O operation
112. A circuit that detects instructions whose source operands are destinations of the C
instructions farther up in the pipeline.
A Branch Target Buffer B Translation Look aside Buffer
C Hardware interlock D Hardwired control unit
113. Which of the following architecture is NOT suitable for realizing SIMD? C
A Vector processor B Array processor
C Von Neumann D Harvard
114. Which is NOT the advantage of RISC over CISC C
A Single cycle instruction execution B Uses only load and store instructions
for data transfer
C Variable size instructions D Has limited number of instructions
115. Array Processors are put under which of these categories: B
A SISD B SIMD
C MISD D MIND
116. The instruction pipeline operates on stream of instructions by NOT overlapping which D
of the following operation?
A The fetch B The decode
C The execute D The interrupt
117. An attached array processor can be defined as B
A An auxiliary processor attached to B An auxiliary processor attached to the
another auxiliary processor. general purpose processor.
C An auxiliary processor attached with D An auxiliary processor attached with
the memory. I/O devices.
118. Arrange the following instruction sequence steps in proper order1. Fetch instruction A
 from memory 2. Execute the instruction 3. Decode the instruction4. Calculate the
effective address
A 1-3-4-2 B 1-2-3-4
C 1-4-3-2 D 1-2-4-3
119. An array processor is a processor that performs computations on _____ B
A Large array of instructions B Large array of data
C Large array of multi computers D Large array of I/O devices
120. Which is the best known SIMD array processor? A
A the ILLIAC IV computer B the fujitsu VP-2600 computer
C the Cray-2 computer D the ARM computer
121. What is an attached array processor? A
A An auxiliary processor attached to the B A DSP processor attached to the
general purpose processor. general purpose processor.
C An ARM processor attached to the D A array processor attached to the
general purpose processor. general purpose processor
122. Which is the Data transfer instruction in RISC processor A
A Load B Add
C Mov D JMP
123. All data manipulation instructions in RISC processor have_______ operations B
A Register to memory B Register to register
C Memory to register D Memory to memory
124. Identify the element which is not the part of the Processing Element(PE) of SIMD array D
processor
A ALU B Floating point unit
C Working registers D Main memory