Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Chapter 5
Arithmetic Circuits
SKEE2263 Digital Systems

Mun’im/Ismahani/Izam

{[email protected],[email protected],[email protected]}

January 28, 2017

Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Table of Contents

1 Iterative Designs

2 Adders

3 High-Speed Adders

4 Subtractors

5 Condition Codes

6 Multipliers

7 High-Speed Multipliers
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Iterative Designs

a7-0 b7-0

z Logic circuit c A circuit can be

decomposed
into smaller 'bit slice'
blocks to facilitate
y7-0
the design process.

a7 b7 a1 b1 a0 b0

z c

y7 y1 y0
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Half Adder

a b c s
0 0 0 0
a
0 1 0 1 s
b
1 0 0 1
1 1 1 0 c

s = a⊕b
c = ab
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Full Adder
Boolean Expressions

ai bi ci ci+1 si
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0 si = ai ⊕ bi ⊕ ci
1 0 0 0 1 ci+1 = ai bi + ai ci + bi ci
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Full Adder
Two-Level Realization

ai
bi si
ci

c i+1
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Full Adder
Multi-Level, Hierarchical Realization

Half adder
Half adder
ai

bi si

c i+1
ci

si = (ai ⊕ bi ) ⊕ ci
= ai ⊕ bi ⊕ ci
ci+1 = ai bi + (ai ⊕ bi )ci
= ai bi + (ai + bi )ci
= ai bi + ai ci + bi ci
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Full Adder
Schematic for Cascadable Module

ai bi
ai bi

c i+1 FA c c i+1
ci

si
si
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

4-bit Ripple Adder

a3 b3 a2 b2 a1 b1 a0 b0

FA FA FA FA
c4 c3 c2 c1 c0

s3 s2 s1 s0
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Delay Analysis of Cascadable Full Adder

a
2τ
b
2τ s
cin

τ
τ cout
τ
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Delay Analysis of Cascadable Full Adder

Ai
Bi
Si
Ci

Ci+1

Ci →Ci+1 Ai →Ci+1
Ci →Si Ai →Si
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Delay Analysis of 4-bit Adder

a3 b3 a2 b2 a1 b1 a0 b0

8τ 6τ 4τ
c4 2τ
c0
c3 c2 c1

10τ
s3 s2 s1 s0

Delay expression in terms of τ :

tp = [4 + 2(n − 2) + 2]τ = [2n + 2]τ
In “O”-notation, delay is linear with number of bits
O(n)
Generic delay expression:
tp = (n − 1)tcarry + tsum
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Carry Lookahead Adder

Analysis of Carry Behavior

ai bi ci ci+1 Decision gi pi
0 0 0 0 “Carry 0 0
0
0 0 1 0 kill” 0 0
0 1 0 0 0 1
0 1 1 1 “Carry 0 1
ci
1 0 0 0 propagate” 0 1
1 0 1 1 0 1
1 1 0 1 “Carry 1 1
1
1 1 1 1 generate” 1 1

ci+1 = 1 :
when ai = bi = 1 (regardless of the carry in) or,
when ai 6= bi and the carry-in (from the previous stage) is 1
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Carry Lookahead Adder

Derivation of pi , gi

Carry generate (gi ):

a signal that is true when ai bi = 1.

gi = ai bi

Carry propagate (pi ):

propagates the carry-in (ci ) to a stage to the next stage
(i.e., ci+1 ← ci ) if the “half sum” ai ⊕ bi = 1.

pi = ai + bi
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Carry Lookahead Adder

ai bi ai bi

ai
bi si
p g ci

pi

gi
0
ci+1 ci
1
Partial Full Adder (PFA)
pi , gi w.r.t. carries
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Carry Lookahead Adder

Carry-out Equations

c1 = g0 + p0 c0
c2 = g1 + p1 c1
= g1 + p1 (g0 + p0 c0 )
= g1 + p1 g0 + p1 p0 c0
c3 = g2 + p2 c2
= g2 + p2 (g1 + p1 g0 + p1 p0 c0 )
= g2 + p2 g1 + p2 p1 g0 + p2 p1 p0 c0
c4 = g3 + p3 c3
= g3 + p3 (g2 + p2 g1 + p2 p1 g0 + p2 p1 p0 c0 )
= g3 + p3 g2 + p3 p2 g1 + p3 p2 p1 g0 + p3 p2 p1 p0 c0
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Carry Lookahead Adder

Carry Lookahead Generator (CLG)

p3 g3 p2 g2 p1 g1 p0 g0 c 0

c4 c3 c2 c1
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Carry Lookahead Adder

4-bit Carry Lookahead Adder
a3 b3 a2 b2 a1 b1 a0 b0

PFA PFA PFA PFA c c0

s3 s2 s1 s0

g3 p3 c3 g2 p2 c2 g1 p1 c1 g0 p0
c4
Carry Lookahead Generator

Maximum gate delay for the carry generation is 3 τ .

The full adders introduce two more gate delays.
∴ the worst case path is 5 τ .
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Carry Lookahead Adder

12-bit Cascaded Carry Lookahead Adders

a 11-8 b 11-8 a 7-4 b 7-4 a 3-0 b 3-0

4 4 4 4 4 4

4-bit carry c8 4-bit carry c4 4-bit carry

c 12 c0
lookahead adder lookahead adder lookahead adder

4 4 4
s 11-8 s 7-4 s 3-0

Delay to calculate C12 = delay(C0 → C4 ) + delay(C4 → C8 ) + delay(C8 → C12 )

= 3τ + 2τ + 2τ
= 7τ
Delay to calculate S11 = delay(C0 → C12 ) + 2τ
= 7τ + 2τ
= 9τ
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Carry Lookahead Adder

16-bit Carry Lookahead Adder

b 15-12 b 11-8 b 7-4 b 3-0

a 15-12 a 11-8 a 7-4 a 3-0
4 4 4 4 4 4 4 4
t
c 12 c8 c4 c0
CLA' CLA' CLA' CLA'

4 4 4 4
s 15-12 s 11-8 s 7-4 s 3-0
P3 G3 P2 G2 P1 G1 P0 G0

c 16 Group Carry Lookahead Logic

Total delay = 10 τ .
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Carry Select Adder

a 7-4 b 7-4
4 4

c8,0 4-bit
0
c4 adder
a 7-4 b 7-4
4 4

c8,1 4-bit
1 a 3-0 b 3-0
adder
4 4
4 4
c4 4-bit
1 0 c0
adder

4 4

c8 s 7-4 s 3-0

Total delay = delay of 1 4-bit adder + 2 τ .

Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Carry Save Adder

3:2 Compression Costing Just 2τ

A B C
n n n
A 0 0 1 0 1 1
B 0 1 0 1 0 1
CSA
+ C 1 1 1 1 0 1
S 0 1 0 0 0 1 1
n+1 n+1 C
P 0 1 1 1 0 1 0
Y X 1 0 1 1 1 0 1
(Carry vector) (Bitwise sum)
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Carry Save Adder

Adding 3 numbers using Ripple Carry Adders only

a3 b3 a2 b2 a1 b1 a0 b0

RCA
FA FA FA HA

c3 c2 c1 c0
CPA

HA FA FA FA HA

s5 s4 s3 s2 s1 s0

Delay 30τ
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Carry Save Adder

Adding 3 numbers using Carry Save Adders

a3 b3 c3 a2 b2 c a1 b1 c a0 b0 c0
2 1

CSA
FA FA FA FA

CPA

HA FA FA HA

s5 s4 s3 s2 s1 s0

Delay 14τ
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Adder Delay Summary

Source: http://www.slideshare.net/ankitgoel/cmos-arithmetic-circuits
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Half Subtractor

Input Output
a b r (borrow) d (difference) d = a0 b + ab0
0 0 0 0 =a⊕b
0 1 1 1
r = a0 b
1 0 0 1
1 1 0 0

a
d
b

r
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Full Subtractor

Input Output
a b rin rout d
0 0 0 0 0
d = a0 b0 c + a0 bc0 + ab0 c0 + abc
0 0 1 1 1
0 1 0 1 1 =a⊕b⊕c
0 1 1 1 0
cout = a0 b0 c + a0 bc0 + a0 bc + abc
1 0 0 0 1
1 0 1 0 0 = a0 c + a0 b + bc
1 1 0 0 0
1 1 1 1 1
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Full Subtractor

Half subtractor
Half subtractor
ai
bi di

r i+1

ri
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Ripple Subtractor

a3 b3 a2 b2 a1 b1 a0 b0

FS FS FS FS
r4 r3 r2 r1 r0

d3 d2 d1 d0
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Subtraction by Adding

S =A+B+1
B
n
= A + B∗
A n
= A + (2n − B)
n
B* = A − B + 2n
X Y =A−B
Borrow cn n-bit adder c0 1
where:
n
B: Ones’
A-B complement of B
Difference
B ∗ : Two’s
complement of B
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Adder/Subtractor

a3 b3 a2 b2 a1 b1 a0 b0

1 0 1 0 1 0 1 0

Sub

FA FA FA FA
c4 c3 c2 c1 c0

s3 s2 s1 s0
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Flags

Code Name Significance

Z Zero Result is zero
N Negative Result is < 0
C Carry The most significant bit produced a
carry
V Overflow Result has too many bits to be repre-
sented correctly
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Z Flag

True when all the bits in an n-bit result are 0s.

Z = s0n−1 s0n−2 · · · s01 s00

= (sn−1 + sn−2 + · · · + s1 + s0 )0
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

N Flag

The negative flag (N) is simply the sign bit. When it is high, the
result was less than zero.

N = sn−1
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

C Flag

The carry out from the adder

C = cn
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

V Flag
True when a calculation produces a result that is greater than a
register can store

an−1 bn−1 sn−1 cn−1 cn−2 V

0 0 0 0 0 0
0 0 1 0 1 1
1 1 0 1 0 1
1 1 1 1 1 0

Method 1:

V = an−1 bn−1 s0n−1 + a0n−1 b0n−1 sn−1

Method 2:
V = cn ⊕ cn−1
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Flags Circuit

a 3 b3 a 2 b2 a 1 b1 a 0 b0
Sub
s0 c in
s1
s2 Z

s3 N
c3 c4 c3 c2 c1 c0
C FA FA FA FA
V
c4
C
s3 s2 s1 s0
V
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Deriving Other Relations

Math Flags Flags

Description
Symbol (Unsigned) (Signed)
= Equal Z
6= Not equal Z’
< Less than C’ N⊕V
≤ Less than or equal C’ + Z Z + (N ⊕ V)
≥ Greater than or equal C N V
> Greater than C · Z’ Z’ · (N V)
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Binary Multiplication

1 1 0 1 (13)10 Multiplicand M
× 1 0 1 1 (11)10 Multiplier Q
1 1 0 1
1 1 0 1 Partial
0 0 0 0 Products
1 1 0 1
1 0 0 0 1 1 1 1 (143) 10 Product P

Multiplication is all about:

1 Generating the partial products
2 Adding the partial products
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

2 × 2 Multiplication

b0
a1 a0

a1 a0 b1
a1 a0
× b1 b0
a1 b0 a0 b0
a1 b1 a0 b1
p3 p2 p1 p0 HA HA

p3 p2 p1 p0
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Ripple Carry Array Multiplier

a3b0 a2b0 a1b0 a0b0

a3b1 a2b1 a1b1 a0b1 p0

HA FA FA HA

a3b2 a2b2 a1b2 a0b2 p1

FA FA FA HA

a3b3 a2b3 a1b3 a0b3 p2

FA FA FA HA

p7 p6 p5 p4 p3
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

M × N Array Multiplier Critical Path

Source: http://www.slideshare.net/ankitgoel/cmos-arithmetic-circuits
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Carry Save Adder Multiplier

a3b0 a2b0 a1b0 a0b0

a3b1 a2b1 a1b1 a0b1 p0

HA HA HA

a3b2 a2b2 a1b2 a0b2 p1

FA FA FA

a3b3 a2b3 a1b3 a0b3 p2

FA FA FA

p3

FA FA HA

p7 p6 p5 p4
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Carry Save Adder Multiplier Critical Path

Source: http://www.slideshare.net/ankitgoel/cmos-arithmetic-circuits
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Wallace Tree Multiplier

An application of carry save adder

Source: http://www.slideshare.net/ankitgoel/cmos-arithmetic-circuits
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Multiplication with Constants

Constants with long strings of 0s or 1s can be multiplied

very efficiently using just a few adders.
Remember that shifting a number one bit = multiplication
by 2

2A 2A
<<1 <<1

8A 16A
A <<3 10A A <<4 14A
Iterative Designs Adders High-Speed Adders Subtractors Condition Codes Multipliers High-Speed Multipliers

Lookup Table (LUT) Multipliers

16 x 4
Memory
Multiplicand A3 D3
x[1:0] A2 D2 Product
Multiplier A1 D1 z[3:0]
y[1:0] A0 D0

A1 A0
A3 A2 00 01 10 11
00 0000 0000 0000 0000
01 0000 0001 0010 0011
10 0000 0010 0100 0110
11 0000 0011 0110 1001