Energy Efficient Scheduling

and DVS Processors

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 Introduction
• Energy consumption is an important issue in embedded systems.
– Mobile and portable devices.
– Laptops, PDAs.
– Mobile and Intelligent systems: Digital camcorders, cellular phones, and portable
medical devices.

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Important Facts (1)
• High performance (SPEED) is needed only for a
small fraction of time, while for the rest of time, a low-
performance, a low-power processor would suffice.

Peak Computing
Work load Rate is needed

Average
rate would
suffice

Time

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Important Facts (2)
• Processors are based on CMOS technology where
dynamic power is the bottleneck
Dynamic power (due to switching activity)
• E = V2 / R E α V2
• P = E/T P α V2 /T P α V2 . F
• Vα F V: voltage; P: power; E: Energy
• E=P*T T = CC / F
• Ei = K . cci . F2

Where T : execution time;

CCi : # clock cycles of task Ti.
F : frequency at which Ti is run.

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• Static power = V*Ileak
where
• Ileak is the leakage current
• V is the applied voltage
• Total power dissipation =Dynamic power
+ Static power
• The goal is how to reduce the total
power consumption

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Dynamic Voltage Scaling
• Minimizing Expected Energy
Consumption in Real-Time Systems
through Dynamic Voltage Scaling

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Problems Theme
• Context: Frame-based hard real time
systems
• Given one or more tasks with
– Same period
– deadline = period
– Order of execution of tasks

• One processor with DVS support

• Goal: Schedule tasks (time allocation,
speed) to minimize expected energy
consumption
Dynamic Voltage Scaling (DVS) processors

• Modern processors operate at multiple

frequency levels.
– Dynamic Voltage Scaling (DVS) techniques
provide the capability for processors to adjust
the speed when executing jobs. Energy
consumption can thus be saved through wise
scheduling.
• The higher the frequency level is the
higher the energy consumption

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Dynamic Voltage Scaling (DVS) processors

Since energy is proportional to F2 , DVS

processors can potentially provide
significant energy savings through
frequency and voltage scaling.

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Example
Some microprocessors today are designed
to have adjustable voltage, so, a 15%
reduction in voltage may result in a 15%
reduction in frequency. What would be the
impact on dynamic energy and on dynamic
power?

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Solution

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Simple DVS-Scheme

DVS

Task queue Next task

Over loaded
Use high speed

f=F
system

Under loaded
Use less speed
f = F/2

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DVS-example
• Consider a task with a computation time 20 units.
Time taken =
t1 (say)
• Energy of task Ti without DVS:

– E1 = K * 20 * F2.

• Energy of Ti with DVS:

– E2 = K * 20 * (F/2)2.

• Clearly, E2 = (E1)/4 Time taken =

t2 = 2 * t1

Therefore, if we reduce the frequency we save energy but, we spend more time
in performing the same computation

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 Energy-Time Tradeoffs

60

40

Energy 20

Savings
10

Time
Simple DVS scheme handling RT-task
• Consider a real-time task T1 = (20, 30)
• Applying the simple DVS scheme
– T1 runs at maximum frequency (F) and
meets the deadline with no energy savings

– T1 runs at half the maximum frequency

(F/2) and completes at time = 40 thereby
missing its deadline

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Simple DVS scheme handling RT-task
No DVS
Frequency

F
20@F

20 30
time
Inference:
DVS cannot be
blindly applied to
DVS: Low workload real-time
embedded
Frequency

systems
F

F/2
20@(F/2)
20 40 time

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Energy aware scheduling in RT Systems

 Objectives
 Minimizing energy consumption
 Meeting the deadlines

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Problems & System Models

Problems

Intra-Task DVS Inter-Task DVS Hybrid

System Model

Ideal Realistic
Problems
• Intra-Task DVS
– Only one task
– Compute speed of each cycle or group of
consecutive cycles.
• Inter-Task DVS
– Multiple Tasks and their order of execution
– Compute fraction of remaining time to allocate
for each task
– At run time, speed changes only at the
boundary of a task
• Hybrid
– Combine Intra and Inter-task DVS
System Models
• Ideal Model
– Unrestricted continuous speed
– No time or energy overhead for changing
speed
– Well defined power-frequency relation.
p(f) = c0+c1f α
• Realistic Model
– Predefined set of discrete speeds
– Changing speed costs time and energy
overhead
– No assumption on power-frequency relation
Inter-task EDF

• Static voltage scaling EDF

• Cycle conserving RT-DVS

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 Static Voltage Scaling EDF: Motivation
Pre-run schedule with holes
WCi = worst case computation time @ Fmax Next arrival
of T1

wc1 wc2 wc3 wc4

Holes in the pre-run schedule imply:

EDF Test:

∑(wci/pi) < 1 (at frequency = Fmax)

In other words, whenever ∑(wci/pi) < 1 there are holes in the EDF
schedule

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Static Voltage Scaling EDF: exploiting holes
Pre-run schedule with holes
WCi = worst case computation time @ Fmax Next arrival
of T1

wc1 wc2 wc3 wc4

Processor typically idles

during holes.
Instead, the holes can be
exploited to slowdown the
processor to save energy

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 Static Voltage Scaling EDF
Next arrival
of T1

wc1 wc2 wc3 wc4

K*wc1 K *wc2 K * wc3 K * wc4

EDF Test:

∑(wci/pi) < 1 at maximum frequency = Fmax

Static-VS EDF Test:

K* [∑(wci/pi)] = 1 at frequency = Fmax/K

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Static voltage scaling: Example
• Task set: T1 = (1, 4) and T2 = (2, 8)
• U = 1/4 + 2/8 = 0.5 (< 1) @ Fmax

• What is the “k” at which the task set is

still schedulable @ (Fmax / k):
– U = (1*k)/4 + (2*k)/8 = k*(0.5) = 1
–k=2
– Therefore, we can operate at f = Fmax / 2
and still meet the deadlines

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 Static voltage scaling: Example
Task set: T1 = (1, 4) and T2 = (2, 8)
U = 1/4 + 2/8 = 0.5 (< 1) @ Fmax

Fm
Frequency

0 1 3 4 5 8 Time

Finding the right frequency scaling parameter (say, k)

U = (1*k)/4 + (2*k)/8 = 0.5*k = 1 @ (Fmax/k)
This gives, k = 2. Therefore, operating frequency = Fmax/2

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 Static voltage scaling: Example
The previous task is modified Task set @ (Fmax/2):
T1 = (2, 4) and T2 = (4, 8)
U = 2/4 + 4/8 = 1 @ (Fmax/2)

Energy consumption:
Fm 1*F^2 + 2*F^2 = 3F^2
Frequency

0 1 3 4 5 8 Time

Energy consumption:
Fm 1*(F/2)^2 + 2*(F/2)^2 = (¾)F^2
Frequency

Fm / 2

0 2 6 8 Time

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What if Ci < WCi ?
Actual
computation
time Next arrival
of T1

K*c1 K *c2 K * c3 K * c4

More holes left unexploited

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What if Ci < WCi ?
Actual
computation
time Next arrival
Task T1 completes before of T1
its WCET

K*c1 K *wc2 K * wc3 K * wc4

Hole of size = (wc1 – c1)

Slow down all these tasks
proportionally

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What if Ci < WCi ? (contd..)

Next arrival
of T1

K*c1 K’ *wc2 K’ * wc3 K’ * wc4

CPU Cycles are conserved by slowing down the

remaining tasks

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 Cycle Conserving EDF

• Idea: When a task is released, we cannot know how

much computation it will actually require, so we
safely assume it to be worst case.

• When task is completed, actual cycles are compared

with worst case and surplus time is given to run
other remaining tasks at lower frequency instead of
doing more work.

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Cycle Conserving EDF Example
• Task set: T1 = (3, 6) and T2 = (6, 12)
• U = 3/6 + 6/12 = 1 @ Fmax

• What is the “k” at which the task set is

still schedulable @ (Fmax / k):
– U = (3*k)/6 + (6*k)/12 = k*(1.0) = 1
–k=1
– Therefore, we should operate at f = Fmax in
order to meet all the deadlines

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 Cycle Conserving EDF Example
If task T1 just
completes in • T1 = (3, 6) and T2 = (6, 12)
one unit
creating holes

Fm
Frequency

T1 T2 T1

What is the new frequency that can be

used and still the deadline can be met?
1 3 6 9 12 Time

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Cycle conserving EDF: Example

New utilization = 1/6 + 6/12 = 0.67

Finding the right “k”
1/6 + (6*k)/12 = 1
K = 5/3
New freq = (3/5) Fmax
Fm
Frequency

T1
T2

0 1 3 6 9 12 Time

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Intra Task Energy Management
• Intra-task DVS: adjusts the voltage and
clock speed within a task.

• Identifies the slack time generated within

a task due to workload variation.

• Application code is pre-processed to

enable the run-time clock/voltage
adjustment.

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 Intra-task DVS Voltage
scheduling
B1 points
Intra-task RT-DVS 20
Intra-task DVS algorithms
typically work with the control
flow graph (CFG) of the real-time
programs.
Each node in the CFG denotes B2 20 10
a basic block of computation.
B3
 The edges in the CFG indicate
the control dependency between
the blocks.
B4
Objective is to assign proper Different paths B5
clock frequency to each of the 10 150
P1: B1, B2.
basic blocks so as to minimize
the total energy consumption P2: B1, B3, B4.
Deadline = 200
while meeting the task deadline. P3: B1, B3, B5.

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 Simple Intra-task DVS: example

B1
Fmax 20

40@Fmax

40
B2 20 B3 10
Fmax

Deadline = 40
30@Fmax

At time = 20,
20 30 40 We know the exact
branch

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 Simple Intra-task DVS: example

B1
Fmax 20

40@Fmax

40
B2 20 B3 10
Fmax

Deadline = 40
20
10@(Fmax/2)
At time = 20,
20 40 We know the exact
branch

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