UNIT 2

Input/output Organisation - Accessing of I/O devices - Memory mapped I/O, Program

controlled I/O, Interrupts - Interrupt hardware, Handling Multiple Interrupts – Direct Memory
Access (basic concept only)
Standard I/O interfaces (General features only) - PCI, SCSI, USB
Computer Peripherals (General features only) - Input Devices - Keyboard, Mouse, Scanner -
Output Devices - Video Displays, Flat Panel Displays, Printers, Graphics Accelerators.

ACCESSING I/O DEVICES

The simplest way to connect an I/O device to the computer is to use a single bus
arrangement. The bus connects all the devices through three sets of lines; address, data and
control. Each I/O device is assigned a unique address. When processor places the particular
address on address bus, the corresponding I/O device will respond. Depending on the read or
write request, the requested data are transferred through data lines.

Special hardware is necessary to interface the I/O devices with the microprocessor. The
address decoder enables the device to recognise its address when this address is available in
the address bus. The data register holds data being transferred to or from the processor. The
status registers contain the information relevant to the operation of the I/O device. The address
decoder, data and status registers and the control circuitry required to coordinate the I/O
transfer constitute device’s interface circuit
MEMORY MAPPED I/O
When the I/O devices and memory shares the same address space, the arrangement is
called memory mapped I/O. With memory mapped I/O, each instruction that can access
memory can be used to transfer data to or from an I/O device. For example, if DATAIN is the
address of the input buffer of a keyboard, the instruction MOVE DATAIN, R0 will read the
DATAIN and stores them into R0. Similarly, MOVE R0, DATAOUT will store the content of
R0 at the location DATAOUT, which may be the output data buffer of a display unit or printer.
Most of the computer uses Memory mapped I/O.
Some processors have special instructions IN and OUT for performing I/O transfers.
For example, Intel family processors have special I/O instructions and separate 16bit address
space for I/O devices. When designing a computer system with these processors, the designer
has the option for connecting I/O devices to the special I/O address space or as part of the
memory address space. One advantage of separate address space is that the I/O devices deals
with fewer address lines. While using the same address lines for this fewer I/O address signals,
a separate special signal is used to confirm that it is an I/O operation. When this signal is active,
the memory unit ignores the requested transfer. This technique, which uses separate address
space for I/O devices is termed as I/O mapped I/O.
PROGRAM CONTROLLED I/O

In program controlled I/O, the processor repeatedly checks a status flag to achieve the
required synchronisation between the processor and I/O device. W say that the processor polls
the device.
Consider the example of I/O operations involving a keyboard and a display device. The
four registers are used in the data transfer operations. STATUS register contains two flags, SIN
and SOUT, which provide the status for the keyboard and display. Two flags KIRQ and DIRQ
are for interrupts. Data from the keyboard are made available in DATAIN and the data sent to
the display are stored in DATAOUT register.

To control the keyboard and display, we need a program. The program should read character
from the keyboard, and stores it in the memory buffer. Then it calls the subroutine PROCESS
to process the input line.
As each character is read, it is displayed in the display. Register R0 is used as a pointer to the
memory buffer area. The contents of R0 are updated using the autoincrement addressing mode,
so that the successive character is stored in successive memory locations. Each character is
checked to see if it is the Carriage Return (CR), which has the ascii code of 0D. if it is, a line
feed character (ASCII code 0A) is sent to move the cursor one line down on the display and
subroutine PROCESS is called. This example illustrates program-controlled I/O.

INTERRUPTS
In polling method, the processor waits for the response form the I/O device. During this wait
period, processor not able to perform useful computation. This causes wastage of effective time
for processing. This can be solved by the technique called Interrupt. In this method, the I/O
device alerts the processor when it becomes ready. It can do so by sending a hardware signal
called Interrupt request to the processor.
Example: Consider a task that requires continuous computations to be performed and the results
to be printed on a printer.
COMPUTE produces a set of n lines output. PRINT routine is executed to send the first line of
text to the printer. At this point, instead of waiting for the line to be printed, the PRINT routine
may be temporarily suspended and execution of COMPUTE routine continued. Whenever the
printer becomes ready, it alerts the processor, by sending an interrupt request signal. In
response to this, processor interrupts the execution of COMPUTE routine and transfers the
control to the PRINT routine. The PRINT routine sends the second line to the printer and is
again suspended. Then the COMPUTE routine resumes the execution and this process
continues until all lines have been printed.
The routine executed in response to the interrupt request is called the Interrupt Service Routine,
which is PRINT in this example.

INTERRUPT HARDWARE
A single interrupt request line may be used to serve n number of devices. All devices are
connected to the line via switches to ground. To request an interrupt, a device closes the switch.
If all the interrupt request lines are inactive, the voltage level is Vdd. When a device closes the
switch, the voltage becomes zero, causing an interrupt request signal received by the processor.
ENABLING & DISABLING INTERRUPTS

The arrival of an interrupt signal from an external device, causes the processor to
suspend the execution of one program and start the execution of another. A fundamental facility
found in all computers is the ability to enable and disable such interruptions.
By using an Interrupt disable instruction, we can disable the further interruptions.
Likewise, interrupt enable instruction will enable the interrupts. The interrupt disable
instruction clears the interrupt-enable bit of the flag register, and the interrupt enable instruction
sets the interrupt- enable bit.
Another method for enabling and disabling the interrupt is the use of edge triggered
signals. Here, the processor’s interrupt request line responds only to the leading edge of the
signal. In this case, the processor receives only one request, regardless of how long the line is
active. Hence there is no danger of multiple interruptions.
The sequence of events involved in handling an interrupt request from a single device
is as follows
1. The device raises an interrupt request
2. The processor interrupts the program currently being executed
3. Interrupts are disabled by changing the control bit in the flag register (except in the case
of edge triggered interrupts)
4. The device is informed that its request has been recognised, and in response, it
deactivates the interrupt-request signal.
5. The action requested by the interrupt is performed by the interrupt service routine.
6. Interrupts are enabled and execution of the interrupted program is resumed.
HANDLING MULTIPLE INTERRUPTS

Since the devices connected to a microprocessor are operationally independent, there is

no definite order in which they generate interrupt. When a request is received over r the
interrupt line, additional information is necessary to identify the particular device. Furthermore,
if two devices have activated the line at the same time, it must be possible to break the tie and
select one of the two requests for service. The information needed to determine which device
is requesting an interrupt must be available in any of the status registers. When a device raises
an interrupt signal, it sets a bit in the status register. The processor identifies the device by
checking this status register. The simplest way to identify the interrupting device is to have the
interrupt service routine poll all the I/O devices connected to it. The first device encountered
with the status bit set is the device that should be serviced.
Vectored Interrupts: To reduce the polling time, a device requesting the interrupt may
identify itself directly to the processor. Then the processor can immediately start executing the
interrupt service routine. All interrupt schemes based on this approach are called vectored
interrupts. A device requesting an interrupt can identify itself by sending a special code to the
processor over the bus. The code supplied may represent the starting address of the interrupt
service routine.
Interrupt Nesting: The I/O devices should be organised in a priority structure. An interrupt
request from a high priority device should be accepted while the processor is servicing a request
from lower priority device. To implement this, we need to assign priority level, which can be
changed under program control. The processor accepts interrupts from the devices that have
higher priorities.

Another method for implementing multiple interrupts, with priority is the daisy chain method.
Here all the interrupt request lines are connected to the INTR pin of the processor. The INTA
signal is connected in daisy chain manner. The INTA signal is first received by device 1, then
device 1 passes it to device 2, and it goes on. If any device has pending requests, that device
blocks INTA signal, and proceeds to put the identifying code on the data bus. Therefore, the
device that is closest to the processor has the highest priority, the second device in the chain
has second priority and so on.
 We can combine these two techniques to form a general structure in which devices are
organised in groups, each group is connected in different priority level. Within a group, devices
are connected in daisy chain.

DIRECT MEMORY ACCESS

To transfer large blocks of data at high speed, a special control unit may be provided to
allow transfer of data directly between an external device and main memory, without
continuous intervention by the processor. This approach is called Direct Memory Access.
DMA transfers are performed by a control circuit, called DMA controller. It performs the
functions that would normally be carried out by the processor while accessing main memory.
For transfer, it provides the address and all the bus signals required. Since it is a block transfer,
the DMA controller must increment the address for successive locations, and keep track of the
number of transfers.
 To initiate the process, the processor sends the starting address, the number of words in
the block, and the directions of transfer. On receiving the information, the DMA controller
proceeds to perform the operation. When the entire block has been transferred, the controller
informs the processor by raising an interrupt signal. While DMA transfer is taking place, the
program that requested the transfer cannot continue, and the processor can be used to execute
another program. After the DMA is completed, the processor can return to the program that
requested the transfer.
Two registers are used for storing the starting address and word count. The third
register is used for storing the status and control flags. The R/W bit determines the direction of
transfer. When it is 1, data are transferred from memory to I/O device. Otherwise, memory
write operation will be performed. When the controller is ready to receive another DMA
transfer command after the completion of a block of data transfer, the Done bit is set to 1.

There are two modes of DMA operations.

Cycle Stealing mode: - memory access by the processor and the DMA controller are
interwoven. On each transfer, the DMA controller gives the control of the bus back to the
processor. This interweaving technique is called cycle stealing.
Block or Burst Mode: - the DMA controller may be given exclusive access to the main memory
to transfer a block of data without interruption. This is called block or burst mode.