TMS320F28004x Microcontroller

Workshop

Workshop Guide and Lab Manual

Kenneth W. Schachter
Revision 1.0
July 2019
Important Notice

Important Notice
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Copyright  2019 Texas Instruments Incorporated

Revision History
July 2019 – Revision 1.0

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C2000 Training Technical
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ii TMS320F28004x Microcontroller Workshop - Introduction

 TMS320F28004x Microcontroller Workshop

TMS320F28004x Microcontroller Workshop

TMS320F28004x Microcontroller
Workshop

Texas Instruments
C2000 Technical Training

C2000 is a trademark of Texas Instruments. Copyright © 2019 Texas Instruments. All rights reserved.

Workshop Outline
Workshop Outline
1. Architecture Overview
2. Programming Development Environment
• Lab: Linker command file
3. Peripheral Register Programming
4. Reset and Interrupts
5. System Initialization
• Lab: Watchdog and interrupts
6. Analog Subsystem
• Lab: Build a data acquisition system
7. Control Peripherals
• Lab: Generate and graph a PWM waveform
8. Direct Memory Access (DMA)
• Lab: Use DMA to buffer ADC results
9. Control Law Accelerator (CLA)
• Lab: Use CLA to filter PWM waveform
10. System Design
• Lab: Run the code from flash memory
11. Communications (SCI echoback from C2000Ware)
12. Support Resources

TMS320F28004x Microcontroller Workshop - Introduction iii

TMS320F28004x Microcontroller Workshop

Required Workshop Materials

Required Workshop Materials
 http://training.ti.com/c2000-f28004x-
microcontroller-workshop

 F280049C LaunchPad (LAUNCHXL-F280049C)

 Install Code Composer Studio v9.0.1

 Run the workshop installer

F28004x Microcontroller Workshop-1.0-Setup.exe

Lab Files / Solution Files

Workshop Manual

Development Tools
F280049C LaunchPad
XDS110 LED1: XDS110
Debug Power External S1: LED5: GPIO34 (green) J11: S2: Boot J14:
Probe (device) Debug Reset LED4: GPIO23 (red) FSI Modes CAN
Port
J2/J4 * J6/J8 *
XDS110 emulation circuitry

J1/J3 * J5/J7 *

USB101: LED0: JP1-3: USB J101: F280049 J15: JP8 J12/13:

USB Power Power JTAG/UART VREFHI (connects Encoder
Interface (USB) Isolation Isolation 3.3V/5V
to J5/J7)

* = BoosterPack plug-in module connector

iv TMS320F28004x Microcontroller Workshop - Introduction

 TMS320F28004x Microcontroller Workshop

F280049C controlCARD
J1:A - USB S1:A - isolated emulation and S1: Boot LED D2:
emulation/ UART communication enable Modes GPIO31 (red)
UART switch

XDS100v2 emulation
and isolation circuitry
LED D3:
GPIO34 (red)

LED D1:
Power
(green)

J1: FSI

S7: PGA S5: GPIO24

Filter / GPIO25

S8: ADC S6: GPIO26

VREFHI / GPIO27
S4: JTAG S2: GPIO10 S3: GPIO08
/ cJTAG / GPIO35 / GPIO37

controlCARD Docking Station

5 V Power Power Switch LED D1: Analog GPIO
Connector (External / USB) Power (green) Signals Signals

JTAG USB Analog GPIO 180-pin HSEC8 Edge

Connector Connector Signals Signals Card Interface

TMDSHSECDOCK is a baseboard that provides header pin access to key signals on compatible
HSEC180-based controlCARDs. A breadboard area is available for rapid prototyping. Board
power can be provided by either a USB cable or a 5V barrel power supply.

TMS320F28004x Microcontroller Workshop - Introduction v

TMS320F28004x Microcontroller Workshop

vi TMS320F28004x Microcontroller Workshop - Introduction

 Architecture Overview
Introduction
This architectural overview introduces the basic architecture of the C2000™ family of
microcontrollers from Texas Instruments. The F28004x series provides high performance
processing for a variety of system control applications. The C2000 processors are ideal for
applications combining digital signal processing, microcontroller processing, efficient C code
execution, and operating system tasks.

Unless otherwise noted, the terms C28x and F28004x refer to TMS320F28004x family of devices
throughout the remainder of this workshop manual. For specific details and differences between
device family members, please refer to the device data sheet, user’s guides, and the technical
reference manual.

Module Objectives
When this module is complete, you should have a basic understanding of the F28004x
architecture and how all of its components work together to create a high-end, uniprocessor
control system.

Module Objectives

 Review the F28004x block diagram

and device features
 Describe the F28004x bus structure
and memory map
 Identify the various memory blocks on
the F28004x
 Identify the peripherals available on
the F28004x

TMS320F28004x Microcontroller Workshop - Architecture Overview 1-1

Introduction to the TMS320F28004x

Chapter Topics
Architecture Overview ................................................................................................................ 1-1
Introduction to the TMS320F28004x ......................................................................................... 1-3
C28x Internal Bussing ........................................................................................................... 1-4
C28x CPU + FPU + VCU + TMU and CLA ............................................................................... 1-5
Special Instructions ............................................................................................................... 1-6
CPU Pipeline ......................................................................................................................... 1-7
C28x CPU + FPU + VCU + TMU Pipeline ............................................................................ 1-8
Memory ..................................................................................................................................... 1-9
Memory Map ......................................................................................................................... 1-9
Dual Code Security Module (DCSM) .................................................................................. 1-10
Peripherals .......................................................................................................................... 1-10
Fast Interrupt Response Manager .......................................................................................... 1-11
Math Accelerators ................................................................................................................... 1-12
Viterbi / Complex Math Unit (VCU-II) .................................................................................. 1-12
Trigonometric Math Unit (TMU)........................................................................................... 1-13
Configurable Logic Block (CLB) .............................................................................................. 1-14
On-Chip Safety Features ........................................................................................................ 1-15
Summary ................................................................................................................................. 1-16

1-2 TMS320F28004x Microcontroller Workshop - Architecture Overview

 Introduction to the TMS320F28004x

Introduction to the TMS320F28004x

The TMS320F004x are device members of the C2000 microcontroller (MCU) product family.
These devices are most commonly used within embedded control applications. Even though the
topics presented in this workshop are based on the TMS320F28004x device family, most all of
the topics are fully applicable to other C2000 MCU product family members. The F28004x MCU
utilizes the TI 32-bit C28x CPU architecture. The MCU has access to a set of highly integrated
analog and control peripherals, which provides a complete solution for demanding real-time high-
performance signal processing applications, such as digital power, industrial drives, inverters, and
motor control.

TMS320F28004x Block Diagram

The above block diagram represents an overview of the device features; however refer to the
data sheet for details about a specific device family member. The F28004x CPU is based on the
TI 32-bit C28x fixed-point accumulator-based architecture and it is capable of operating at a clock
frequency of up to 100 MHz. The CPU is tightly coupled with a Floating-Point Unit (FPU) which
enables support for hardware IEEE-754 single-precision floating-point format operations. Also, a
tightly coupled Trigonometric Math Unit (TMU) extends the capability of the CPU to efficiently
execute trigonometric and arithmetic operations commonly found in control system applications.
Similar to the FPU, the TMU provides hardware support for IEEE-754 single-precision floating-
point operations which accelerate trigonometric math functions. A Viterbi, Complex Math, and
CRC Unit (VCU) further extends the capabilities of the CPU for supporting various
communication-based algorithms and is very useful for general-purpose signal processing
applications, such as filtering and spectral analysis.

The Control Law Accelerator (CLA) is an independent 32-bit floating-point math hardware
accelerator which executes real-time control algorithms in parallel with the main C28x CPU,
effectively doubling the computational performance. With direct access to the various control and
communication peripherals, the CLA minimizes latency, enables a fast trigger response, and
avoids CPU overhead. Also, with direct access to the ADC results registers, the CLA is able to
read the result on the same cycle that the ADC sample conversion is completed, providing “just-
in-time” reading, which reduces the sample to output delay.

TMS320F28004x Microcontroller Workshop - Architecture Overview 1-3

Introduction to the TMS320F28004x

C28x Internal Bussing

As with many high performance microcontrollers, multiple busses are used to move data between
the memory blocks, peripherals, and the CPU. The C28x memory bus architecture consists of six
buses (three address and three data):
• A program read bus (22-bit address line and 32-bit data line)
• A data read bus (32-bit address line and 32-bit data line)
• A data write bus (32-bit address line and 32-bit data line)

C28x CPU Internal Bus Structure

Program Program Address Bus (22)
PC
Program-read Data Bus (32)
Decoder
Data-read Address Bus (32) Program
Memory
Data-read Data Bus (32)

Registers Execution Debug

ARAU R-M-W TMU
MPY32x32 TR0-TR7
SP Atomic Real-Time Data
ALU ALU VCU Memory
DP @X JTAG
XT VR0-VR8
XAR0 Emulation
P FPU CLA
to R0H-R7H MR0-MR3
XAR7 ACC

Register Bus / Result Bus Peripherals

Data/Program-write Data Bus (32)

Data-write Address Bus (32)

The 32-bit-wide data busses provide single cycle 32-bit operations. This multiple bus architecture
(Harvard Bus Architecture) enables the C28x to fetch an instruction, read a data value and write a
data value in a single cycle. All peripherals and memory blocks are attached to the memory bus
with prioritized memory accesses.

1-4 TMS320F28004x Microcontroller Workshop - Architecture Overview

 C28x CPU + FPU + VCU + TMU and CLA

C28x CPU + FPU + VCU + TMU and CLA

The C28x is a highly integrated, high performance solution for demanding control applications.
The C28x is a cross between a general purpose microcontroller and a digital signal processor
DSP), balancing the code density of a RISC processor and the execution speed of a DSP with
the architecture, firmware, and development tools of a microcontroller.

The DSP features include a modified Harvard architecture and circular addressing. The RISC
features are single-cycle instruction execution, register-to-register operations, and a modified
Harvard architecture. The microcontroller features include ease of use through an intuitive
instruction set, byte packing and unpacking, and bit manipulation.

C28x CPU + FPU + VCU + TMU and CLA

 MCU/DSP balancing code density &
execution time
 16-bit instructions for improved code density
Program Bus
 32-bit instructions for improved execution time
CLA Bus
 32-bit fixed-point CPU + FPU
 32x32 fixed-point MAC, doubles as dual
16x16 MAC
 IEEE Single-precision floating point
32x32 bit R-M-W
hardware and MAC
TMU
Multiplier Atomic CLA  Floating-point simplifies software
VCU
FPU ALU development and boosts performance
PIE  Viterbi, Complex Math, CRC Unit (VCU)
Register Bus 3 adds support for Viterbi decode, complex
CPU 32-bit math and CRC operations
Timers
Watchdog  Parallel processing Control Law Accelerator
(CLA) adds IEEE Single-precision 32-bit
Data Bus floating point math operations
 CLA algorithm execution is independent of
the main CPU
 Trigonometric operations supported by TMU
 Fast interrupt service time
 Single cycle read-modify-write instructions

The C28x design supports an efficient C engine with hardware that allows the C compiler to
generate compact code. Multiple busses and an internal register bus allow an efficient and
flexible way to operate on the data. The architecture is also supported by powerful addressing
modes, which allow the compiler as well as the assembly programmer to generate compact code
that is almost one to one corresponded to the C code.

The C28x is as efficient in DSP math tasks as it is in system control tasks. This efficiency
removes the need for a second processor in many systems. The 32 x 32-bit multiply-accumulate
(MAC) capabilities can also support 64-bit processing, enable the C28x to efficiently handle
higher numerical resolution calculations that would otherwise demand a more expensive solution.
Along with this is the capability to perform two 16 x 16-bit multiply accumulate instructions
simultaneously or Dual MACs (DMAC). The devices also feature floating-point units.

The addition of the Floating-Point Unit (FPU) to the fixed-point CPU core enables support for
hardware IEEE-754 single-precision floating-point format operations. The FPU adds an extended
set of floating-point registers and instructions to the standard C28x architecture, providing
seamless integration of floating-point hardware into the CPU.

TMS320F28004x Microcontroller Workshop - Architecture Overview 1-5

C28x CPU + FPU + VCU + TMU and CLA

Special Instructions
C28x Atomic Read/Modify/Write
Atomic Instructions Benefits
LOAD  Simpler programming
READ

 Smaller, faster code

Registers CPU ALU / MPY Mem
 Uninterruptible (Atomic)
WRITE

STORE  More efficient compiler

Standard Load/Store Atomic Read/Modify/Write

DINT
AND *XAR2,#1234h
MOV AL,*XAR2
AND AL,#1234h 2 words / 1 cycles
MOV *XAR2,AL
EINT
6 words / 6 cycles
Note: Example shows non-atomic assembly instructions vs. atomic assembly instruction; Compiler intrinsics can
be used for generating the atomic assembly instructions if the user needs guaranteed atomicity at the C level

Atomic instructions are a group of small common instructions which are non-interuptable. The
atomic ALU capability supports instructions and code that manages tasks and processes. These
instructions usually execute several cycles faster than traditional coding.

1-6 TMS320F28004x Microcontroller Workshop - Architecture Overview

 C28x CPU + FPU + VCU + TMU and CLA

CPU Pipeline
C28x CPU Pipeline
A F 1 F 2 D1 D2 R1 R2 E W 8-stage pipeline
B F 1 F 2 D1 D2 R1 R2 E W
C F 1 F 2 D1 D2 R1 R2 E W

D F 1 F 2 D1 D2 R1 R2 E W
E & G Access
E F 1 F 2 D1 D2 R1 R2 E W same address
F F 1 F 2 D1 D2 R1 R2 E W

G F 1 F 2 D1 D2 R
R11 R2 RE2 W
E W

H F1 F2 D1 D2 R1 R12 RE2 W
E W

F1: Instruction Address

F2: Instruction Content Protected Pipeline
D1: Decode Instruction
D2: Resolve Operand Addr  Order of results are as written in
R1: Operand Address source code
R2: Get Operand
 Programmer need not worry about
E: CPU doing “real” work
W: store content to memory the pipeline

The C28x uses a special 8-stage protected pipeline to maximize the throughput. This protected
pipeline prevents a write to and a read from the same location from occurring out of order.

This pipelining also enables the C28x CPU to execute at high speeds without resorting to
expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency for
conditional discontinuities. Special store conditional operations further improve performance.
With the 8-stage pipeline most operations can be performed in a single cycle.

TMS320F28004x Microcontroller Workshop - Architecture Overview 1-7

C28x CPU + FPU + VCU + TMU and CLA

C28x CPU + FPU + VCU + TMU Pipeline

C28x CPU + FPU + VCU + TMU Pipeline
Fetch Decode Read Exe Write
F28x Pipeline F1 F2 D1 D2 R1 R2 E W

FPU Instruction D R E1 E2/W

VCU / TMU Instruction D R E1 E2/W

Load
Store
0 delay slot instruction
1 delay slot instruction
Floating-point math operations, conversions between integer and floating-
point formats, and complex MPY/MAC require 1 delay slot – everything else
does not require a delay slot (load, store, max, min, absolute, negative, etc.)

 Floating Point Unit, VCU and TMU has an unprotected pipeline

 i.e. FPU/VCU/TMU can issue an instruction before previous instruction has
written results
 Compiler prevents pipeline conflicts
 Assembler detects pipeline conflicts
 Performance improvement by placing non-conflicting
instructions in floating-point pipeline delay slots

Floating-point unit (FPU), VCU and TMU operations are not pipeline protected. Some
instructions require delay slots for the operation to complete. This can be accomplished by insert
NOPs or other non-conflicting instructions between operations.

In the user’s guide, instructions requiring delay slots have a ‘p’ after their cycle count. The 2p
stands for 2 pipelined cycles. A new instruction can be started on each cycle. The result is valid
only 2 instructions later.

Three general guideslines for the FPU/VCU/TMU pipeline are:

Math MPYF32, ADDF32, 2p cycles

SUBF32, MACF32, One delay slot
VCMPY

Conversion I16TOF32, F32TOI16, 2p cycles

F32TOI16R, etc… One delay slot

Everything else* Load, Store, Compare, Single cycle

Min, Max, Absolute and No delay slot
Negative value

* Note: MOV32 between FPU and CPU registers is a special case.

1-8 TMS320F28004x Microcontroller Workshop - Architecture Overview

 Memory

Memory
The F28004x utilizes a memory map where the unified memory blocks can be accessed in either
program space, data space, or both spaces. This type of memory map lends itself well for
supporting high-level programming languages. The memory map structure consists of RAM
blocks dedicated to the CPU, RAM blocks accessible by the CPU and CLA, RAM blocks
accessible by the DMA module, message RAM blocks between the CPU and CLA, CAN
message RAM blocks, flash, and one-time programmable (OTP) memory. The Boot ROM is
factory programmed with boot software routines and standard tables used in math related
algorithms.

Memory Map
The C28x CPU core contains no memory, but can access on-chip and off-chip memory. The
C28x uses 32-bit data addresses and 22-bit program addresses. This allows for a total address
reach of 4G words (1 word = 16-bits) in data memory and 4M words in program memory.

Simplified F28004x Memory Map

0x000000
M0 RAM (1Kx16)
0x000400 0x00C000
M1 RAM (1Kx16) GS0 – GS3 RAM
(8Kx16 each)
0x000D00 LS0 – LS7 RAM
PIE Vectors 0x049000 accessible by
(512x16) CAN A MSG RAM
(2Kx16) CPU & CLA
0x001480 0x04B000
CLA to CPU MSG CAN B MSG RAM
RAM (128x16) (2Kx16)
0x001500 GS0 – GS3 RAM
CPU to CLA MSG 0x078000 accessible by
RAM (128x16) TI / User OTP DMA
(4Kx16)

0x080000
0x008000
FLASH
LS0 – LS7 RAM
(2Kx16 each) (128Kx16)

0x3F8000
Boot ROM (32Kx16)
0x3FFFC0
BROM Vectors (64x16)

There are two dedicated RAM block (M0 and M1) which are tightly coupled with the CPU, and
only the CPU has access to them. The PIE Vectors are a special memory area containing the
vectors for the peripheral interrupts. The eight local shared memory blocks, LS0 through LS7,
are accessible by the CPU and CLA. The four global shared memory blocks, GS0 through GS3,
are accessible by CPU and DMA.

There are two types of message RAM blocks: CLA message RAM blocks and CAN message
RAM blocks. The CLA message RAM blocks are used to share data between the CPU and CLA.
The CAN message RAM blocks contains message objects and parity bits for the message
objects (CAN message RAM can only be accessed in debug mode).

The user OTP is a one-time, programmable, memory block which contains device specific
calibration data for the ADC, internal oscillators, and buffered DACs, in addition to settings used

TMS320F28004x Microcontroller Workshop - Architecture Overview 1-9

Memory

by the flash state machine for erase and program operations. Additionally, it contains locations
for programming security settings, such as passwords for selectively securing memory blocks,
configuring the standalone boot process, as well as selecting the boot-mode pins in case the
factory-default pins cannot be used. This information is programmed into the dual code security
module (DCSM). The flash memory is primarily used to store program code, but can also be
used to store static data. The boot ROM and boot ROM vectors are located at the bottom of the
memory map.

Dual Code Security Module (DCSM)

Dual Code Security Module
 Prevents reverse engineering and protects valuable
intellectual property

Z1_CSMPSWD0 Z2_CSMPSWD0
Z1_CSMPSWD1 Z2_CSMPSWD1
Z1_CSMPSWD2 Z2_CSMPSWD2
Z1_CSMPSWD3 Z2_CSMPSWD3

 Various on-chip memory resources can be assigned to

either zone 1 or zone 2
 Each zone has its own password
 128-bit user defined password is stored in OTP
 128-bits = 2128 = 3.4 x 1038 possible passwords
 To try 1 password every 8 cycles at 100 MHz, it would take
at least 8.6 x 1023 years to try all possible combinations!

Peripherals
The F28004x is available with a variety of built in peripherals optimized to support control
applications. See the data sheet for specific availability.
• PGA • SCI
• ePWM
• Watchdog • I2C
• eCAP
• DMA • LIN
• eQEP
• CLA • CAN
• CMPSS
• SDFM • FSI
• ADC
• SPI • PMBUS
• DAC

1 - 10 TMS320F28004x Microcontroller Workshop - Architecture Overview

 Fast Interrupt Response Manager

Fast Interrupt Response Manager

The fast interrupt response manage is capable of automatically performing context save of critical
registers. This results in the ability of servicing many asynchronous events with minimal latency.
The F28004x implements a zero cycle penalty to do 14 registers context saved and restored
during an interrupt. This feature helps reduces the interrupt service routine overheads.

C28x Fast Interrupt Response Manager

 192 dedicated PIE
vectors
PIE module

Peripheral Interrupts 12x16 = 192

 No software decision For 192 28x CPU Interrupt logic
interrupts
making required
INT1 to
 Direct access to RAM INT12
vectors 192 12 interrupts
C28x
PIE IFR IER INTM CPU
 Auto flags update Register
 Concurrent auto Map

context save
Auto Context Save
T ST0
AH AL
PH PL
AR1 (L) AR0 (L)
DP ST1
DBSTAT IER
PC(msw) PC(lsw)

By incorporating the very fast interrupt response manager with the peripheral interrupt expansion
(PIE) block, it is possible to allow up to 192 interrupt vectors to be processed by the CPU. More
details about this will be covered in the reset, interrupts, and system initialization modules.

TMS320F28004x Microcontroller Workshop - Architecture Overview 1 - 11

Math Accelerators

Math Accelerators
Viterbi / Complex Math Unit (VCU-II)
Viterbi / Complex Math Unit (VCU)
Extends C28x instruction
set to support: VCU execution
registers
 Viterbi operations
VSTATUS
 Decode for communications
Data path logic for VCU-II
 Complex math VR0 Instruction
1. General instructions
 16-bit fixed-point complex FFT VR1
2. CRC instructions
 used in spread spectrum VR2
3. Arithmetic instructions
communications, and many signal VR3 4. Galois Field instructions
processing algorithms VSM0
VR4 to 5. Complex FFT instructions
 Complex filters VSM63
VR5
 used to improve data reliability,
transmission distance, and power VR6
efficiency
VR7
 Power Line Communications
(PLC) and radar applications VR8
VCU
 Cyclic Redundancy Check Control Logic
VT0
(CRC)
 Communications and memory VT1
robustness checks
VCRC
 Other: OFDM interleaving &
de-interleaving, Galois Field
arithmetic, AES acceleration

The Viterbi, Complex Math, and CRC Unit (VCU) adds an extended set of registers and
instructions to the standard C28x architecture for supporting various communications-based
algorithms, such as power line communications (PLC) standards PRIME and G3. These
algorithms typically require Viterbi decoding, complex Fast Fourier Transform (FFT), complex
filters, and cyclical redundancy check (CRC). By utilizing the VCU a significant performance
benefit is realized over a software implementation. It performs fixed-point operations using the
existing instruction set format, pipeline, and memory bus architecture. Additionally, the VCU is
very useful for general-purpose signal processing applications such as filtering and spectral
analysis.

1 - 12 TMS320F28004x Microcontroller Workshop - Architecture Overview

 Math Accelerators

Trigonometric Math Unit (TMU)

Trigonometric Math Unit (TMU)
Adds instructions to FPU for

y = r * sin(rad)
y
r
x
calculating common
Trigonometric operations
x = r * cos(rad)

Operation Instruction Exe Cycles Result Latency FPU Cycles w/o TMU
Z = Y/X DIVF32 Rz,Ry,Rx 1 5 ~24
Y = sqrt(X) SQRTF32 Ry,Rx 1 5 ~26
Y = sin(X/2pi) SINPUF32 Ry,Rx 1 4 ~33
Y = cos(X/2pi) COSPUF32 Ry,Rx 1 4 ~33
Y = atan(X)/2pi ATANPUF32 Ry,Rx 1 4 ~53
Instruction To QUADF32 Rw,Rz,Ry,Rx 3 11 ~90
Support ATAN2 ATANPUF32 Ra,Rz
Calculation ADDF32 Rb,Ra,Rw
Y = X * 2pi MPY2PIF32 Ry,Rx 1 2 ~4
Y = X * 1/2pi DIV2PIF32 Ry,Rx 1 2 ~4

 Supported by natural C and C-intrinsics

 Significant performance impact on algorithms such as:
• Park / Inverse Park • dq0 Transform & Inverse dq0
• Space Vector GEN • FFT Magnitude & Phase Calculations

The Trigonometric Math Unit (TMU) is an extension of the FPU and the C28x instruction set, and
it efficiently executes trigonometric and arithmetic operations commonly found in control system
applications. Similar to the FPU, the TMU provides hardware support for IEEE-754 single-
precision floating-point operations that are specifically focused on trigonometric math functions.
Seamless code integration is accomplished by built-in compiler support that automatically
generates TMU instructions where applicable. This dramatically increases the performance of
trigonometric functions, which would otherwise be very cycle intensive. It uses the same pipeline,
memory bus architecture, and FPU registers as the FPU, thereby removing any special
requirements for interrupt context save or restore.

TMS320F28004x Microcontroller Workshop - Architecture Overview 1 - 13

Configurable Logic Block (CLB)

Configurable Logic Block (CLB)

Configurable Logic Block (CLB)
 Collection of configurable
logic tiles CLB G L S
CLB1 Int
CPU I/F CELL
Tile1 CLB XTRIP
XTRIPx
XBAR XBAR XBAR1
XBAR1,3
L O y
 Can be interconnected O
B
C
A
s
t
A L e
using software to L
B
m

B U B
implement custom digital U
S
S u
s
CLB2 Int
logic functions L
O
CPU I/F CELL
Tile2

 Enhances existing A
L

ePWM,eQEP, & eCAP Peripherals

ePWM, eQEP, & eCAP Peripherals
peripherals through a set of B
U
S

crossbar interconnections CLB3 Int

L Tile3
CPU I/F CELL
 Crossbars allow the CLB to O
C
A

be connected to external L

GPIO pins U
S

CLB4 Int
 Each tile contains the core L
O
CPU I/F CELL
Tile4

reconfiguration logic C
A
L

 CPU interface can be used B

U
S

to exchange data with the

rest of the device

The Configurable Logic Block (CLB) is configured by software and it allows for the
implementation of custom digital logic functions. Enhancements to the existing peripherals are
enabled through a set of crossbar interconnections. This provides a high level of connectivity to
existing control peripherals such as the enhanced pulse width modulators (ePWM), the enhanced
capture modules (eCAP), and the enhanced quadrature encoder pulse modules (eQEP). The
crossbars also allow the CLB to be connected to external GPIO pins. Therefore, the CLB can be
configured to interact with device peripherals to perform small logical functions such as simple
PWM generators, or to implement custom serial data exchange protocols.

The CLB subsystem contains a number of identical tiles. There are four tiles in the F28004x CLB
subsystems. Each tile contains combinational and sequential logic blocks, as well as other
dedicated hardware. The figure above shows the structure of the CLB subsystem in the F28004x
device.

1 - 14 TMS320F28004x Microcontroller Workshop - Architecture Overview

 On-Chip Safety Features

On-Chip Safety Features

On-Chip Safety Features
 Memory Protection
 ECC and parity enabled RAMs, shared RAMs protection
 ECC enabled flash memory
 Clock Checks
 Missing clock detection logic
 PLLSLIP detection
 NMIWDs
 Windowed watchdog
 Write Register Protection
 LOCK protection on system configuration registers
 EALLOW protection
 PIE vector address validity check

 Annunciation
 Single error pin for external signalling of error

TMS320F28004x Microcontroller Workshop - Architecture Overview 1 - 15

Summary

Summary
Summary
 High performance 32-bit CPU
 32x32 bit or dual 16x16 bit MAC
 IEEE single-precision floating point unit (FPU)
 Hardware Control Law Accelerator (CLA)
 Viterbi, complex math, CRC unit (VCU)
 Trigonometric math unit (TMU)
 Atomic read-modify-write instructions
 Fast interrupt response manager
 128Kw on-chip flash memory
 Dual code security module (DCSM)
 Control peripherals
 Analog peripherals
 Direct memory access (DMA)
 Shared GPIO pins
 Communications peripherals

1 - 16 TMS320F28004x Microcontroller Workshop - Architecture Overview

 Programming Development Environment
Introduction
This module will explain how to use Code Composer Studio (CCS) integrated development
environment (IDE) tools to develop a program. Creating projects and setting building options will
be covered. Use and the purpose of the linker command file will be described.

Module Objectives
Module Objectives

 Use Code Composer Studio to:

 Create a Project
 Set Build Options

 Create a user linker command file which:

 Describes a system’s available memory
 Indicates where sections will be placed
in memory

TMS320F28004x Microcontroller Workshop - Programming Development Environment 2-1

Code Composer Studio

Chapter Topics
Programming Development Environment ................................................................................ 2-1
Code Composer Studio ............................................................................................................. 2-3
Software Development and COFF Concepts........................................................................ 2-3
Code Composer Studio ......................................................................................................... 2-4
Edit and Debug Perspective (CCSv9) ................................................................................... 2-5
Target Configuration ............................................................................................................. 2-6
CCSv9 Project ....................................................................................................................... 2-7
Creating a New CCSv9 Project ............................................................................................. 2-8
CCSv9 Build Options – Compiler / Linker ............................................................................. 2-9
CCS Debug Environment .................................................................................................... 2-10
Creating a Linker Command File ............................................................................................ 2-12
Sections............................................................................................................................... 2-12
Linker Command Files (.cmd) ............................................................................................ 2-15
Memory-Map Description .................................................................................................... 2-15
Section Placement .............................................................................................................. 2-16
Summary: Linker Command File ........................................................................................ 2-17
Lab 2: Linker Command File ................................................................................................... 2-18

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 Code Composer Studio

Code Composer Studio

Software Development and COFF Concepts
In an effort to standardize the software development process, TI uses the Common Object File
Format (COFF). COFF has several features which make it a powerful software development
system. It is most useful when the development task is split between several programmers.

Each file of code, called a module, may be written independently, including the specification of all
resources necessary for the proper operation of the module. Modules can be written using Code
Composer Studio (CCS) or any text editor capable of providing a simple ASCII file output. The
expected extension of a source file is .ASM for assembly and .C for C programs.

Code Composer Studio

Build Code
lnk.cmd Simulator
Compile

Development
Tool
Asm Link Debug

External
Editor Libraries Graphs, Emulator
Profiling
MCU
Board
 Code Composer Studio includes:
 Integrated
Edit/Debug GUI
 Code Generation Tools
 TI-RTOS

Code Composer Studio includes a built-in editor, compiler, assembler, linker, and an automatic
build process. Additionally, tools to connect file input and output, as well as built-in graph
displays for output are available. Other features can be added using the plug-ins capability

Numerous modules are joined to form a complete program by using the linker. The linker
efficiently allocates the resources available on the device to each module in the system. The
linker uses a command (.CMD) file to identify the memory resources and placement of where the
various sections within each module are to go. Outputs of the linking process includes the linked
object file (.OUT), which runs on the device, and can include a .MAP file which identifies where
each linked section is located.

The high level of modularity and portability resulting from this system simplifies the processes of
verification, debug and maintenance. The process of COFF development is presented in greater
detail in the following paragraphs.

The concept of COFF tools is to allow modular development of software independent of hardware
concerns. An individual assembly language file is written to perform a single task and may be
linked with several other tasks to achieve a more complex total system.

TMS320F28004x Microcontroller Workshop - Programming Development Environment 2-3

Code Composer Studio

Writing code in modular form permits code to be developed by several people working in parallel
so the development cycle is shortened. Debugging and upgrading code is faster, since
components of the system, rather than the entire system, is being operated upon. Also, new
systems may be developed more rapidly if previously developed modules can be used in them.

Code developed independently of hardware concerns increases the benefits of modularity by

allowing the programmer to focus on the code and not waste time managing memory and moving
code as other code components grow or shrink. A linker is invoked to allocate systems hardware
to the modules desired to build a system. Changes in any or all modules, when re-linked, create
a new hardware allocation, avoiding the possibility of memory resource conflicts.

Code Composer Studio

Code Composer Studio: IDE

 Integrates: edit, code generation,

and debug

 Single-click access using buttons

 Powerful graphing/profiling tools

 Automated tasks using Scripts

 Built-in access to RTOS functions

 Based on the Eclipse open source
software framework

Code Composer Studio™ (CCS) is an integrated development environment (IDE) for Texas
Instruments (TI) embedded processor families. CCS comprises a suite of tools used to develop
and debug embedded applications. It includes compilers for each of TI's device families, source
code editor, project build environment, debugger, profiler, simulators, real-time operating system
and many other features. The intuitive IDE provides a single user interface taking you through
each step of the application development flow. Familiar tools and interfaces allow users to get
started faster than ever before and add functionality to their application thanks to sophisticated
productivity tools.

CCS is based on the Eclipse open source software framework. The Eclipse software framework
was originally developed as an open framework for creating development tools. Eclipse offers an
excellent software framework for building software development environments and it is becoming
a standard framework used by many embedded software vendors. CCS combines the
advantages of the Eclipse software framework with advanced embedded debug capabilities from
TI resulting in a compelling feature-rich development environment for embedded developers.
CCS supports running on both Windows and Linux PCs. Note that not all features or devices are
supported on Linux.

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 Code Composer Studio

Edit and Debug Perspective (CCSv9)

A perspective defines the initial layout views of the workbench windows, toolbars, and menus that
are appropriate for a specific type of task, such as code development or debugging. This
minimizes clutter to the user interface.

Edit and Debug Perspective (CCSv9)

 Each perspective provides a set of functionality aimed
at accomplishing a specific task

 Edit Perspective  Debug Perspective

 Displays views used  Displays views used for
during code development debugging
 C/C++ project, editor, etc.  Menus and toolbars
associated with debugging,
watch and memory
windows, graphs, etc.

Code Composer Studio has “Edit” and “Debug” perspectives. Each perspective provides a set of
functionality aimed at accomplishing a specific task. In the edit perspective, views used during
code development are displayed. In the debug perspective, views used during debug are
displayed.

TMS320F28004x Microcontroller Workshop - Programming Development Environment 2-5

Code Composer Studio

Target Configuration
A Target Configuration defines how CCS connects to the device. It describes the device using
GEL files and device configuration files. The configuration files are XML files and have a
*.ccxml file extension.

Creating a Target Configuration

 File  New  Target

Configuration File

 Select connection type

 Select device
 Save configuration

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 Code Composer Studio

CCSv9 Project
Code Composer works with a project paradigm. Essentially, within CCS you create a project for
each executable program you wish to create. Projects store all the information required to build
the executable. For example, it lists things like: the source files, the header files, the target
system’s memory-map, and program build options.

CCSv9 Project

Project files contain:

 List of files:
 Source (C, assembly)
 Libraries
 Linker command files
 TI-RTOS configuration file
 Project settings:
 Build options (compiler,
assembler, linker, and TI-RTOS)
 Build configurations

A project contains files, such as C and assembly source files, libraries, BIOS configuration files,
and linker command files. It also contains project settings, such as build options, which include
the compiler, assembler, linker, and TI-RTOS, as well as build configurations.

To create a new project, you need to select the following menu items:

File  New  CCS Project

Along with the main Project menu, you can also manage open projects using the right-click popup
menu. Either of these menus allows you to modify a project, such as add files to a project, or
open the properties of a project to set the build options.

TMS320F28004x Microcontroller Workshop - Programming Development Environment 2-7

Code Composer Studio

Creating a New CCSv9 Project

A graphical user interface (GUI) is used to assist in creating a new project. The GUI is shown in
the slide below.

Creating a New CCSv9 Project

1. Project Name, Location, and Device

 File  New  CCS Project

2. Tool-chain

3. Project templates and examples

After a project is created, the build options are configured.

2-8 TMS320F28004x Microcontroller Workshop - Programming Development Environment

 Code Composer Studio

CCSv9 Build Options – Compiler / Linker

Project options direct the code generation tools (i.e. compiler, assembler, linker) to create code
according to your system’s needs. When you create a new project, CCS creates two sets of build
options – called Configurations: one called Debug, the other Release (you might think of as
optimize).

To make it easier to choose build options, CCS provides a graphical user interface (GUI) for the
various compiler and linker options. Here’s a sample of the configuration options.

CCSv9 Build Options – Compiler / Linker

 Compiler  Linker
 22 categories for code  9 categories for linking
generation tools  Specify various link
 Controls many aspects of options
the build process, such as:  ${PROJECT_ROOT}
 Optimization level specifies the current
 Target device
project directory
 Compiler / assembly / link
options

There is a one-to-one relationship between the items in the text box on the main page and the
GUI check and drop-down box selections. Once you have mastered the various options, you can
probably find yourself just typing in the options.

There are many linker options but these four handle all of the basic needs.
• -o <filename> specifies the output (executable) filename.
• -m <filename> creates a map file. This file reports the linker’s results.
• -c tells the compiler to autoinitialize your global and static variables.
• -x tells the compiler to exhaustively read the libraries. Without this option libraries are
searched only once, and therefore backwards references may not be resolved.

To help make sense of the many compiler options, TI provides two default sets of options
(configurations) in each new project you create. The Release (optimized) configuration invokes
the optimizer with –o3 and disables source-level, symbolic debugging by omitting –g (which
disables some optimizations to enable debug).

TMS320F28004x Microcontroller Workshop - Programming Development Environment 2-9

Code Composer Studio

CCS Debug Environment

The basic buttons that control the debug environment are located in the top of CCS:

The common debugging and program execution descriptions are shown below:

Start debugging

Image Name Description Availability

New Target Creates a new target configartion file. File New Menu
Configuration Target Menu

Debug Opens a dialog to modify existing debug configura-

Debug Toolbar
tions. Its drop down can be used to access other
Target Menu
launching options.

Connect Connect to hardware targets. TI Debug Toolbar

Target Target Menu
Debug View Context Menu

Terminate All Terminates all active debug sessions. Target Menu

Debug View Toolbar

2 - 10 TMS320F28004x Microcontroller Workshop - Programming Development Environment

 Code Composer Studio

Program execution

Image Name Description Availability

Halt Halts the selected target. The rest of the debug

Target Menu
views will update automatically with most recent
Debug View Toolbar
target data.

Run Resumes the execution of the currently loaded

Target Menu
program from the current PC location. Execution
Debug View Toolbar
continues until a breakpoint is encountered.

Run to Line Resumes the execution of the currently loaded

Target Menu
program from the current PC location. Execution
Disassembly Context Menu
continues until the specific source/assembly line is
Source Editor Context Menu
reached.

Go to Main Runs the programs until the beginning of function

Debug View Toolbar
main in reached.

Step Into Steps into the highlighted statement. Target Menu

Debug View Toolbar

Step Over Steps over the highlighted statement. Execution

will continue at the next line either in the same
method or (if you are at the end of a method) it Target Menu
will continue in the method from which the current Debug View Toolbar
method was called. The cursor jumps to the decla-
ration of the method and selects this line.

Step Return Steps out of the current method. Target Menu

Debug View Toolbar

Reset Resets the selected target. The drop-down menu

Target Menu
has various advanced reset options, depending on
Debug View Toolbar
the selected device.

Restart Restores the PC to the entry point for the currently

loaded program. If the debugger option "Run to
Target Menu
main on target load or restart" is set the target will
Debug View Toolbar
run to the specified symbol, otherwise the execu-
tion state of the target is not changed.

Assembly The debugger executes the next assembly instruc- TI Explicit Stepping Toolbar
Step Into tion, whether source is available or not. Target Advanced Menu

Assembly The debugger steps over a single assembly instruc-

Step Over tion. If the instruction is an assembly subroutine, TI Explicit Stepping Toolbar
the debugger executes the assembly subroutine Target Advanced Menu
and then halts after the assembly function returns.

TMS320F28004x Microcontroller Workshop - Programming Development Environment 2 - 11

Creating a Linker Command File

Creating a Linker Command File

Sections
Looking at a C program, you'll notice it contains both code and different kinds of data (global,
local, etc.). All code consists of different parts called sections. All default section names begin
with a dot and are typically lower case. The compiler has default section names for initialized and
uninitialized sections. For example, x and y are global variables, and they are placed in the
section .ebss. Whereas 2 and 7 are initialized values, and they are placed in the section called
.cinit. The local variables are in a section .stack, and the code is placed in a section called .txt.

Sections
Global vars (.ebss) Init values (.cinit)

 All code consists of

int x = 2; different parts called
int y = 7; sections
 All default section
names begin with “.”
void main(void)
 The compiler has
{ default section names
long z; for initialized and
uninitialized sections
z = x + y;
}

Local vars (.stack) Code (.text)

In the TI code-generation tools (as with any toolset based on the COFF – Common Object File
Format), these various parts of a program are called Sections. Breaking the program code and
data into various sections provides flexibility since it allows you to place code sections in ROM
and variables in RAM. The preceding diagram illustrated four sections:
• Global Variables
• Initial Values for global variables
• Local Variables (i.e. the stack)
• Code (the actual instructions)

2 - 12 TMS320F28004x Microcontroller Workshop - Programming Development Environment

 Creating a Linker Command File

The following is a list of the sections that are created by the compiler. Along with their
description, we provide the Section Name defined by the compiler. This is a small list of compiler
default section names. The top group is initialized sections, and they are linked to flash. In our
previous code example, we saw .txt was used for code, and .cinit for initialized values. The
bottom group is uninitialized sections, and they are linked to RAM. Once again, in our previous
example, we saw .ebss used for global variables and .stack for local variables.

Compiler Section Names

Initialized Sections
Name Description Link Location
.text code FLASH
.cinit initialization values for FLASH
global and static variables
.econst constants (e.g. const int k = 3;) FLASH
.switch tables for switch statements FLASH
.pinit tables for global constructors (C++) FLASH

Uninitialized Sections
Name Description Link Location
.ebss global and static variables RAM
.stack stack space low 64Kw RAM
.esysmem memory for far malloc functions RAM

Note: During development initialized sections could be linked to RAM since

the emulator can be used to load the RAM

Sections of a C program must be located in different memories in your target system. This is the
big advantage of creating the separate sections for code, constants, and variables. In this way,
they can all be linked (located) into their proper memory locations in your target embedded
system. Generally, they’re located as follows:

Program Code (.text)

Program code consists of the sequence of instructions used to manipulate data, initialize system
settings, etc. Program code must be defined upon system reset (power turn-on). Due to this basic
system constraint it is usually necessary to place program code into non-volatile memory, such as
FLASH or EPROM.

Constants (.cinit – initialized data)

Initialized data are those data memory locations defined at reset.It contains constants or initial
values for variables. Similar to program code, constant data is expected to be valid upon reset of
the system. It is often found in FLASH or EPROM (non-volatile memory).

Variables (.ebss – uninitialized data)

Uninitialized data memory locations can be changed and manipulated by the program code
during runtime execution. Unlike program code or constants, uninitialized data or variables must
reside in volatile memory, such as RAM. These memories can be modified and updated,
supporting the way variables are used in math formulas, high-level languages, etc. Each variable

TMS320F28004x Microcontroller Workshop - Programming Development Environment 2 - 13

Creating a Linker Command File

must be declared with a directive to reserve memory to contain its value. By their nature, no value
is assigned, instead they are loaded at runtime by the program.

Next, we need to place the sections that were created by the compiler into the appropriate
memory spaces. The uninitialized sections, .ebss and .stack, need to be placed into RAM; while
the initialized sections, .cinit, and .txt, need to be placed into flash.

Placing Sections in Memory

Memory
Sections
0x00 0000 RAMM0
(0x400)
.ebss
0x00 0400 RAMM1
(0x400)
.stack

0x08 0000 FLASH .cinit

(0x40000)

.text

Linking code is a three step process:

1. Defining the various regions of memory (on-chip RAM vs. FLASH vs. External Memory).
2. Describing what sections go into which memory regions
3. Running the linker with “build” or “rebuild”

2 - 14 TMS320F28004x Microcontroller Workshop - Programming Development Environment

 Creating a Linker Command File

Linker Command Files (.cmd)

The linker concatenates each section from all input files, allocating memory to each section
based on its length and location as specified by the MEMORY and SECTIONS commands in the
linker command file. The linker command file describes the physical hardware memory and
specifies where the sections are placed in the memory. The file created during the link process is
a .out file. This is the file that will be loaded into the microcontroller. As an option, we can
generate a map file. This map file will provide a summary of the link process, such as the
absolute address and size of each section.

Linking

 Memory description
 How to place s/w into h/w

Link.cmd

.obj Linker .out

.map

Memory-Map Description
The MEMORY section describes the memory configuration of the target system to the linker.
The format is: Name: origin = 0x????, length = 0x????
For example, if you placed a 256Kw FLASH starting at memory location 0x080000, it would read:

MEMORY
{
FLASH: origin = 0x080000 , length = 0x040000
}

Each memory segment is defined using the above format. If you added RAMM0 and RAMM1, it
would look like:

MEMORY
{
RAMM0: origin = 0x000000 , length = 0x0400
RAMM1: origin = 0x000400 , length = 0x0400

TMS320F28004x Microcontroller Workshop - Programming Development Environment 2 - 15

Creating a Linker Command File

Remember that the MCU has two memory maps: Program, and Data. Therefore, the MEMORY
description must describe each of these separately. The loader uses the following syntax to
delineate each of these:

Linker Page TI Definition

Page 0 Program
Page 1 Data

Linker Command File

MEMORY
{
PAGE 0: /* Program Memory */
FLASH: origin = 0x080000, length = 0x40000

PAGE 1: /* Data Memory */

RAMM0: origin = 0x000000, length = 0x400
RAMM1: origin = 0x000400, length = 0x400
}
SECTIONS
{
.text:> FLASH PAGE = 0
.ebss:> RAMM0 PAGE = 1
.cinit:> FLASH PAGE = 0
.stack:> RAMM1 PAGE = 1
}

A linker command file consists of two sections, a memory section and a sections section. In the
memory section, page 0 defines the program memory space, and page 1 defines the data
memory space. Each memory block is given a unique name, along with its origin and length. In
the sections section, the section is directed to the appropriate memory block.

Section Placement
The SECTIONS section will specify how you want the sections to be distributed through memory.
The following code is used to link the sections into the memory specified in the previous example:

SECTIONS
{
.text:> FLASH PAGE 0
.ebss:> RAMM0 PAGE 1
.cinit:> FLASH PAGE 0
.stack:> RAMM1 PAGE 1
}

2 - 16 TMS320F28004x Microcontroller Workshop - Programming Development Environment

 Creating a Linker Command File

The linker will gather all the code sections from all the files being linked together. Similarly, it will
combine all ‘like’ sections.

Beginning with the first section listed, the linker will place it into the specified memory segment.

Summary: Linker Command File

The linker command file (.cmd) contains the inputs — commands — for the linker. This
information is summarized below:

Linker Command File Summary

 Memory Map Description

 Name
 Location
 Size
 Sections Description
 Directssoftware sections into named
memory regions
 Allows per-file discrimination
 Allows separate load/run locations

TMS320F28004x Microcontroller Workshop - Programming Development Environment 2 - 17

Lab 2: Linker Command File

Lab 2: Linker Command File

 Objective
Use a linker command file to link the C program file (Lab2.c) into the system described below.

Lab 2: Linker Command File

Memory

on-chip
memory

F28004x

System Description:
• TMS320F28004x
• All internal RAM
blocks allocated

Placement of Sections:
• .text into RAM Block RAMGS01 on PAGE 0 (program memory)
• .cinit into RAM Block RAMGS01 on PAGE 0 (program memory)
• .ebss into RAM Block RAMM0 on PAGE 1 (data memory)
• .stack into RAM Block RAMM1 on PAGE 1 (data memory)

 Initial Hardware Set Up

Note: The lab exercises in this workshop have been developed and targeted for the F280049C
LaunchPad. Optionally, the F280049C Experimenter Kit can be used. Refer to Appendix
A for additional information on using the F280049C Experimenter Kit with this workshop.

• F280049C LaunchPad:

Using the supplied USB cable – plug the USB Standard Type A connector into the computer USB
port and the USB Micro Type B connector into the LaunchPad. This will power the LaunchPad
using the power supplied by the computer USB port. Additionally, this USB port will provide the
JTAG communication link between the device and Code Composer Studio.

 Initial Software Set Up

Code Composer Studio must be installed in addition to the workshop files. A local copy of the
required C2000Ware files is included with the lab files. This provides portability, making the
workshop files self-contained and independent of other support files or resources. The lab
directions for this workshop are based on all software installed in their default locations.

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 Lab 2: Linker Command File

 Procedure

Start Code Composer Studio and Open a Workspace

1. Start Code Composer Studio (CCS) by double clicking the icon on the desktop or selecting it
from the Windows Start menu. When CCS loads, a dialog box will prompt you for the
location of a workspace folder. Use the default location for the workspace and click Launch.

This folder contains all CCS custom settings, which includes project settings and views when
CCS is closed so that the same projects and settings will be available when CCS is opened
again. The workspace is saved automatically when CCS is closed.
2. The first time CCS opens an introduction page appears. Close the page by clicking the X on
the “Getting Started” tab. You should now have an empty workbench. The term “workbench”
refers to the desktop development environment. Maximize CCS to fill your screen.

The workbench will open in the CCS Edit perspective view. Notice the “CCS Edit” icon in the
upper right-hand corner. A perspective defines the initial layout views of the workbench
windows, toolbars, and menus which are appropriate for a specific type of task (i.e. code
development or debugging). This minimizes clutter to the user interface. The CCS Edit
perspective is used to create or build C/C++ projects. A CCS Debug perspective view will
automatically be enabled when the debug session is started. This perspective is used for
debugging C/C++ projects.

Setup Target Configuration

3. Open the target configuration dialog box. On the menu bar click:

File  New  Target Configuration File

In the file name field type F28004x.ccxml. This is just a descriptive name since multiple
target configuration files can be created. Leave the “Use shared location” box checked and
select Finish.
4. In the next window that appears, select the emulator using the “Connection” pull-down list
and choose “Texas Instruments XDS110 USB Debug Probe”. In the “Board or Device” box
type TMS320F280049C to filter the options. In the box below, check the box to select
“TMS320F280049C”.

The LaunchPad XDS110 USB Debug Probe is only wired to support 2-pin cJTAG mode.
Under Advanced Setup click “Target Configuration” and highlight “Texas Instruments
XDS110 USB Debug Probe_0”. Under Connection Properties set the JTAG/SWD/cJTAG
Mode to “cJTAG (1149.7) 2-pin advanced modes”.
Click Save to save the configuration, then close the “F28004x.ccxml” setup window by
clicking the X on the tab.
5. To view the target configurations, click:

View  Target Configurations

and click the sign (‘+’ or ‘>’) to the left of “User Defined”. Notice that the F28004x.ccxml file is
listed and set as the default. If it is not set as the default, right-click on the .ccxml file and
select “Set as Default”. Close the Target Configurations window by clicking the X on the tab.

Create a New Project

6. A project contains all the files you will need to develop an executable output file (.out) which
can be run on the MCU hardware. To create a new project click:

TMS320F28004x Microcontroller Workshop - Programming Development Environment 2 - 19

Lab 2: Linker Command File

File  New  CCS Project or click: Project  New CCS Project…

A CCS Project window will open. At the top of this window, filter the “Target” options by using
the pull-down list on the left and choose “28004x Piccolo”. In the pull-down list immediately
to the right, choose the “TMS320F280049C”.

Leave the “Connection” box blank. We have already set up the target configuration.
7. The next section selects the project settings. In the Project name field type Lab2. Uncheck
the “Use default location” box. Click the Browse… button and navigate to:
C:\F28004x\Labs\Lab2\project

Click Select Folder.

8. Next, open the “Tool-chain” section and set the “Linker command file” to “<none>”. We will
be using our own linker command file rather than the one supplied by CCS. Leave the
“Runtime Support Library” set to “<automatic>”. This will automatically select the
“rts2800_fpu32.lib” runtime support library for floating-point devices.
9. Then, open the “Project templates and examples” section and select the “Empty Project”
template. Click Finish.
10. A new project has now been created. Notice the Project Explorer window contains Lab2. If
the workbench is empty, reset the perspective view by clicking:
Window  Perspective  Reset Perspective…
The project is set “Active” and the output files will be located in the “Debug” folder. At this
point, the project does not include any source files. The next step is to add the source files to
the project.
11. To add the source files to the project, right-click on Lab2 in the Project Explorer window and
select:
Add Files…

or click: Project  Add Files…

and make sure you are looking in C:\F28004x\Labs\Lab2\source. With the “files of
type” set to view all files (*.*) select Lab2.c and Lab2.cmd then click OPEN. A “File
Operation” window will open, choose “Copy files” and click OK. This will add the files to the
project.
12. In the Project Explorer window, click the sign (‘+’ or ‘>’) to the left of Lab2 and notice that the
files are listed.

Project Build Options

13. There are numerous build options in the project. Most default option settings are sufficient for
getting started. We will inspect a couple of the default options at this time. Right-click on
Lab2 in the Project Explorer window and select Properties or click:

Project  Properties
14. A “Properties” window will open and in the section on the left under “Build” be sure that the
“C2000 Compiler” and “C2000 Linker” options are visible. Next, under “C2000 Linker” select
the “Basic Options”. Notice that .out and .map files are being specified. The .out file is
the executable code that will be loaded into the MCU. The .map file will contain a linker
report showing memory usage and section addresses in memory. Also notice the stack size
is set to 0x200.

2 - 20 TMS320F28004x Microcontroller Workshop - Programming Development Environment

 Lab 2: Linker Command File

15. Under “C2000 Compiler” select the “Processor Options”. Notice the large memory model
and unified memory boxes are checked. Next, notice the “Specify CLA support” is set to
cla2, the “Specify floating point support” is set to fpu32, the “Specify TMU support” is set to
TMU0, and the “Specify VCU support” is set to vcu0. Select Apply and Close to close the
Properties window.

Linker Command File – Lab2.cmd

16. Open and inspect Lab2.cmd by double clicking on the filename in the Project Explorer
window. Notice that the Memory{} declaration describes the system memory shown on the
“Lab2: Linker Command File” slide in the objective section of this lab exercise. Memory
blocks RAMLS4, RAMLS5 and RAMGS01 have been placed in program memory on page 0,
and the other memory blocks have been placed in data memory on page 1.
17. In the Sections{} area notice that the sections defined on the slide have been “linked” into
the appropriate memories. Also, notice that a section called .reset has been allocated. The
.reset section is part of the rts2800_fpu32.lib and is not needed. By putting the TYPE =
DSECT modifier after its allocation the linker will ignore this section and not allocate it. Close
the inspected file.

Build and Load the Project

18. Two buttons on the horizontal toolbar control code generation. Hover your mouse over each
button as you read the following descriptions:

Button Name Description_____________________________________

1 Build Full build and link of all source files

2 Debug Automatically build, link, load and launch debug-session

19. Click the “Build” button and watch the tools run in the Console window. Check for errors in
the Problems window (we have deliberately put an error in Lab2.c). When you get an error,
you will see the error message in the Problems window. Expand the error by clicking on the
sign (‘+’ or ‘>’) to the left of the “Errors”. Then simply double-click the error message. The
editor will automatically open to the source file containing the error, with the code line
highlighted with a red circle with a white “x” inside of it.
20. Fix the error by adding a semicolon at the end of the “z = x + y” statement. For future
knowledge, realize that a single code error can sometimes generate multiple error messages
at build time. This was not the case here.
21. Build the project again. There should be no errors this time.
22. CCS can automatically save modified source files, build the program, open the debug
perspective view, connect and download it to the target, and then run the program to the
beginning of the main function.

Click on the “Debug” button (green bug) or click RUN  Debug

Notice the “CCS Debug” icon in the upper right-hand corner indicating that we are now in the
CCS Debug perspective view. The program ran through the C-environment initialization
routine in the rts2800_fpu32.lib and stopped at main() in Lab2.c.

TMS320F28004x Microcontroller Workshop - Programming Development Environment 2 - 21

Lab 2: Linker Command File

Debug Environment Windows

It is standard debug practice to watch local and global variables while debugging code. There are
various methods for doing this in CCS. We will examine two of them here: memory browser, and
expressions.
23. Open a “Memory Browser” to view the global variable “z”.

Click: View  Memory Browser on the menu bar.

Type &z into the address field, select “Data” memory page, and then <enter>. Note that you
must use the ampersand (meaning “address of”) when using a symbol in a memory browser
address box. Also note that CCS is case sensitive.

Set the properties format to “16-Bit Hex – TI Style” in the browser. This will give you more
viewable data in the browser. You can change the contents of any address in the memory
browser by double-clicking on its value. This is useful during debug.
24. Notice the “Variables” window automatically opened and the local variables x and y are
present. The variables window will always contain the local variables for the code function
currently being executed.

(Note that local variables actually live on the stack. You can also view local variables in a
memory browser by setting the address to “SP” after the code function has been entered).
25. We can also add global variables to the “Expressions” window if desired. Let's add the global
variable “z”.

Click the “Expressions” tab at the top of the window. In the empty box in the “Expression”
column (Add new expression), type z and then <enter>. An ampersand is not used here.
The expressions window knows you are specifying a symbol. (Note that the expressions
window can be manually opened by clicking: View  Expressions on the menu bar).

Check that the expressions window and memory browser both report the same value for “z”.
Try changing the value in one window, and notice that the value also changes in the other
window.

Single-stepping the Code

26. Click the “Variables” tab at the top of the window to watch the local variables. Single-step
through main() by using the <F5> key (or you can use the “Step Into” button on the
horizontal toolbar). Check to see if the program is working as expected. What is the value
for “z” when you get to the end of the program?

Terminate Debug Session and Close Project

27. The “Terminate” button will terminate the active debug session, close the debugger and
return Code Composer Studio to the CCS Edit perspective view.

Click: Run  Terminate or use the Terminate icon:

28. Next, close the project by right-clicking on Lab2 in the Project Explorer window and select
Close Project.

End of Exercise

2 - 22 TMS320F28004x Microcontroller Workshop - Programming Development Environment

 Peripherial Register Programming
Introduction
This module starts with exploring different types of programming models; which include the
traditional #define macro approach, the bit field structure header files approach, and the driver
library approach. In this workshop, the C2000 Peripheral Driver Library, or Driverlib, will be used.
Driverlib is a set of low-level drivers for configuring memory-mapped peripheral registers. The
Driverlib provides a more readable and portable approach to peripheral register programming
than the other programming model methods.

The Driverlib is written in C and all source code can be found within C2000Ware. It provides
drivers for all peripherals, as well as drivers for configuring various memory mapped device
settings. In this module, you will learn how to use the Driverlib to facilitate programming the
peripherals and the device.

Module Objectives
Module Objectives

 Review register programming model

 Understand the usage of the F28004x
Driverlib and associated files
 Program an application using Driverlib
 Discuss Driverlib optimization

TMS320F28004x Microcontroller Workshop - Peripherial Register Programming 3-1

Register Programming Model

Chapter Topics
Peripherial Register Programming ............................................................................................ 3-1
Register Programming Model ................................................................................................... 3-3
Driver Library (Driverlib) ............................................................................................................ 3-5
Construction of a Driverlib Function ...................................................................................... 3-6
Driverlib Optimization ............................................................................................................ 3-7
Driverlib API Functions and Examples .................................................................................. 3-8
Content Assist ....................................................................................................................... 3-9
Driverlib Documentation ........................................................................................................ 3-9
Driverlib Summary............................................................................................................... 3-10
Lab File Directory Structure ................................................................................................ 3-10

3-2 TMS320F28004x Microcontroller Workshop - Peripherial Register Programming

 Register Programming Model

Register Programming Model

Register Programming Model
 Driverlib
Software  C functions automatically set
register bit fields
 Common tasks and
Driverlib peripheral modes supported
 Reduces learning curve and
Hardware Abstraction

simplifies programming
Bit Fields  Bit Field Header Files
 C structures – Peripheral
Register Header Files
Direct  Register access whole or by
bits and bit fields are
manipulated without masking
Registers and Addresses  Ease-of-use with CCS IDE
 Direct
 User code (C or assembly)
Hardware defines and access register
addresses

The various levels of the programming model provide different degrees of abstraction. The
highest level is DriverLib which are C functions that automatically set the bit fields. This gives you
a minimum amount of flexibility in exchange for a reduced learning curve and simplified
programming. The bit field header files are C structures that allow registers to be access whole
or by bits and bit fields, and modified without masking. This provides a balance between ease of
use and flexibility when working with Code Composer Studio. Direct access to the registers is the
lowest level where the user code, in C or assembly, defines and access register addresses.

TMS320F28004x Microcontroller Workshop - Peripherial Register Programming 3-3

Register Programming Model

Programming Model Comparison

 Register addresses # defined individually
Direct  User must compute bit-field masks
 Not easy-to-read

*CMPR1 = 0x1234;

 Header files define all registers as structures

Bit Field Header Files  Bit-fields directly accessible
 Easy-to-read

EPwm1Regs.CMPA.bit.CMPA = EPwm1Regs.TBPRD * duty;

 Driverlib performs low-level register manipulation

Driverlib  Easy-to-read
 Highest abstraction level

EPWM_setCounterCompareValue(EPWM1_BASE, EPWM_COUNTER_COMPARE_A, duty);

 The device support package includes documentation and examples showing how to
use the Bit Field Header Files or Driverlib
 Device support packages located at: C:\ti\c2000\C2000Ware\device_support\
C:\ti\c2000\C2000Ware\driverlib\
 C2000Ware can be downloaded at www.ti.com/tool/c2000ware

The above slide provides a comparison of each programming model, from the lowest level to the
highest level of abstraction. With direct access to the registers, the register addresses are
#defined individually and the user must compute the bit-field mask. The bit field header files
define all registers as structures and the bit fields are directly accessible. DriverLib performs low-
level register manipulation and provides the highest level of abstraction. This workshop makes
use of the Driverlib, which provides flexibility and makes it easy to program the device. Device
support packages can be downloaded from www.ti.com.

3-4 TMS320F28004x Microcontroller Workshop - Peripherial Register Programming

 Driver Library (Driverlib)

Driver Library (Driverlib)

Driver Library (Driverlib)
 Driverlib “APIs” provide many advantages and benefits:
 Require less detailed knowledge of the hardware
 Produce code that is easy-to-write and easy-to-read
 Generally require less development time
 Provide portability across other C2000 devices
 Optimize well; remove overhead and speed up code execution

 If needed, “direct register access” can be used to create

custom Driverlib functions
 Requires detailed knowledge of:
 Operation of each register and bit field
 Interactions and sequencing required for proper peripheral operation
 Can result in smaller and more efficient code

 Both APIs and direct register access can be used

independently or combined

The Driver Library (Driverlib) is a set of drivers for accessing the peripherals and device
configuration registers. While Driverlib is not drivers in the pure operating system sense (does
not a common interface and does not connect into a global device driver), they do provide a
software layer to facilitate a slightly higher level of programming.

Driverlib File Structure

Software driver (Driverlib API)
 Contains source code for drivers
 .c files and .h files
Direct register access
 Contains peripheral, interrupt, and register
access header files
 hw_*.h
 One per peripheral / memmap device function
 Defines all registers and bit fields within the registers
for each peripheral
 Used by driver API to access a peripheral
 Can be used to bypass driverlib API
 hw_memmap.h
 Defines base address for each peripheral
 hw_ints.h
 Defines interrupt numbers (used with interrupt.c)
 hw_types.h
 Defines type definitions

TMS320F28004x Microcontroller Workshop - Peripherial Register Programming 3-5

Driver Library (Driverlib)

Construction of a Driverlib Function

Construction of a Driverlib Function
 Driverlib API functions are built on top of the direct
register access model
 Useful to understand for debugging or when needing to directly
access a register or bit field
 Uses a similar traditional #define approach
 Naming convention used in header files macros:
• Values that end in _BASE are module instance base addresses
• Values that contain an _O_ are register address offsets
• Values that end in _M are mask for multi-bit field register
• Values that end in _S are the number of bits to shift
hw_types.h contains the follow macros:
• HWREG(x) are 32-bit accesses
• HWREGH(x) are 16-bit accesses (or upper/lower 32-bit word)
• HWREGB(x) are 8-bit accesses
• HWREGBP(x) are used with byte peripherals
where x is the address to be accessed

With the direct register access model, the peripherals are programmed by writing values directly
to the peripheral’s registers. A set of macros is provided to simplify this process. These macros
are stored in several header files contained in the \inc directory.

Driverlib Function Example

user.c – user source file
// Configure EPWM clock prescaler to TBCLK = EPWMCLK
EPWM_setClockPrescaler(EPWM2_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);

epwm.h
hw_memmap.h
Contains typedef enum values for:
#define EPWM2_BASE 0x00004100U // EPWM2
EPWM_CLOCK_DIVIDER (_1 = 0)
EPWM_HSCLOCK_DIVIDER (_1 = 0)

epwm.h – EPWM Driver

static inline void EPWM_setClockPrescaler(uint32_t base,
EPWM_ClockDivider prescaler,
EPWM_HSClockDivider highSpeedPrescaler)
{
ASSERT(EPWM_isBaseValid(base));

// write to CLKDIV and HSPCLKDIV bit

HWREGH(base + EPWM_O_TBCTL) =
((HWREGH(base + EPWM_O_TBCTL) &
~(EPWM_TBCTL_CLKDIV_M | EPWM_TBCTL_HSPCLKDIV_M))|
(((uint16_t)prescaler << EPWM_TBCTL_CLKDIV_S) |
((uint16_t)highSpeedPrescaler << EPWM_TBCTL_HSPCLKDIV_S)));
}

hw_epwm.h
Contains #define for all:
EPWM_xxx values in epwm.h
Note: CCS ‘F3’ will open declaration

3-6 TMS320F28004x Microcontroller Workshop - Peripherial Register Programming

 Driver Library (Driverlib)

Driverlib Optimization
Driverlib Optimization
 In general, software abstraction can come at the cost of performance
 However, Driverlib’s low-level abstraction and optimization-conscious
design makes it efficient

 Most functions have been declared as inline functions

 Allows the compiler to treat functions like macros when optimizer is turned on
 Removes the overhead of function calls and speeds up code execution

 Use compiler option --opt_level set to 0 or higher

The optimization options are selected in the CCS project by right-clicking on the project in the
project explorer window and then clicking ‘Properties’. In the properties window, the optimization
settings are located under: Build  C2000 Compiler  Optimization

Optimization Example
 Read ADC conversion results
 Optimization level of -O2
 Single MOV instruction is generated for each function call

 When compiled with:

 Optimization level of -O2
 Turn off inlining (--disable_inlining)
 Results:
 22 words of code
 4 words for ADC_readResult() and 18 words for the calling functions
 53 cycles to execute

TMS320F28004x Microcontroller Workshop - Peripherial Register Programming 3-7

Driver Library (Driverlib)

Driverlib API Functions and Examples

Driverlib API Functions

ADC DMA Interrupt

ASysCtl ECAP LIN
CAN EPWM MemCfg
CLA EQEP PGA
CLAPROMCRC Flash PMBus
CMPSS FSI SCI
CPU Timer GPIO SDFM
DAC HRCAP SPI
DCC HRPWM SysCtrl
DCSM I2C X-BAR

See the F28004x Peripheral Driver Library User’s Guide for details

Driverlib Examples
 Example projects are helpful for getting started

C:\ti\c2000\C2000Ware_<version>\driverlib\f28004x\examples

3-8 TMS320F28004x Microcontroller Workshop - Peripherial Register Programming

 Driver Library (Driverlib)

Content Assist
Content Assist

Activate by: Ctrl + Space

The Content Assist feature can be used to offer suggestions for completing function and
parameter names. Also, hover over the function to view its description.

Driverlib Documentation
Driverlib Documentation
Available in .pdf or .html formats

C:\ti\c2000\C2000Ware_<version>\device_support\f28004x\docs

TMS320F28004x Microcontroller Workshop - Peripherial Register Programming 3-9

Driver Library (Driverlib)

Driverlib Summary
Driverlib Summary
 Easier code development
 Easy to use
 Has been written to be optimized well
 CCS – hover over function to view description
 Compatible with Bit Field Header Files
 TI has already done all the work!
 Use the correct Driverlib package for your device:

F28004x F2807x F2837xS F2837xD

Go to http://www.ti.com and enter “C2000Ware” in the keyword search box

Lab File Directory Structure

Lab File Directory Structure
Supporting Files
 Easier to make projects portable
 ${PROJECT_ROOT} provides
an anchor point for paths to files
that travel with the project
 Easier to maintain and update
supporting files
Project Source Files
 All modified files are in the
Project Folder
Other Source Files that are
“Added” to the Project Folder
 Source files for multiple part
lab exercises

Note: CCSv9 will automatically add ALL files contained in the folder where the project is created

3 - 10 TMS320F28004x Microcontroller Workshop - Peripherial Register Programming

 Reset and Interrupts
Introduction
This module describes the device reset and interrupt process, as well as explaining how the
Peripheral Interrupt Expansion (PIE) is used to service the peripheral interrupts.

Module Objectives
Module Objectives

 Reset Sources

 Enhanced Boot Modes

 Peripheral Reset

 Interrupt Source and Interrupt Structure

 Peripheral Interrupt Expansion

 Initialize Interrupt Module

 Event Sequence of an Interrupt

TMS320F28004x Microcontroller Workshop - Reset and Interrupts 4-1

Reset and Boot Process

Chapter Topics
Reset and Interrupts ................................................................................................................... 4-1
Reset and Boot Process ........................................................................................................... 4-3
Reset - Bootloader ................................................................................................................ 4-5
Emulation Boot Mode ............................................................................................................ 4-6
Stand-Alone Boot Mode ........................................................................................................ 4-7
Boot Mode Definition ............................................................................................................. 4-8
Reset Code Flow – Summary ............................................................................................... 4-9
Emulation Boot Mode using Code Composer Studio GEL ................................................... 4-9
Getting to main() ................................................................................................................. 4-10
Peripheral Software Reset Registers .................................................................................. 4-11
Interrupts ................................................................................................................................. 4-12
Interrupt Processing ............................................................................................................ 4-13
Interrupt Enable Register (IER) ........................................................................................... 4-14
Interrupt Global Mask Bit (INTM) ........................................................................................ 4-14
Peripheral Interrupt Expansion (PIE) .................................................................................. 4-15
PIE Block Initialization ......................................................................................................... 4-18
Interrupt Signal Flow – Summary........................................................................................ 4-20
Interrupt Response and Latency ......................................................................................... 4-21

4-2 TMS320F28004x Microcontroller Workshop - Reset and Interrupts

 Reset and Boot Process

Reset and Boot Process

Reset Sources
Missing Clock Detect CPU
Watchdog Reset
Power-on Reset XRS
NMI WD Reset
XRS pin active
To XRS pin
Logic shown is functional representation, not actual implementation

 POR – Power-on Reset generates a device reset during

power-up conditions
 RESC – Reset Cause register contains the cause of the
last reset (sticky bits maintain state with multiple resets)
 NMI WD Reset – module detects hardware errors and
triggers a reset if the CPU does not respond to an error
within a user-specified amount of time
The device has various reset sources, which include an external reset pin, watchdog timer reset,
power-on reset which generates a device reset during power-up conditions, NMI reset, and a
missing clock detect reset. A reset cause register (RESC) is available and can be read to
determine the cause of the reset. The external reset pin is the main chip-level reset for the
device, and it resets the device to the default state. The power-on reset (POR) circuit is used to
create a clean reset throughout the device during power-up, while suppressing glitches on the
input/output pins.

TMS320F28004x Microcontroller Workshop - Reset and Interrupts 4-3

Reset and Boot Process

Enhanced Boot Modes

 The enhanced boot modes provide for the:
 Ability to move, reduce, or eliminate boot mode select pins

 BOOTPIN-CONFIG register selects boot pins to be used

 Emulation Boot Mode: EMU-BOOTPIN-CONFIG register
 Stand-Alone Boot Mode: Z1-OTP-BOOTPIN-CONFIG register

 BOOTDEF register determines boot mode option and

assignment of peripheral GPIO pins or flash/RAM entry
point
 Emulation Boot Mode: EMU-BOOTDEF-LOW/HIGH register
 Stand-Alone Boot Mode: Z1-OTP-BOOTDEF-LOW/HIGH register

When the MCU is powered-on, and each time the MCU is reset, the internal bootloader software
located in the boot ROM is executed. The boot ROM contains bootloading routines and
execution entry points into specific on-chip memory blocks. This initial software program is used
to load an application to the device RAM through the various bootable peripherals, or it can be
configured to start an application located in flash. The F28004x is extremely flexible in its ability
to use alternate, reduce, or completely eliminate boot mode selection pins by programming a
BOOTPIN_CONFIG register.

4-4 TMS320F28004x Microcontroller Workshop - Reset and Interrupts

 Reset and Boot Process

Reset - Bootloader
Reset – Bootloader

Reset vector
Reset fetched from
ENPIE = 0 boot ROM
INTM = 1 0x3F FFC0

YES Emulator NO
Connected ?

Emulation Boot Stand-alone Boot

Boot determined by Boot determined by
EMU-BOOTPIN-CONFIG GPIO pins
EMU-BOOTDEF-LOW Z1-OTP-BOOTPIN-CONFIG
EMU-BOOTDEF-HIGH Z1-OTP-BOOTDEF-LOW
Z1-OTP-BOOTDEF-HIGH

EMU BOOT registers located in PIE RAM starting at 0x000D00

Z1 OTP BOOT registers located in DCSM OTP starting at 0x05F008

After the MCU is powered-up or reset, the peripheral interrupt expansion block, also known as the
PIE block, and the master interrupt switch INTM are disabled. This prevents any interrupts during
the boot process. The program counter is set to 0x3FFFC0, where the reset vector is fetched.
Execution then continues in the boot ROM at the code section named InitBoot. If the emulator is
connected, then the boot process follows the Emulation Boot mode flow. In Emulation Boot
mode, the boot is determined by the EMU-BOOTPIN-CONFIG and EMU-BOOTDEF-LOW/HIGH
registers located in the PIE RAM. If the emulator is not connected, the boot process follows the
Stand-alone Boot mode flow. In Stand-alone Boot mode, the boot is determined by two GPIO
pins or the Z1-OTP-BOOTPIN-CONFIG and Z1-OTP-BOOTDEF-HIGH/LOW registers located in
the DCSM OTP.

TMS320F28004x Microcontroller Workshop - Reset and Interrupts 4-5

Reset and Boot Process

Emulation Boot Mode

Emulation Boot Mode
Emulator Connected
EMU-BOOTPIN-CONFIG Register
Emulation Boot 31–24 23–16 15–8 7–0
Boot determined by KEY BMSP2 BMSP1 BMSP0
EMU-BOOTPIN-CONFIG
If the BOOTPIN_CONFIG is invalid, the
BOOTPIN_CONFIG NO Boot Mode “wait” boot mode is used. The value
can then be modified using the
Key = 0x5A or 0xA5? Wait debugger and a reset issued to restart
the boot process.
YES
BOOTPIN_CONFIG BMSP2 BMSP1 BMSP0
Key = 0xA5? 0 BMSP
0xFF 0xFF 0xFF 1 Boot Mode
YES NO
0xFF 0xFF GPIO
1 BMSP
0xFF GPIO 0xFF 2 Boot Modes
(0x5A) BOOTDEF
Emulate GPIO 0xFF 0xFF
EMU-BOOTDEF-LOW
Stand-alone 0xFF GPIO GPIO
Boot Mode 2 BMSP EMU-BOOTDEF-HIGH
GPIO 0xFF GPIO 4 Boot Modes
Reads OTP for boot
pins and boot mode. GPIO GPIO 0xFF
3 BMSP
GPIO GPIO GPIO 8 Boot Modes
0xFF = BMSP field not used
GPIO = use valid GPIO pin (0-254)

In Emulation Boot mode, first the KEY value located in the EMU-BOOTPIN-CONFIG register (bit
fields 31-24) is checked for a value of 0x5A or 0xA5. If the KEY value is not 0x5A or 0xA5, the
“wait” boot mode is entered. The KEY value and the Boot Mode Selection Pin values (BMSP2-0,
bit fields 23-0) can then be modified using the debugger and a reset is issued to restart the boot
process. This is the typical sequence followed during device power-up with the emulator con-
nected, allowing the user to control the boot process using the debugger.
Once the EMU-BOOTPIN-CONFIG register is configured and a reset is issued, the KEY value is
checked again. If the KEY value is set to 0xA5 the Stand-alone Boot mode is emulated and the
Z1-OTP-BOOTPIN-CONFIG register is read for the boot pins and boot mode. Otherwise, the
KEY value is set to 0x5A and the boot mode is determined by the BMSP bit field values in the
EMU-BOOTPIN-CONFIG register and the EMU-BOOTDEF-LOW/HIGH registers. The EMU-
BOOTPIN-CONFIG register contains three BMSP bit fields. If the BMSP bit field is set to 0xFF,
then the bit field is not used. Therefore, the boot modes can be set by zero, one, two, or three
BMSP bit fields. This provides one, two, four, or eight boot mode options, respectively. Details
about the BOOTDEF options will be discussed after the Stand-alone Boot mode is covered.

4-6 TMS320F28004x Microcontroller Workshop - Reset and Interrupts

 Reset and Boot Process

Stand-Alone Boot Mode

Stand-alone Boot Mode
Emulator Not Connected
Z1-OTP-BOOTPIN-CONFIG Register
Stand-alone Boot 31–24 23–16 15–8 7–0
Boot determined by KEY BMSP2 BMSP1 BMSP0

GPIO pins BMSP1 BMSP0

Z1-OTP-BOOTPIN-CONFIG
GPIO24 GPIO32 Boot Mode
0 0 Parallel I/O
BOOTPIN_CONFIG NO
0 1 SCI / Wait
Key = 0x5A ? 1 0 CAN
YES 1 1 Flash

BMSP2 BMSP1 BMSP0

0 Pins
0xFF 0xFF 0xFF 1 Boot Mode
0xFF 0xFF GPIO
1 Pin
0xFF GPIO 0xFF 2 Boot Modes
BOOTDEF
GPIO 0xFF 0xFF
Z1-OTP-BOOTDEF-LOW
0xFF GPIO GPIO
2 Pins Z1-OTP-BOOTDEF-HIGH
GPIO 0xFF GPIO 4 Boot Modes
GPIO GPIO 0xFF
3 Pins
GPIO GPIO GPIO 8 Boot Modes
0xFF = pin not used
GPIO = use valid GPIO pin (0-254)

In Stand-alone Boot mode, if the KEY value located in the Z1-OTP-BOOTPIN-CONFIG register
(bit fields 31-24) is not 0x5A, the boot mode is determined by the default GPIO24 and GPIO32
pins. These two pins provide four boot options – Parallel I/O, SCI/Wait, CAN or Flash. If the KEY
value is 0x5A the boot mode is determined by the BMSP bit field values in the Z1-OTP-
BOOTPIN-CONFIG and the OTP-BOOTDEF-LOW/HIGH registers. The Z1-OTP-BOOTPIN-
CONFIG register contains three BMSP bit fields. If the BMSP bit field is set to 0xFF, then the
GPIO pin is not used. Therefore, the boot modes can be set by zero, one, two, or three GPIO
pins. This provides one, two, four, or eight boot mode options, respectively.

TMS320F28004x Microcontroller Workshop - Reset and Interrupts 4-7

Reset and Boot Process

Boot Mode Definition

The BOOTDEF options described here applies to both the EMU-BOOTDEF-LOW/HIGH registers
used in Emulation Boot mode and the Z1-OTP-BOOTDEF-LOW/HIGH registers used in Stand-
alone Boot mode. The BOOTDEF-LOW/HIGH registers consist of eight separate bit fields named
BOOT_DEF0 through BOOT-DEF7. These bit fields correspond to the one, two, four, or eight
boot mode options that are selected by the zero, one, two, or three BMSP bit fields/GPIO pins,
respectively in the BOOTPIN_CONFIG register. Therefore, if zero BMSP bit fields/GPIO pins are
selected, then only the BOOT_DEF0 bit field in the BOOTDEF-LOW/HIGH registers is used.
Likewise, if three BMSP bit fields/GPIO pins are selected, then BOOT_DEF0 through
BOOT_DEF7 in the BOOTDEF-LOW/HIGH registers is used.

Boot Mode Definition

Provides flexibility to move or eliminate boot select pins
63 - 56 55 - 48 47- 40 39- 32
BOOTDEF-HIGH BOOT_DEF7 BOOT_DEF6 BOOT_DEF5 BOOT_DEF4

31 - 24 23 - 16 15 - 8 7-0
BOOTDEF-LOW BOOT_DEF3 BOOT_DEF2 BOOT_DEF1 BOOT_DEF0

Parallel I/O Wait

Value D0 – D7 DSP Ctrl Host Ctrl Value WD Status
Options Mode
0x00 GPIO0-7 GPIO16 GPIO11 0x04 Enabled
RAM
SCI 0x24 Disabled
Value Entry Point
Value SCIATX SCIARX Flash Value Boot Mode
0x05 0x0000000
0x01 GPIO29 GPIO28 Value Entry Point I2C 0 Parallel I/O
0x21 GPIO16 GPIO17 0x03 0x0080000 Value SDAA SCLAA 1 SCI / Wait
0x41 GPIO8 GPIO9 0x23 0x008EFF0 0x07 GPIO32 GPIO33 2 CAN
0x61 GPIO48 GPIO49 0x43 0x0090000 0x47 GPIO26 GPIO27 3 Flash
0x81 GPIO24 GPIO25 0x63 0x009EFF0 0x67 GPIO42 GPIO43 4 Wait

SPI CAN 5 RAM

Value SPIA_SIMO SPIA_SOMI SPIA_CLK SPIA_STE Value CANTXA CANRXA 6 SPI

0x26 GPIO8 GPIO10 GPIO9 GPIO11 0x02 GPIO32 GPIO33 7 I2C

0x46 GPIO54 GPIO55 GPIO56 GPIO57 0x22 GPIO4 GPIO5 8 PLC

0x66 GPIO16 GPIO17 GPIO56 GPIO57 0x42 GPIO31 GPIO30

0x86 GPIO8 GPIO17 GPIO9 GPIO11 0x62 GPIO37 GPIO35

The value in the BOOT_DEF bit fields determines which peripheral is used for bootloading or the
entry point that is used for code execution. In the BOOT_DEF bit field the lower bits define the
boot mode used and the upper bits define the options for that bit mode. Utilizing this type of
booting technique provides flexibility for selecting multiple boot modes, as well as reducing the
number of boot mode pins.

4-8 TMS320F28004x Microcontroller Workshop - Reset and Interrupts

 Reset and Boot Process

Reset Code Flow – Summary

In summary, the reset code flow is as follows. After reset, the program counter is set to
0x3FFFC0, where the flow is vectored to the Init_Boot code in the Boot ROM. The Init_Boot code
defines the execution entry based on emulation boot mode or stand-alone boot mode. The entry
point can be executing boot-loading routines, entry to the flash, or M0 RAM.

Reset Code Flow - Summary

0x000000 0x000000
M0 RAM (1Kw)

0x080000 0x080000

0x08EFF0
FLASH (128Kw)
0x090000

0x09EFF0

0x3F8000 Boot ROM (32Kw) Execution entry

determined by
Boot Code Emulation Boot Mode or
Stand-Alone Boot Mode
InitBoot
• •
• •

BROM vector (64w)

RESET 0x3FFFC0 * reset vector Bootloading
Routines
(SCI, SPI, I2C,
CAN, Parallel I/O)

* reset vector = 0x3FC7A5

Emulation Boot Mode using Code Composer

Studio GEL
The CCS GEL file is used to setup the boot modes for the device during debug. By default the
GEL file provides functions to set the device for “Boot to SARAM” and “Boot to FLASH”. The
GEL file can be modified to include other boot mode options, if desired.

/********************************************************************/
/* EMU Boot Mode - Set Boot Mode During Debug */
/********************************************************************/
menuitem "EMU Boot Mode Select"
hotmenu EMU_BOOT_SARAM()
{
*(unsigned long *)0xD00 = 0x5AFFFFFF;
*0xD04 = 0x0005;
}
hotmenu EMU_BOOT_FLASH()
{
*(unsigned long *)0xD00 = 0x5AFFFFFF;
*0xD04 = 0x0003;
}

To access the GEL file use: Tools  GEL Files

TMS320F28004x Microcontroller Workshop - Reset and Interrupts 4-9

Reset and Boot Process

Getting to main()
After reset how do we get to main()?
 At the code entry point, branch to _c_int00()
 Part of compiler run-time support library
 Sets up compiler environment
 Calls main()

.sect “codestart”
CodeStartBranch.asm
LB _c_int00

MEMORY
{
PAGE 0:
BEGIN_M0 : origin = 0x000000, length = 0x000002
Linker .cmd }
SECTIONS
{
codestart : > BEGIN_M0, PAGE = 0
}

Note: the above example is for boot mode set to RAMM0; to run out of Flash, the
“codestart” section would be linked to the entry point of the Flash memory block

After reset how do we get to main? When the bootloader process is completed, a branch to the
compiler runtime support library is located at the code entry point. This branch to _c_int00 is
executed, then the compiler environment is set up, and finally main is called.

4 - 10 TMS320F28004x Microcontroller Workshop - Reset and Interrupts

 Reset and Boot Process

Peripheral Software Reset Registers

Peripheral Software Reset
Peripheral Software
Peripheral
Reset Signal
SOFTPRESx
Register

 Driverlib function used to reset a peripheral:

SysCtl_resetPeripheral(peripheral);
 peripheral parameter values:
SYSCTL_PERIPH_RES_CLA1 SYSCTL_PERIPH_RES_ADCx (x = A to C)

SYSCTL_PERIPH_RES_EPWMx (x = 1 to 8) SYSCTL_PERIPH_RES_CMPSSx (x = 1 to 7)

SYSCTL_PERIPH_RES_ECAPx (x = 1 to 7) SYSCTL_PERIPH_RES_PGAx (x = 1 to 7)

SYSCTL_PERIPH_RES_EQEPx (x = 1 or 2) SYSCTL_PERIPH_RES_DACx (x = A or B)

SYSCTL_PERIPH_RES_SD1 SYSCTL_PERIPH_RES_FSITXA

SYSCTL_PERIPH_RES_SCIx (x = A or B) SYSCTL_PERIPH_RES_FSIRXA

SYSCTL_PERIPH_RES_SPIx (x = A or B) SYSCTL_PERIPH_RES_LINA

SYSCTL_PERIPH_RES_I2CA SYSCTL_PERIPH_RES_PMBUSA

SYSCTL_PERIPH_RES_CANx (x = A or B)

The peripheral software reset register (SOFTPRESx) contains the reset bit for each peripheral.
The Driverlib functions are used to reset a peripheral, as shown above.

TMS320F28004x Microcontroller Workshop - Reset and Interrupts 4 - 11

Interrupts

Interrupts
Interrupt Sources

TINT0
Timer0 NMI
NMI NMI
LPMINT
LPM Logic WAKEINT
WDINT CPU
Watchdog

INPUT4
XINT1 PIE INT1
GPIO0 (Peripheral to
INPUT5
GPIO1 XINT2 Interrupt INT12
Input INPUT6 Expansion)
●
●
XINT3
●
X-BAR INPUT13
XINT4
GPIOx
INPUT14
XINT5
TINT1
Timer1 INT13
TINT2
Peripheral Timer2 INT14
Interrupts

The internal interrupt sources include the general purpose timers 0, 1, and 2, and all of the
peripherals on the device. External interrupt sources include the five external interrupt lines,
which are mapped through the Input X-BAR, and the external reset pin. The CPU core has 14
interrupt lines. The Peripheral Interrupt Expansion block, known as the PIE block, is connected to
the core interrupt lines 1 through 12 and is used to expand the CPU core interrupt capability,
allowing up to 192 possible interrupt sources.

4 - 12 TMS320F28004x Microcontroller Workshop - Reset and Interrupts

 Interrupts

Interrupt Processing
Maskable Interrupt Processing
Conceptual Core Overview

Core (IFR) (IER) (INTM)

Interrupt Interrupt Interrupt Global
Flag Enable Interrupt
Line Register Register Mask

INT1 1

INT2 0 C28x
CPU

INT14 1

 If an interrupt signal is recognized, the corresponding IFRBit is set and latched

 If the IERBit is set and the INTM is clear, the CPU receives the interrupt
 Compiler generates atomic instructions (non-interruptible) for setting/clearing IFR
 IFRBit is cleared when interrupt is acknowledged by CPU
 The IFR register is cleared on reset

By using a series of flag and enable registers, the CPU can be configured to service one interrupt
while others remain pending, or perhaps disabled when servicing certain critical tasks. When an
interrupt signal occurs on a core line, the interrupt flag register (IFR) for that core line is set. If the
appropriate interrupt enable register (IER) is enabled for that core line, and the interrupt global
mask (INTM) is enabled, the interrupt signal will propagate to the core. Once the interrupt service
routine (ISR) starts processing the interrupt, the INTM bit is disabled to prevent nested interrupts.
The IFR is then cleared and ready for the next interrupt signal. When the interrupt servicing is
completed, the INTM bit is automatically enabled, allowing the next interrupt to be serviced.
Notice that when the INTM bit is ‘0’, the “switch” is closed and enabled. When the bit is ‘1’, the
“switch” is open and disabled. The IER is managed by enabling and disabling Driverlib parameter
values. The INTM bit in the status register is managed by using a Driverlib function or in-line
assembly instructions (macro).

TMS320F28004x Microcontroller Workshop - Reset and Interrupts 4 - 13

Interrupts

Interrupt Enable Register (IER)

Interrupt Enable Register (IER)
15 14 13 12 11 10 9 8
RTOSINT DLOGINT INT14 INT13 INT12 INT11 INT10 INT9
7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1

Enable: Set IER Bit = 1

Disable: Clear IER Bit = 0

 Driverlib function used to modify IER:

Interrupt_enableInCPU(cpuInterrupt);
Interrupt_disableInCPU(cpuInterrupt);
 cpuInterrupt parameter is a logical OR of the values:
 INTERRUPT_CPU_INTx
 where x is the interrupt number between 1 and 14
 INTERRUPT_CPU_DLOGINT
 INTERRUPT_CPU_RTOSINT
 IER register is cleared on reset

Interrupt Global Mask Bit (INTM)

Interrupt Global Mask Bit
Bit 0
ST1 INTM

 INTM is used to globally enable/disable interrupts:

 Enable: INTM = 0
 Disable: INTM = 1 (reset value)

 Driverlib function used to modify INTM:

Interrupt_enableMaster();
Interrupt_disableMaster();

 Alternatively the following macros can be used:

EINT; //defined as - asm(" clrc INTM");
DINT; //defined as - asm(" setc INTM");

4 - 14 TMS320F28004x Microcontroller Workshop - Reset and Interrupts

 Interrupts

Peripheral Interrupt Expansion (PIE)

Peripheral Interrupt Expansion - PIE
Interrupt Group 1
PIE module for 192 Interrupts
PIEIFR1 PIEIER1
12 x 16 = 192 INT1.y interrupt group INT1.1 1
INT2.y interrupt group
INT1.2 0
INT3.y interrupt group INT1
• •
INT4.y interrupt group • •
INT5.y interrupt group
• •
INT1.16 1
Peripheral Interrupts

INT6.y interrupt group

192
INT7.y interrupt group
Core Interrupt logic
INT8.y interrupt group
INT9.y interrupt group INT1 – INT12

INTM
INT10.y interrupt group C28x

IER
IFR
12 Interrupts
INT11.y interrupt group CPU

INT12.y interrupt group

INT13 (TINT1)
INT14 (TINT2)
NMI

The C28x CPU core has a total of fourteen interrupt lines, of which two interrupt lines are directly
connected to CPU Timers 1 and 2 (on INT13 and INT14, respectively) and the remaining twelve
interrupt lines (INT1 through INT12) are used to service the peripheral interrupts. A Peripheral
Interrupt Expansion (PIE) module multiplexes up to sixteen peripheral interrupts into each of the
twelve CPU interrupt lines, further expanding support for up to 192 peripheral interrupt signals.
The PIE module also expands the interrupt vector table, allowing each unique interrupt signal to
have its own interrupt service routine (ISR), permitting the CPU to support a large number of
peripherals.

The PIE module has an individual flag and enable bit for each peripheral interrupt signal. Each of
the sixteen peripheral interrupt signals that are multiplexed into a single CPU interrupt line is
referred to as a “group”, so the PIE module consists of 12 groups. Each PIE group has a 16-bit
flag register (PIEIFRx), a 16-bit enable register (PIEIERx), and a bit field in the PIE acknowledge
register (PIEACK) which acts as a common interrupt mask for the entire group. For a peripheral
interrupt to propagate to the CPU, the appropriate PIEIFR must be set, the PIEIER enabled, the
CPU IFR set, the IER enabled, and the INTM enabled. Note that some peripherals can have
multiple events trigger the same interrupt signal, and the cause of the interrupt can be determined
by reading the peripheral’s status register.

We have already discussed the interrupt process in the core. Now we need to look at the
peripheral interrupt expansion block. This block is connected to the core interrupt lines 1 through
12. The PIE block consists of 12 groups. Within each group, there are sixteen interrupt sources.
Each group has a PIE interrupt enable register and a PIE interrupt flag register. Note that
interrupt lines 13, 14, and NMI bypass the PIE block.

TMS320F28004x Microcontroller Workshop - Reset and Interrupts 4 - 15

Interrupts

F28004x PIE Assignment Table - Lower

INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1

INT1 WAKE TIMER0 XINT2 XINT1 ADCC1 ADCB1 ADCA1

(WDOG)
EPWM8_ EPWM7_ EPWM6_ EPWM5_ EPWM4_ EPWM3_ EPWM2_ EPWM1_
INT2 TZ TZ TZ TZ TZ TZ TZ TZ

INT3 EPWM8 EPWM7 EPWM6 EPWM5 EPWM4 EPWM3 EPWM2 EPWM1

INT4 ECAP7 ECAP6 ECAP5 ECAP4 ECAP3 ECAP2 ECAP1

INT5 EQEP2 EQEP1

INT6 SPIB_TX SPIB_RX SPIA_TX SPIA_RX

INT7 DMA_CH6 DMA_CH5 DMA_CH4 DMA_CH3 DMA_CH2 DMA_CH1

I2CA_
INT8 FIFO I2CA

INT9 CANB_1 CANB_0 CANA_1 CANA_0 SCIB_TX SCIB_RX SCIA_TX SCIA_RX

ADCB_ ADCA_
INT10 ADCB4 ADCB3 ADCB2 EVT ADCA4 ADCA3 ADCA2 EVT

INT11 CLA1_8 CLA1_7 CLA1_6 CLA1_5 CLA1_4 CLA1_3 CLA1_2 CLA1_1

FPU_UND FPU_OV
INT12 ERFLOW ERFLOW XINT5 XINT4 XINT3

Note: above label names proceed with INT_ and #defines are located in driverlib/inc/hw_ints.h

The PIE assignment table maps each peripheral interrupt to the unique vector location for that
interrupt service routine. Notice the interrupt numbers on the left represent the twelve core group
interrupt lines and the interrupt numbers across the top represent the lower eight of the sixteen
peripheral interrupts within the core group interrupt line. The next figure shows the upper eight of
the sixteen peripheral interrupts within the core group interrupt line.

F28004x PIE Assignment Table - Upper

INTx.16 INTx.15 INTx.14 INTx.13 INTx.12 INTx.11 INTx.10 INTx.9

INT1

INT2

INT3

INT4 ECAP7_2 ECAP6_2

SDFM1 SDFM1 SDFM1 SDFM1
INT5 DR4 DR3 DR2 DR1 SDFM1

INT6
CLA1PR FSIRXA_ FSIRXA_ FSITXA_ FSITXA_
INT7 DCC OMCRC INT2 INT1 INT2 INT1

INT8 PMBUSA LINA_1 LINA_0

INT9
ADCC_
INT10 ADCC4 ADCC3 ADCC2 EVT

INT11
CLA_UND CLA_OV SYS_PLL RAM_ACC FLASH_CO RAM_CO
INT12 ERFLOW ERFLOW _SLIP _VIOL RR_ERR RR_ERR
Note: above label names proceed with INT_ and #defines are located in driverlib/inc/hw_ints.h

4 - 16 TMS320F28004x Microcontroller Workshop - Reset and Interrupts

 Interrupts

PIEIER and PIEACK Registers

PIEIERx register (x = 1 to 12)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTx.16 INTx.15 INTx.14 INTx.13 INTx.12 INTx.11 INTx.10 INTx.9 INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1

PIE Interrupt Acknowledge register (PIEACK)

15 - 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PIEACKx

 NOTE: These Driverlib functions modify BOTH the

PIEIER and core IER registers:
Interrupt_enable(interruptNumber);
Interrupt_disable(interruptNumber);
 interruptNumber values are supplied in driverlib/inc/hw_ints.h
 Driverlib function used to acknowledge PIE group:
Interrupt_clearACKGroup(group);
 group parameter is a logical OR of the values:
 INTERRUPT_ACK_GROUPx
 where x is the interrupt number between 1 and 12
 Acknowledges group and clears any interrupt flag within group
 Required to receive further interrupts in PIE group (done in ISR)

Similar to the core interrupt process, the PIE module has an individual flag and enable bit for
each peripheral interrupt signal. Each PIE group has a 16-bit flag register, a 16-bit enable
register, and a bit field in the PIE acknowledge register which acts as a common interrupt mask
for the entire group. An enable PIE bit in the PIECTRL register is used to activate the PIE
module. Note that when using the Driverlib function to enable and disable interrupts, both the
PIEIER and CPU core IER registers are modified.

TMS320F28004x Microcontroller Workshop - Reset and Interrupts 4 - 17

Interrupts

PIE Block Initialization

Initialize Interrupt Module and PIE Block
Main.c interrupt.c
// CPU Initialization Set INTM (disable)
• Clear CPU IER
•
• Clear CPU IFR
Interrupt_initModule();
Interrupt_initVectorTable(); Clear PIEIER registers
• Clear PIEIFR registers
•
• Enable vector fetching
from PIE block

interrupt.c Memory Map

*** Initialize PIE Vectors ***
Set all vector locations to:
Interrupt_defaultHandler()
Set NMI vector location to:
Interrupt_nmiHandler() PIE RAM
Set ITRAP vector location to: Vectors
Interrupt_illegalOperationHandler() 512w
(ENPIE = 1)

Default PIE vectors are then remapped to call user ISR:

Interrupt_register(interruptNumber, &userNameISR);
interruptNumber values located in driverlib/inc/hw_ints.h Boot ROM
Reset Vector
Note: interrupt.c is located in \driverlib folder

Two separate functions are called to initialize the the interrupt module and PIE block. During
processor initialization the interrupt vectors, as mapped in the PIE interrupt assignment table, is
copied to the PIE RAM and then the PIE module is enabled by setting ENPIE to ‘1’. When the
CPU receives an interrupt, the vector address of the ISR is fetched from the PIE RAM, and the
interrupt with the highest priority that is both flagged and enabled is executed. Priority is
determined by the location within the interrupt vector table. The lowest numbered interrupt has
the highest priority when multiple interrupts are pending.

4 - 18 TMS320F28004x Microcontroller Workshop - Reset and Interrupts

 Interrupts

PIE Initialization Code Flow - Summary

RESET Reset Vector Boot option determines
<0x3F FFC0> <reset vector> = Boot Code code execution entry point

CodeStartBranch.asm
.sect “codestart”

M0 RAM Entry Point Flash Entry Point

<0x00 0000> = LB _c_int00
OR <0x08 0000> = LB _c_int00

_c_int00: rts2800_fpu32.lib
• Interrupt
•
•
CALL main()
PIE Vector Table

Main.c Initialization() 512 Word RAM

{ 0x00 0D00 – 0EFF
main() Load PIE Vectors
{ initialization(); Enable the PIE DefaultIsr.c
• Enable PIEIER
• interrupt void name(void)
• Enable CPU IER
} Enable INTM {
•
} •
•
}

In summary, the PIE initialization code flow is as follows. After the device is reset and execution
of the boot code is completed, the selected boot option determines the code entry point. In this
figure, two different entry points are shown. The one on the left is for memory block M0 RAM,
and the one on the right is for flash.

In either case, the CodeStartBranch.asm file has a Long Branch instruction to the entry point of
the runtime support library. After the runtime support library completes execution, main is called.
In main, the two functions are called to initialize the interrupt process and enable the PIE module.
When the CPU receives an interrupt, the vector address of the ISR is fetched from the PIE RAM,
and the interrupt with the highest priority that is both flagged and enabled is executed. Priority is
determined by the location within the interrupt vector table.

TMS320F28004x Microcontroller Workshop - Reset and Interrupts 4 - 19

Interrupts

Interrupt Signal Flow – Summary

Interrupt Signal Flow – Summary
Peripheral Interrupt Expansion (PIE) – Interrupt Group x
PIEIFRx PIEIERx
Peripheral INTx.y
Interrupt
1
Interrupt_enable(interruptNumber);

Core Interrupt Logic

Core IFR IER INTM
INTx
1
EINT;
or: Interrupt_enableMaster();

PIE Vector Table DefaultIsr.c

interrupt void name(void)
{
•
•
•
}
INTx.y  name
(For peripheral interrupts where x = 1 to 12, and y = 1 to 16)

In summary, the following steps occur during an interrupt process. First, a peripheral interrupt is
generated and the PIE interrupt flag register is set. If the PIE interrupt enable register is enabled,
then the core interrupt flag register will be set. Next, if the core interrupt enable register and
global interrupt mask is enabled, the PIE vector table will redirect the code to the interrupt service
routine.

4 - 20 TMS320F28004x Microcontroller Workshop - Reset and Interrupts

 Interrupts

Interrupt Response and Latency

Interrupt Response - Hardware Sequence
CPU Action Description
Registers → stack 14 Register words auto saved
0 → IFR (bit) Clear corresponding IFR bit
0 → IER (bit) Clear corresponding IER bit
1 → INTM/DBGM Disable global ints/debug events
Vector → PC Loads PC with int vector address
Clear other status bits Clear LOOP, EALLOW, IDLESTAT

Note: some actions occur simultaneously, none are interruptible

T ST0
AH AL
PH PL
AR1 AR0
DP ST1
DBSTAT IER
PC(msw) PC(lsw)

Interrupt Latency
Latency
ext. Internal
interrupt interrupt Assumes ISR in
occurs occurs internal RAM
here here

cycles
2 4 3 3 1 3
Recognition Get vector ISR
Sync ext. F1/F2/D1 of Save D2/R1/R2 of instruction
signal delay (3), SP and place ISR return ISR executed
alignment (1), in PC instruction address instruction
(ext. interrupt (3 reg. on next
(3 reg. pairs cycle
interrupt placed in pairs saved)
only) pipeline saved)

 Minimum latency (to when real work occurs in the ISR):

 Internal interrupts: 14 cycles
 External interrupts: 16 cycles

 Maximum latency: Depends on wait states, INTM, etc.

TMS320F28004x Microcontroller Workshop - Reset and Interrupts 4 - 21

Interrupts

4 - 22 TMS320F28004x Microcontroller Workshop - Reset and Interrupts

 System Initialization
Introduction
This module covers the operation of the OSC/PLL-based clock module and watchdog timer.
Also, the general-purpose digital I/O, external interrups, low power modes and the register
protection will be covered.

Module Objectives
Module Objectives

 OSC/PLL Clock Module

 Watchdog Timer
 General Purpose I/O
 External Interrupts
 Low Power Modes
 Register Protection

TMS320F28004x Microcontroller Workshop - System Initialization 5-1

Oscillator/PLL Clock Module

Chapter Topics
System Initialization .................................................................................................................... 5-1
Oscillator/PLL Clock Module ..................................................................................................... 5-3
Initializing Clock Modules ...................................................................................................... 5-5
Watchdog Timer ........................................................................................................................ 5-6
General Purpose Digital I/O .................................................................................................... 5-10
Configuring GPIO Pins ........................................................................................................ 5-11
GPIO Input X-Bar ................................................................................................................ 5-14
GPIO Output X-Bar ............................................................................................................. 5-15
External Interrupts ................................................................................................................... 5-17
Low Power Modes ................................................................................................................... 5-18
Register Protection.................................................................................................................. 5-20
Lab 5: System Initialization ..................................................................................................... 5-22

5-2 TMS320F28004x Microcontroller Workshop - System Initialization

 Oscillator/PLL Clock Module

Oscillator/PLL Clock Module

Oscillator / PLL Clock Module
Internal OSC1CLK
OSC 1 WDCLK
(10 MHz) CLKSRCCTL1
SYSPLLCTL1
Internal OSC2CLK 1x OSCCLK
SYSCLKDIVSEL
OSC 2 00* 0*
(10 MHz) (PLL bypass)
01

MUX
1/n PLLSYSCLK
XCLKIN X1

XTAL OSC
(X2 n.c.) PLLCLK
PLL 1
XTAL

XTAL

SYSPLLMULT SYSCLK
X2 CPU CPUCLK

One per SYSCLK peripheral

PCLKCRx
PERxSYSCLK

One per LSPCLK peripheral

PCLKCRx
PERxLSPCLK
LOSPCP LSPCLK

One per CAN module

CLKSRCCTL2

0* CAN bit Clock

1
* default

The device clock signals are derived from one of four clock sources: Internal Oscillator 1
(INTOSC1), Internal Oscillator 2 (INTOSC2), External Oscillator (XTAL), and single-ended 3.3V
external clock (XCLKIN). At power-up, the device is clocked from the on-chip 10 MHz oscillator
INTOSC2. INTSOC2 is the primary internal clock source, and is the default system clock at
reset. The device also includes a redundant on-chip 10 MHz oscillator INTOSC1. INTOSC1 is a
backup clock source, which normally only clocks the watchdog timers and missing clock detection
circuit. Additionally, the device includes dedicated X1 and X2 pins for supporting an external
clock source such as an external oscillator, crystal, or resonator.

TMS320F28004x Microcontroller Workshop - System Initialization 5-3

Oscillator/PLL Clock Module

PLL and LOSPCP

INTOSC1 1x
OSCCLK
INTOSC2 00* 0*
(PLL bypass)
XTAL 01 PLLSYSCLK
1/n CPU SYSCLK
PLLCLK
PLL 1

LOSPCP LSPCLK
SYSCTL_PLL_ENABLE
SYSCTL_OSCSRC_OSC1 SYSCTL_PLL_DISABLE
SYSCTL_OSCSRC_OSC2
SYSCTL_SYSDIV(x)
SYSCTL_OSCSRC_XTAL
where x is either 1 or an
even value up to 126

SYSCTL_FMULT_0
SYSCTL_IMULT(x) SYSCTL_LSPCLK_PRESCALE_x
SYSCTL_FMULT_1_4
where x is a value where x is 1, 2, 4, 6, 8, 10, 12, 14
from 1 to 127 SYSCTL_FMULT_1_2
SYSCTL_FMULT_3_4

SysCtl_setClock(config); SysCtl_setLowSpeedClock( );
The config parameter is the OR of several LSPCLK = SYSCLK / 4 (default)
different values, many of which are grouped
into sets where only one can be chosen

The clock sources can be multiplied using the PLL and divided down to produce the desired clock
frequencies for a specific application. A clock source can be fed directly into the CPU or
multiplied using the PLL. The PLL provides the capability to use the internal 10 MHz oscillator
and run the device at the full clock frequency. If the input clock is removed after the PLL is
locked, the input clock failed detect circuitry will issue a limp mode clock of 1 to 4 MHz.
Additionally, an internal device reset will be issued. The low-speed peripheral clock prescaler is
used to clock some of the communication peripherals.

The PLL has a 7-bit integer and 2-bit fractional ratio control to select different CPU clock rates.
The C28x CPU provides a SYSCLK clock signal. This signal is prescaled to provide a clock
source for some of the on-chip communication peripherals through the low-speed peripheral clock
prescaler. Other peripherals are clocked by SYSCLK and use their own clock prescalers for
operation.

5-4 TMS320F28004x Microcontroller Workshop - System Initialization

 Oscillator/PLL Clock Module

Initializing Clock Modules

Initializing Clock Modules
Main.c device.c
// CPU Initialization void Device_init(void)
Device_init(); {
• // Set up PLL control and clock dividers
•
• SysCtl_setClock(DEVICE_SETCLOCK_CFG);
sysctl.h SysCtl_setLowSpeedClock(SYSCTL_LSPCLK_PRESCALE_4);
// Turn on all peripherals
Contains values that
can be passed to: Device_enableAllPeripherals();
SysCtl_setClock() }
SysCtl_setLowSpeedClock() void Device_enableAllPeripherals(void )
SysCtl_enablePeripheral() {
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_<name>);
• •
• •
• •
}

device.h
#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL |
100 MHz SYSCLK frequency
based on SYSCTL_IMULT(10) |
DEVICE_SETCLOCK_CFG SYSCTL_FMULT_NONE |
PLLSYSCLK = 20MHz SYSCTL_SYSDIV(2) |
(XTAL_OSC) * 10 (IMULT) * 1 SYSCTL_PLL_ENABLE)
(FMULT) / 2 (PLLCLK_BY_2)

The peripheral clock control register (PCLKCRx) allows individual peripheral clock signals to be
enabled or disabled using a Driverlib function. If a peripheral is not being used, its clock signal
could be disabled, thus reducing power consumption.

Peripheral Clock Enable / Disable

SYSCLK Peripheral
PCLKCRx
Register

 Driverlib function used to enable / disable peripheral:

SysCtl_[enable|disable]Peripheral(peripheral);
 peripheral parameter values:
SYSCTL_PERIPH_CLK_CLA1 SYSCTL_PERIPH_CLK_ADCx (x = A to C)

SYSCTL_PERIPH_CLK_EPWMx (x = 1 to 8) SYSCTL_PERIPH_CLK_CMPSSx (x = 1 to 7)

SYSCTL_PERIPH_CLK_ECAPx (x = 1 to 7) SYSCTL_PERIPH_CLK_PGAx (x = 1 to 7)

SYSCTL_PERIPH_CLK_EQEPx (x = 1 or 2) SYSCTL_PERIPH_CLK_DACx (x = A or B)

SYSCTL_PERIPH_CLK_SD1 SYSCTL_PERIPH_CLK_FSITXA

SYSCTL_PERIPH_CLK_SCIx (x = A or B) SYSCTL_PERIPH_CLK_FSIRXA

SYSCTL_PERIPH_CLK_SPIx (x = A or B) SYSCTL_PERIPH_CLK_LINA

SYSCTL_PERIPH_CLK_I2CA SYSCTL_PERIPH_CLK_PMBUSA

SYSCTL_PERIPH_CLK_CANx (x = A or B) SYSCTL_PERIPH_CLK_DCC0

TMS320F28004x Microcontroller Workshop - System Initialization 5-5

Watchdog Timer

Watchdog Timer
The watchdog timer is a safety feature, which resets the device if the program runs away or gets
trapped in an unintended infinite loop. The watchdog counter runs independent of the CPU. If
the counter overflows, a user-selectable reset or interrupt is triggered. During runtime the correct
key values in the proper sequence must be written to the watchdog key register in order to reset
the counter before it overflows.

Watchdog Timer
 Resets the device if the CPU crashes
 Watchdog counter runs independently of CPU
 If counter overflows, a reset or interrupt is
triggered (user selectable)
 CPU must write correct data key sequence to
reset the counter before overflow
 Watchdog must be serviced or disabled
within 131,072 WDCLK cycles after reset
 This translates to 13.11 ms with a 10 MHz
WDCLK

The watchdog timer provides a safeguard against CPU crashes by automatically initiating a reset
if it is not serviced by the CPU at regular intervals. In motor control applications, this helps
protect the motor and drive electronics when control is lost due to a CPU lockup. Any CPU reset
will set the PWM outputs to a high-impedance state, which will turn off the power converters in a
properly designed system.

The watchdog timer starts running immediately after system power-up/reset, and must be dealt
with by software soon after. Specifically, the watchdog must be serviced or disabled within 13.11
milliseconds (using a 10 MHz watchdog clock) after any reset before a watchdog initiated reset
will occur. This translates into 131,072 watchdog clock cycles, which is a seemingly tremendous
amount! Indeed, this is plenty of time to get the watchdog configured as desired and serviced. A
failure of your software to properly handle the watchdog after reset could cause an endless cycle
of watchdog initiated resets to occur.

5-6 TMS320F28004x Microcontroller Workshop - System Initialization

 Watchdog Timer

Watchdog Timer Module

WDOVERRIDE
WDPRECLKDIV WDPS
Watchdog Watchdog
WDCLK
Pre-divider Pre-scaler WDDIS

WDCNTR
8-bit Watchdog
Counter
CLR CNT
WDRST
System Output
Reset Pulse
WDWCR WDCNTR
less than WDINT
window WDWCR
55 + AA
Detector minimum
Good Key

WDCHK
Watchdog
Reset Key
Register 3
/
/ Bad WDCHK Key
WDKEY 3
1 0 1

The watchdog clock is divided by the pre-divider and then pre-scaled, if desired for slower
watchdog time periods. A watchdog disable switch allows the watchdog to be enabled and
disabled. Also a watchdog override switch provides an additional safety mechanism to insure the
watchdog cannot be disabled. Once set, the only means to disable the watchdog is by a system
reset.

During initialization, a value ‘101’ is written into the watchdog check bit fields. Any other values
will cause a reset or interrupt. During run time, the correct keys must be written into the
watchdog key register before the watchdog counter overflows and issues a reset or interrupt.
Issuing a reset or interrupt is user-selectable. The watchdog also contains an optional
“windowing” feature that requires a minimum delay between counter resets.

TMS320F28004x Microcontroller Workshop - System Initialization 5-7

Watchdog Timer

Watchdog Pre-divider and Pre-scaler

WDPRECLKDIV WDPS
Watchdog Watchdog
WDCLK
Pre-divider Pre-scaler

SysCtl_setWatchdogPredivider(SYSCTL_WD_PREDIV_x);
where x is 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, or 4096
default = 512 (providing backwards compatibility)

SysCtl_setWatchdogPrescaler(SYSCTL_WD_PRESCALE_x);
where x is 1, 2, 4, 8, 16, 32, or 64
default = 1

 Remember: Watchdog starts counting immediately

after reset is released!
 Reset default with WDCLK = 10 MHz computed as
(1/10 MHz) * 512 * 1 * 256 = 13.11 ms

Watchdog Driverlib Functions

 WDDIS – disable / enable
 Functions only if WDOVERRIDE is not cleared
SysCtl_disableWatchdog();
SysCtl_enableWatchdog();
 WDOVERRIDE (clear only to protect – reset device to disable)
SysCtl_clearWatchdogOverride();
 Watchdog Mode – reset / interrupt
SysCtl_setWatchdogMode(mode);
 mode parameter values:
SYSCTL_WD_MODE_RESET
SYSCTL_WD_MODE_INTERRUPT
 Watchdog Minimum Window
SysCtl_setWatchdogWindowValue(value);
 value parameter sets a minimum delay between counter
resets (0 = disabled)

5-8 TMS320F28004x Microcontroller Workshop - System Initialization

 Watchdog Timer

Resetting the Watchdog

 Driverlib functions:
 SysCtl_serviceWatchdog(); // resets the watchdog
 SysCtl_enableWatchdogReset(); // writes 0x55 WDKEY
 SysCtl_resetWatchdog(); // writes 0xAA WDKEY

 WDKEY write values:

0x55 - counter enabled for reset on next 0xAA write
0xAA - counter set to zero if reset enabled
 Writing
any other value has no effect
 Watchdog should not be serviced solely in an ISR
 If main code crashes, but interrupt continues to
execute, the watchdog will not catch the crash
 Could put the 0x55 WDKEY in the main code, and the
0xAA WDKEY in an ISR; this catches main code
crashes and also ISR crashes

WDKEY Write Results

Sequential Value Written
Step to WDKEY Result

1 0xAA No action
2 0xAA No action
3 0x55 WD counter enabled for reset on next AAh write
4 0x55 WD counter enabled for reset on next AAh write
5 0x55 WD counter enabled for reset on next AAh write
6 0xAA WD counter is reset
7 0xAA No action
8 0x55 WD counter enabled for reset on next AAh write
9 0xAA WD counter is reset
10 0x55 WD counter enabled for reset on next AAh write
11 0x23 No effect; WD counter not reset on next AAh write
12 0xAA No action due to previous invalid value
13 0x55 WD counter enabled for reset on next AAh write
14 0xAA WD counter is reset

TMS320F28004x Microcontroller Workshop - System Initialization 5-9

General Purpose Digital I/O

General Purpose Digital I/O

GPIO Grouping Overview
GPIO Port A Group GPIO Port A Mux1
Mux1 Register Register
(GPAGMUX1) (GPAMUX1) Input
GPIO Port A Qual

GPIO Port A
[GPIO 0 to 15] [GPIO 0 to 15]
Direction Register
(GPADIR)
GPIO Port A Group GPIO Port A Mux2 [GPIO 0 to 31]
Mux2 Register Register
(GPAGMUX2) (GPAMUX2)
[GPIO 16 to 31] [GPIO 16 to 31]
Internal Bus

GPIO Port B Group GPIO Port B Mux1

Mux1 Register Register
(GPBGMUX1) (GPBMUX1) Input
GPIO Port B Qual

GPIO Port B
[GPIO 32 to 47] [GPIO 32 to 47]
Direction Register
(GPBDIR)
GPIO Port B Group GPIO Port B Mux2 [GPIO 32 to 63]
Mux2 Register Register
(GPBGMUX2) (GPBMUX2)
[GPIO 48 to 63] [GPIO 48 to 63]

Analog
Input Input

Port H
[GPIO 224 to 255]
Inverter Qual

The F28004x device incorporates a multiplexing scheme to enable each I/O pin to be configured
as a GPIO pin or one of several peripheral I/O signals. Sharing a pin across multiple functions
maximizes application flexibility while minimizing package size and cost. A GPIO Group
multiplexer and four GPIO Index multiplexers provide a double layer of multiplexing to allow up to
twelve independent peripheral signals and a digital I/O function to share a single pin. Each output
pin can be controlled by either a peripheral or either the CPU or CLA. By default, all of the pins
are configured as GPIO, and when configured as a signal input pin, a qualification sampling
period can be specified to remove unwanted noise. Optionally, each pin has an internal pullup
resistor that can be enabled in order to keep the input pin in a known state when no external
signal is driving the pin. The GPIO pins are grouped into two ports (Port A and Port B), and each
port has 32 pins. For a GPIO, each port has a series of registers that are used to control the
value on the pins, and within these registers each bit corresponds to one GPIO pin. Additionally,
Analog Port H is an input ony which has input qualification capability.

If the pin is configured as GPIO, a direction (DIR) register is used to specify the pin as either an
input or output. By default, all GPIO pins are inputs. The current state of a GPIO pin
corresponds to a bit value in a data (DAT) register, regardless if the pin is configured as GPIO or
a peripheral function. Writing to the DAT register bit field clears or sets the corresponding output
latch, and if the pin is configured as an output the pin will be driven either low or high. The state
of various GPIO output pins on the same port can be easily modified using the SET, CLEAR, and
TOGGLE registers. The advantage of using these registers is a single instruction can be used to
modify only the pins specified without disturbing the other pins. This also eliminates any timing
issues that may occur when writing directly to the data registers.

5 - 10 TMS320F28004x Microcontroller Workshop - System Initialization

 General Purpose Digital I/O

GPIO Pin Block Diagram

CLA CPU Input 00:00 unused
GPyDAT(R) GPyDAT(R) X-BAR 00:01 Peripheral 1
00:10 Peripheral 2
00:11 Peripheral 3
Input 01:00 unused
Qualification 01:01 Peripheral 5
CPU 01:10 Peripheral 6
GPyQSEL1/2 GPyCSEL1-4 01:11 Peripheral 7
0 1
GPyCTRL GPyDAT(W))
GPyDAT(W
CPU CPU 00 10:xx Peripherals 9-11
GPySET
GPySET CLA 01
GPyINV GPyCLEAR reserved 10 11:xx
GPyCLEAR Peripherals 13-15
CPU GPyTOGGLE reserved 11
GPyTOGGLE

CPU CPU 00:00 GPIO

GPyDIR GPyODR 00:01 Peripheral 1
0 = Input 0 = Normal 00:10 Peripheral 2 GPyG:GPy
1 = Output 1 = Open Drain 00:11 Peripheral 3
GPyGMUX1/2
01:00 GPIO GPyMUX1/2
01:01 Peripheral 5 CPU
01:10 Peripheral 6
GPyPUD Internal Pull-Up 01:11 Peripheral 7
CPU 0 = enable 10:xx GPIO & Peripherals 9-11
1 = disable
Pin (default GPIO 0-xx) 11:xx GPIO & Peripherals 13-15
y = A or B

Configuring GPIO Pins

Configuring GPIO Pins using Driverlib
 Configure peripheral multiplexing
GPIO_setPinConfig(pinConfig);
 pinConfig is defined in pin_map.h (GPIO_#_value)
 Configure pin properties
GPIO_setPadConfig(pin, pinType);
 pin is the GPIO pin number
 pinType can be the following values:
 GPIO_PIN_TYPE_STD
 GPIO_PIN_TYPE_PULLUP
 GPIO_PIN_TYPE_OD
 GPIO_PIN_TYPE_INVERT
 INVERT may be OR-ed with STD or PULLUP
 Set direction for pins configured as GPIO
GPIO_setDirectionMode(pin, pinIO);
 pin is the GPIO pin number
 pinIO can be following values:
 GPIO_DIR_MODE_IN
 GPIO_DIR_MODE_OUT

The input qualification scheme is very flexible, and the type of input qualification can be
configured for each GPIO pin individually. In the case of a GPIO input pin, the qualification can
be specified as only synchronize to SYSCLKOUT or qualification by a sampling window. For pins

TMS320F28004x Microcontroller Workshop - System Initialization 5 - 11

General Purpose Digital I/O

that are configured as peripheral inputs, the input can also be asynchronous in addition to
synchronized to SYSCLKOUT or qualified by a sampling window.

GPIO Input Qualification

Input to GPIO and

pin peripheral
Qualification modules

SYSCLK

 Input qualification available on

ports A, B, and H
 Individually selectable per pin samples taken
 no qualification (peripherals only)
 sync to SYSCLK only
 qualify 3 samples
 qualify 6 samples
 QUALPRD = SYSCLKOUT/n T T T
 where n can be 1 or an even value
between 2 and 510 inclusive T = qual period

Input Qualification Driverlib Functions

 Qualification Mode
GPIO_setQualificationMode(pin, qualification);
 pin is the GPIO pin number
 qualification values are:
 GPIO_QUAL_SYNC
 GPIO_QUAL_3SAMPLE
 GPIO_QUAL_6SAMPLE
 GPIO_QUAL_ASYNC

 Qualification Period
GPIO_setQualificationPeriod(pin, divider);
 pin is the GPIO pin number
 divider is the value by which the frequency of SYSCLKOUT is divided
and it can be 1 or an even value between 2 and 510 inclusive

5 - 12 TMS320F28004x Microcontroller Workshop - System Initialization

 General Purpose Digital I/O

GPIO Core Select

 Selects which core’s GPIODAT/SET/CLEAR/TOGGLE
registers are used to control a pin
 Each pin individually controlled
31 0 31 0 31 0 31 0

GPxCSEL4 GPxCSEL3 GPxCSEL2 GPxCSEL1

A: GPIO31-24 GPIO23-16 GPIO15-8 GPIO7-0
B: GPIO63-56 GPIO55-48 GPIO47-40 GPIO39-32

 Driverlib function used to select core:

GPIO_setMasterCore(pin, core);
 pin is the GPIO pin number
 core parameter values:
 GPIO_CORE_CPU1
 GPIO_CORE_CPU1_CLA1

Driverlib GPIO Data Control Functions

 Pin Functions
GPIO_readPin(pin);
GPIO_writePin(pin, outVal);
GPIO_togglePin(pin);
 pin is the GPIO pin number
 outVal parameter is the value written to the pin

 Port Functions
GPIO_readPortData(port);
GPIO_writePortData(port, outVal);
GPIO_setPortPins(port, pinMask);
GPIO_clearPortPins(port, pinMask);
GPIO_togglePortPins(port, pinMask);
 port is the GPIO port: GPIO_PORT_x where x is the port letter
 outVal parameter is bit-packed value (32 pins) written to the port
 pinMask parameter is a bit-packed value (32 pins) masking the port

TMS320F28004x Microcontroller Workshop - System Initialization 5 - 13

General Purpose Digital I/O

GPIO Input X-Bar

GPIO Input X-BAR

The Input X-BAR is used to route external GPIO signals into the device. It has access to every
GPIO pin, where each signal can be routed to any or multiple destinations which include the
ADCs, eCAPs, ePWMs, Output X-BAR, and external interrupts. This provides additional flexibility
above the multiplexing scheme used by the GPIO structure. Since the GPIO does not affect the
Input X-BAR, it is possible to route the output of one peripheral to another, such as measuring the
output of an ePWM with an eCAP for frequency testing.

5 - 14 TMS320F28004x Microcontroller Workshop - System Initialization

 General Purpose Digital I/O

GPIO Input X-BAR Architecture

GPIO 0 This block
INPUTx diagram is
replicated
GPIO n 16 times

XBAR_setInputPin(input, pin);
input Destinations (pin is the GPIO pin number)
XBAR_INPUT1 eCAPx, ePWM X-BAR, ePWM[TZ1, TRIP1], Output X-BAR
XBAR_INPUT2 eCAPx, ePWM X-BAR, ePWM[TZ2, TRIP2], Output X-BAR
XBAR_INPUT3 eCAPx, ePWM X-BAR, ePWM[TZ3, TRIP3], Output X-BAR
XBAR_INPUT4 eCAPx, ePWM X-BAR, XINT1, Output X-BAR
XBAR_INPUT5 eCAPx, ePWM X-BAR, XINT2, ADCEXTSOC, EXTSYNCIN1, Output X-BAR
XBAR_INPUT6 eCAPx, ePWM X-BAR, XINT3, ePWM[TRIP6], EXTSYNCIN2, Output X-BAR
XBAR_INPUT7 eCAPx, ePWM X-BAR
XBAR_INPUT8 eCAPx, ePWM X-BAR
XBAR_INPUT9 eCAPx, ePWM X-BAR
XBAR_INPUT10 eCAPx, ePWM X-BAR
XBAR_INPUT11 eCAPx, ePWM X-BAR
XBAR_INPUT12 eCAPx, ePWM X-BAR
XBAR_INPUT13 eCAPx, ePWM X-BAR, XINT4
XBAR_INPUT14 eCAPx, ePWM X-BAR, XINT5
XBAR_INPUT15 eCAPx
XBAR_INPUT16 eCAPx

GPIO Output X-Bar

GPIO Output X-BAR

The Output X-BAR is used to route various internal signals out of the device. It contains eight
outputs that are routed to the GPIO structure, where each output has one or multiple assigned pin
positions, which are labeled as OUTPUTXBARx. Additionally, the Output X-BAR can select a
single signal or logically OR up to 32 signals.

TMS320F28004x Microcontroller Workshop - System Initialization 5 - 15

General Purpose Digital I/O

GPIO Output X-BAR Architecture

0.0 XBAR_enableOutputMux(output, muxes);
0.1 0
0.2
0.3 XBAR_setOutputLatchMode(output, enable);
This block 1.0
diagram is 1.1 1
replicated 1.2
1.3 OUTPUTx
8 times
Latch
Muxed with
31.0 Peripheral
31.1 31 GPIO Pins
31.2
31.3 XBAR_invertOutputSignal(output, invert);
XBAR_setOutputMuxConfig(output, muxConfig);
MUX 0 1 2 3 MUX 0 1 2 3
0 CMPSS1.CTRIPOUTH CMPSS1.CTRIPOUTH_OR_CTRIPOUTL ADCAEVT1 ECAP1OUT 16 SD1FLT1.COMPH SD1FLT1.COMPH_OR_COMPL
1 CMPSS1.CTRIPOUTL INPUTXBAR1 ADCCEVT1 17 SD1FLT1.COMPL CLAHALT
2 CMPSS2.CTRIPOUTH CMPSS2.CTRIPOUTH_OR_CTRIPOUTL ADCAEVT2 ECAP2OUT 18 SD1FLT2.COMPH SD1FLT2.COMPH_OR_COMPL
3 CMPSS2.CTRIPOUTL INPUTXBAR2 ADCCEVT2 19 SD1FLT2.COMPL
4 CMPSS3.CTRIPOUTH CMPSS3.CTRIPOUTH_OR_CTRIPOUTL ADCAEVT3 ECAP3OUT 20 SD1FLT3.COMPH SD1FLT3.COMPH_OR_COMPL
5 CMPSS3.CTRIPOUTL INPUTXBAR3 ADCCEVT3 21 SD1FLT3.COMPL
6 CMPSS4.CTRIPOUTH CMPSS4.CTRIPOUTH_OR_CTRIPOUTL ADCAEVT4 ECAP4OUT 22 SD1FLT4.COMPH SD1FLT4.COMPH_OR_COMPL
7 CMPSS4.CTRIPOUTL INPUTXBAR4 ADCCEVT4 23 SD1FLT4.COMPL
8 CMPSS5.CTRIPOUTH CMPSS5.CTRIPOUTH_OR_CTRIPOUTL ADCBEVT1 ECAP5OUT 24
9 CMPSS5.CTRIPOUTL INPUTXBAR5 25
10 CMPSS6.CTRIPOUTH CMPSS6.CTRIPOUTH_OR_CTRIPOUTL ADCBEVT2 ECAP6OUT 26
11 CMPSS6.CTRIPOUTL INPUTXBAR6 27
12 CMPSS7.CTRIPOUTH CMPSS7.CTRIPOUTH_OR_CTRIPOUTL ADCBEVT3 ECAP7OUT 28
13 CMPSS7.CTRIPOUTL ADCSOCAO 29
14 ADCBEVT4 EXTSYNCOUT 30
15 ADCSOCBO 31

5 - 16 TMS320F28004x Microcontroller Workshop - System Initialization

 External Interrupts

External Interrupts
External Interrupts
5 external interrupt signals
 XINT1, XINT2, XINT3, XINT4 and XINT5
 Each external interrupt can be mapped to any of
the GPIO pins via the X-BAR Input architecture
 XINT1-5 are sources for Input X-BAR signals 4, 5, 6,
13, and 14 respectively
 XINT1, XINT2, and XINT3 also have a free-
running 16-bit counter which measures the
elapsed time between interrupts
 Counter resets to zero each time the interrupt occurs
 Driverlib function used to read counter value:
GPIO_getInterruptCounter(extIntNum);
 extIntNum parameter is: GPIO_INT_XINTx (x = 1, 2, or 3)

Configuring External Interrupts

 Configuring external interrupts is a multi-step process:
 Select GPIO pin, set polarity, and enable interrupt

GPIO_setInterruptPin(pin, extIntNum);
GPIO_setInterruptType(extIntNum, intType);
GPIO_[enable|disable]Interrupt(extIntNum);
 pin is the GPIO pin number
 extIntNum parameter specifies the external interrupt
 GPIO_INT_XINT1
 GPIO_INT_XINT2
 GPIO_INT_XINT3
 GPIO_INT_XINT4
 GPIO_INT_XINT5
 intType parameter specifies the type of interrupt trigger
 GPIO_INT_TYPE_FALLING_EDGE
 GPIO_INT_TYPE_RISING_EDGE
 GPIO_INT_TYPE_BOTH_EDGES

TMS320F28004x Microcontroller Workshop - System Initialization 5 - 17

Low Power Modes

Low Power Modes

Low Power Modes

Low Power CPU Peripheral Watchdog PLL INTOSC XTAL

Mode Logic Logic Clock 1/2
Clock Clock
Normal Run on on on on on on
IDLE off on on on on on
HALT off off off off on on

 HALT
 INTOSC – not automatically powered down; software
configurable
 XTAL – can be powered down by software at any time
 STANDBY is not supported but can be emulated – see
device Technical Reference Manual
 See device data sheet for each low power mode
power consumption

Low Power Mode Exit

Exit
Interrupt GPIO Any
Watchdog
Reset 0 - 63 Enabled
Interrupt
Low Power Signal Interrupt
Mode

IDLE yes no yes yes

HALT yes yes no / yes no

5 - 18 TMS320F28004x Microcontroller Workshop - System Initialization

 Low Power Modes

Low Power Mode Driverlib Functions

 Configuring low power mode
SysCtl_enterIdleMode(); //enter IDLE mode
SysCtl_enterHaltMode(); //enter HALT mode

 Set pin to wake up device from HALT mode

SysCtl_enableLPMWakeupPin(pin);
SysCtl_disableLPMWakeupPin(pin);
 pin is the GPIO pin number (numerical value 0-63)

 Run watchdog while in HALT mode

SysCtl_enableWatchdogInHalt();
SysCtl_disableWatchdogInHalt();

TMS320F28004x Microcontroller Workshop - System Initialization 5 - 19

Register Protection

Register Protection
LOCK Protection Registers
 “LOCK” registers protects several system configuration
registers from spurious CPU writes
 Once the LOCK Driverlib functions are set the respective
locked registers can no longer be modified by software:
ASysCtl_lockTemperatureSensor ASysCtl_lockCMPHNMux PGA_lockRegisters
ASysCtl_lockANAREF ASysCtl_lockCMPLNMux SysCtl_lockAccessControlRegs
ASysCtl_lockVMON ASysCtl_lockVREG SysCtl_lockSyncSelect
ASysCtl_lockDCDC DAC_lockRegister XBAR_lockInput
ASysCtl_lockPGAADCINMux EPWM_lockRegisters XBAR_lockOutput
ASysCtl_lockCMPHPMux HRPWM_lockRegisters XBAR_lockEPWM
ASysCtl_lockCMPLPMux MemCfg_commitConfig

 The following Driverlib functions can be locked/unlocked:

FSI_lockTxCtrl GPIO_lockPortConfig MemCfg_lockConfig
FSI_lockRxCtrl GPIO_unlockPortConfig MemCfg_unlockConfig
SysCtl_lockExtADCSOCSelect

A series of “lock” registers can be used to protect several system configuration settings from
spurious CPU writes. After the lock registers bits are set, the respective locked registers can no
longer be modified by software. However, some registers have lock/unlock capability.

EALLOW Protection (1 of 2)

 EALLOW stands for Emulation Allow

 Code access to protected registers allowed
only when EALLOW = 1 in the ST1 register
 The emulator can always access protected
registers
 EALLOW bit controlled by assembly level
instructions
 ‘EALLOW’ sets the bit (register access enabled)
 ‘EDIS’ clears the bit (register access disabled)

 EALLOW bit cleared upon ISR entry, restored

upon exit

5 - 20 TMS320F28004x Microcontroller Workshop - System Initialization

 Register Protection

EALLOW Protection (2 of 2)
 Driverlib functions automatically take care of
EALLOW and EDIS protection
 The following registers are protected:
Device Configuration & Emulation
Flash
Code Security Module
PIE Vector Table
DMA, CLA, SD, EMIF, X-Bar (some registers)
CANA/B (control registers only; mailbox RAM not protected)
ePWM, CMPSS, ADC, DAC (some registers)
GPIO (control registers only)
System Control
See device data sheet and Technical Reference Manual for detailed listings

TMS320F28004x Microcontroller Workshop - System Initialization 5 - 21

Lab 5: System Initialization

Lab 5: System Initialization

 Objective
The objective of this lab exercise is to perform the processor system initialization. Additionally,
the peripheral interrupt expansion (PIE) vectors will be initialized and tested using the information
discussed in the previous module. This initialization process will be used again in all of the lab
exercises throughout this workshop.

The first part of the lab exercise will setup the system initialization and test the watchdog
operation by having the watchdog cause a reset. In the second part of the lab exercise the
interrupt process will be tested by using the watchdog to generate an interrupt. This lab will make
use of the F28004x Driver Library (Driverlib) to simplify the programming of the device. Please
review these files, and make use of them in the future, as needed.

 Procedure

Create a New Project

1. Create a new project (File  New  CCS Project) for this lab exercise. The top
section should default to the options previously selected (setting the “Target” to
“TMS320F280049C”, and leaving the “Connection” box blank). Name the project Lab5.
Uncheck the “Use default location” box. Using the “Browse…” button navigate to:
C:\F28004x\Labs\Lab5\project then click Select Folder. Set the “Linker
Command File” to <none>, and be sure to set the “Project templates and examples” to
“Empty Project”. Then click Finish.

2. Right-click on Lab5 in the Project Explorer window and add (copy) the following files to
the project (Add Files…) from C:\F28004x\Labs\Lab5\source:

CodeStartBranch.asm Lab_5_6_7.cmd
DefaultIsr_5.c Main_5.c
device.c Watchdog_5.c
Gpio.c

Project Build Options

3. Setup the build options by right-clicking on Lab5 in the Project Explorer window and
select “Properties”. We need to setup the include search path to include the Driverlib
files and common lab header files. Under “C2000 Compiler” select “Include Options”. In
the include search path box that opens (“Add dir to #include search path”)
click the Add icon (first icon with green plus sign). Then in the “Add directory path”
window type (one at a time):
${PROJECT_ROOT}/../../f28004x_driverlib/driverlib

${PROJECT_ROOT}/../../f28004x_driverlib/driverlib/inc

${PROJECT_ROOT}/../../Lab_common/include

Click OK to include each search path.

4. Next, we need to setup the file search path for Driverlib. Under “C2000 Linker” select
“File Search Path”. The file search path box will open and in the include library file
section (“Include library file or command file as input”) click the Add
icon. Then in the “Add file path” window type:

5 - 22 TMS320F28004x Microcontroller Workshop - System Initialization

 Lab 5: System Initialization

driverlib.lib
and click OK. Then in the library search path section (“Add <dir> to library
search path”) click the Add icon. In the “Add directory path” window type:
${PROJECT_ROOT}/../../f28004x_driverlib/driverlib/ccs/Debug
and click OK.
5. Now, we need to setup the predefined symbols. Under “C2000 Compiler” select
“Predefined Symbols”. In the predefined name box that opens (“Pre-define NAME”)
click the Add icon. Then in the “Enter Value” window type _LAUNCHXL_F280049C.
This name is used in the project to conditionally include #defines for pin numbers and
other GPIO configuration code specific to the LaunchPad (rather than the controlCARD).
This conditional code is located in the device.h file. Click OK to include the name.
Finally, click Apply and Close to save and close the Properties window.

Memory Configuration
6. Open and inspect the linker command file Lab_5_6_7.cmd. Notice that the user defined
section “codestart” is being linked to a memory block named BEGIN_M0. The
codestart section contains code that branches to the code entry point of the project. The
bootloader must branch to the codestart section at the end of the boot process. Recall
that the emulation boot mode "RAM" branches to address 0x000000 upon bootloader
completion.

Notice that the linker command file Lab_5_6_7.cmd has a memory block named
BEGIN_M0: origin = 0x000000, length = 0x0002, in program memory. The
existing parts of memory blocks BOOT_RSVD and RAMM0 in data memory has been
modified to avoid any overlaps with this memory block.

7. In the linker command file, notice that RESET in the MEMORY section has been defined
using the “(R)” qualifier. This qualifier indicates read-only memory, and is optional. It will
cause the linker to flag a warning if any uninitialized sections are linked to this memory.
The (R) qualifier can be used with all non-volatile memories (e.g., flash, ROM, OTP), as
you will see in later lab exercises. Close the Lab_5_6_7.cmd linker command file.

System Initialization
8. Open and inspect main_5.c. Notice the Device_init() function call to device.c for
initializing the device.
9. Open Watchdog_5.c and edit the file to configure the watchdog for generating a reset.
Also, edit the file to disable the watchdog. Make the modifications to the file at the
appropriate locations in the code. Save your work.
10. Open and inspect Gpio.c. Notice the Driverlib functions that are being used to
configure the GPIO pins. Also, notice the input X-BAR configuration. This file will be
used in the remaining lab exercises.

Build and Load

11. Click the “Build” button and watch the tools run in the Console window. Check for
errors in the Problems window.
12. Click the “Debug” button (green bug). The CCS Debug perspective view should open,
the program will load automatically, and you should now be at the start of main().

TMS320F28004x Microcontroller Workshop - System Initialization 5 - 23

Lab 5: System Initialization

13. After CCS loaded the program in the previous step, it set the program counter (PC) to
point to _c_int00. It then ran through the C-environment initialization routine in the
rts2800_fpu32.lib and stopped at the start of main(). CCS did not do a device reset, and
as a result the bootloader was bypassed.
In the remaining parts of this lab exercise, the device will be undergoing a reset due to
the watchdog timer. Therefore, we must configure the device by loading values into
EMU_KEY and EMU BMODE so the bootloader will jump to “RAMM0” at address
0x000000. Set the bootloader mode using the menu bar by clicking:
Scripts  EMU Boot Mode Select  EMU_BOOT_RAM
If the device is power cycled between lab exercises, or within a lab exercise, be sure to
re-configure the boot mode to EMU_BOOT_RAM.

Run the Code – Watchdog Reset Disabled

14. Place the cursor in the “main loop” section (on the asm(“ NOP”); instruction line) and
right click the mouse key and select Run To Line. This is the same as setting a
breakpoint on the selected line, running to that breakpoint, and then removing the
breakpoint.

15. Place the cursor on the first line of code in main() and set a breakpoint by double clicking
in the line number field to the left of the code line. Notice that line is highlighted with a
blue dot indicating that the breakpoint has been set. (Alternatively, you can set a
breakpoint on the line by right-clicking the mouse and selecting Breakpoint (Code
Composer Studio)  Breakpoint). The breakpoint is set to prove that the
watchdog is disabled. If the watchdog causes a reset, code execution will stop at this
breakpoint (or become trapped as explained in the watchdog hardware reset below).

16. Run your code for a few seconds by using the “Resume” button on the toolbar , or by
using Run  Resume on the menu bar (or F8 key). After a few seconds halt your code
by using the “Suspend” button on the toolbar , or by using Run  Suspend on the
menu bar (or Alt-F8 key). Where did your code stop? Are the results as expected? If
things went as expected, your code should be in the “main loop”.

Run the Code – Watchdog Reset Enabled

17. Open the Project Explorer window in the CCS Debug perspective view by selecting View
 Project Explorer. Modify the Watchdog_5.c Driverlib function to enable the
watchdog. This will enable the watchdog to function and cause a reset. Save the file.

18. Build the project by clicking Project  Build Project. Select Yes to “Reload the
program automatically”.

Alternatively, you can add the “Build” button to the tool bar in the CCS Debug
perspective (if it is not already there) so that it will available for future use. Click Window
 Perspective  Customize Perspective… and then select the Tool Bar
Visibility tab. Check the Code Composer Studio Project Build box. This will automatically
select the “Build” button in the Tool Bar Visibility tab. Click OK.

19. Again, place the cursor in the “main loop” section (on the asm(“ NOP”); instruction line)
and right click the mouse key and select Run To Line.

20. This time we will have the watchdog issue a reset that will toggle the XRSn pin (i.e.
perform a hardware reset). Now run your code. Where did your code stop? Are the

5 - 24 TMS320F28004x Microcontroller Workshop - System Initialization

 Lab 5: System Initialization

results as expected? If things went as expected, your code should have stopped at the
breakpoint. What happened is as follows. While the code was running, the watchdog
timed out and reset the processor. The reset vector was then fetched and the ROM
bootloader began execution. Since the device is in emulation boot mode (i.e. the
emulator is connected) the bootloader read the EMU_KEY and EMU_BMODE values
from the PIE RAM. These values were previously set for boot to RAMM0 boot mode by
CCS. Since these values did not change and are not affected by reset, the bootloader
transferred execution to the beginning of our code at address 0x000000 in the RAMM0,
and execution continued until the breakpoint was hit in main( ).

Configure Watchdog Interrupt

The first part of this lab exercise used the watchdog to generate a CPU reset. This was
tested using a breakpoint set at the beginning of main(). Next, we are going to use the
watchdog to generate an interrupt. This part will demonstrate the interrupt concepts learned
in the previous module.

21. In Main_5.c notice the two function calls to interrupt.c for initializing the PIE
registers and PIE vectors:
Interrupt_initModule();
Interrupt_initVectorTable();

22. Modify main()to enable global interrupts at the appropriate location in the code.

23. In Watchdog_5.c modify the Driverlib function to cause the watchdog to generate an
interrupt rather than a reset.

24. Using the “PIE Interrupt Assignment Table” shown in the previous module find the
location for the watchdog interrupt “INT_WAKE” and fill in the following information:

PIE group #: # within group:

This will be used in the next step.

25. Next modify Watchdog_5.c at the appropriate locations in the code as follows:
• Add the Driverlib function to re-map the watchdog interrupt signal to call the ISR
function. (Hint: #define name in driverlib/inc/hw_ints.h and label name
in DefaultIsr_5.c)
• Add the Driverlib function to enable the appropriate PIEIER and core IER

26. Save all changes to the files.

27. Inspect DefaultIsr_5.c. This file contains interrupt service routines. The ISR for
WAKE interrupt has been trapped by an emulation breakpoint contained in an inline
assembly statement using “ESTOP0”. This gives the same results as placing a
breakpoint in the ISR. We will run the lab exercise as before, except this time the
watchdog will generate an interrupt. If the registers have been configured properly, the
code will be trapped in the ISR.

Build and Load

28. Build the project by clicking Project  Build Project, or by clicking on the
“Build” button (if it has been added to the tool bar). Select Yes to “Reload the program
automatically”.

TMS320F28004x Microcontroller Workshop - System Initialization 5 - 25

Lab 5: System Initialization

Run the Code – Watchdog Interrupt

29. Place the cursor in the “main loop” section, right click the mouse key and select Run To
Line.

30. Run your code. Where did your code stop? Are the results as expected? If things went
as expected, your code should stop at the “ESTOP0” instruction in the wakeISR().

Terminate Debug Session and Close Project

31. Terminate the active debug session using the Terminate button. This will close the
debugger and return Code Composer Studio to the CCS Edit perspective view.

32. Next, close the project by right-clicking on Lab5 in the Project Explorer window and
select Close Project.

End of Exercise

Note: By default, the watchdog timer is enabled out of reset. Code in the file
CodeStartBranch.asm has been configured to disable the watchdog. This can be
important for large C code projects. During this lab exercise, the watchdog was actually
re-enabled (or disabled again) in the file Watchdog_5.c.

5 - 26 TMS320F28004x Microcontroller Workshop - System Initialization

 Analog Subsystem
Introduction
The Analog Subsystem consists of the Analog-to-Digital Converter (ADC), Comparator
Subsystem (CMPSS), Programmable Gain Amplifier (PGA), Digital-to-Analog Converter (DAC),
and the Analog Subsystem Interconnect. This module will explain the operation of each
subsystem. The lab exercise will use the ADC to perform data acquisition.

Module Objectives
Module Objectives
 Understand the operation of the:
 Analog-to-Digital Converter (ADC)

 Comparator Subsystem (CMPSS)

 Programmable Gain Amplifier (PGA)

 Digital-to-Analog Converter (DAC)

 Analog Subsystem Interconnect

 Use the ADC to perform data acquisition

Analog Subsystem:
• Three 12-Bit Analog-to-Digital Converters (ADCs)
o 3.45 MSPS each (up to 10.35 MSPS per system)
o Selectable internal reference of 2.5v or 3.3v
o Ratiometric external reference set by VREFHI/VREFLO
• Seven Comparator Subsystems (CMPSS)
o Each contains:
 Two analog comparators
 Two programmable 12-bit reference DACs
 One ramp generator and Two digital glitch filter
• Seven Programmable Gain Amplifiers (PGAs)
o Each features:
 Four programmable gain modes: 3x, 6x, 12x, 24x
 Programmable output filtering
• Two 12-bit Buffered Digital-to-Analog Converter Outputs (DACs)
o Selectable reference voltage

TMS320F28004x Microcontroller Workshop - Analog Subsystem 6-1

Analog-to-Digital Converter (ADC)

Chapter Topics
Analog Subsystem ...................................................................................................................... 6-1
Analog-to-Digital Converter (ADC) ............................................................................................ 6-3
ADC Module Block Diagram ................................................................................................. 6-3
ADC Triggering ..................................................................................................................... 6-5
ADC Conversion Priority ....................................................................................................... 6-7
Post Processing Block ........................................................................................................ 6-10
ADC Clocking Flow ............................................................................................................. 6-12
ADC Timing ......................................................................................................................... 6-13
ADC Conversion Result Registers ...................................................................................... 6-13
Signed Input Voltages ......................................................................................................... 6-14
Built-In ADC Calibration ...................................................................................................... 6-14
Analog Subsystem External Reference .............................................................................. 6-15
Comparator Subsystem (CMPSS) .......................................................................................... 6-16
Comparator Subsystem Block Diagram .............................................................................. 6-17
Programmable Gain Amplifier (PGA) ...................................................................................... 6-18
PGA Block Diagram ............................................................................................................ 6-18
Digital-to-Analog Converter (DAC) .......................................................................................... 6-19
Buffered DAC Block Diagram.............................................................................................. 6-20
Analog Subsystem Interconnect ............................................................................................. 6-21
Analog Group Connections ................................................................................................. 6-22
Analog Group Connection – Example ................................................................................. 6-23
Lab 6: Analog-to-Digital Converter.......................................................................................... 6-25

6-2 TMS320F28004x Microcontroller Workshop - Analog Subsystem

 Analog-to-Digital Converter (ADC)

Analog-to-Digital Converter (ADC)

The F28004x includes three independent high-performance ADC modules. Each ADC module
has a single sample-and-hold (S/H) circuit and using multiple ADC modules enables
simultaneous sampling or independent operation (sequential sampling). The ADC module is
implemented using a successive approximation (SAR) type ADC with a resolution of 12-bits and a
performance of 3.45 MSPS, yielding up to 10.35 MSPS for the device.

ADC Module Block Diagram

ADC Module Block Diagram
ADCIN0

Post Processing
ADCRESULT0
ADCIN1
ADCIN2 ADCRESULT1

Blocks
12-bit Result
ADCIN3 S/H ADCRESULT2
MUX A/D MUX
Converter
ADCIN14 SOCx ADCRESULT15
ADCIN15
ADC full-scale ADC ADC
input range is CHSEL EOCx ADCINT1-4
Generation Interrupt
VREFLO to VREFHI Logic Logic
SOCx Signal ADCINT1
ADCINT2
SOC0 TRIGSEL CHSEL ACQPS
SOCx Triggers

SOC1 TRIGSEL CHSEL ACQPS

SOC2 TRIGSEL CHSEL ACQPS Software
SOC3 TRIGSEL CHSEL ACQPS CPU1 Timer (0,1,2)
EPWMxSOCA/C (x = 1 to 8)
EPWMxSOCB/D (x = 1 to 8)
SOC15 TRIGSEL CHSEL ACQPS External Pin(GPIO/ADCEXTSOC)
SOCx Configuration Registers

*** Multiple ADC modules allow for simultaneous sampling or independent operation ***

The ADC triggering and conversion sequencing is managed by a series of start-of-conversion

(SOCx) configuration registers. Each SOCx register configures a single channel conversion,
where the SOCx register specifies the trigger source that starts the conversion, the channel to
convert, and the acquisition sample window duration. Multiple SOCx registers can be configured
for the same trigger, channel, and/or acquisition window. Configuring multiple SOCx registers to
use the same trigger will cause that trigger to perform a sequence of conversions, and configuring
multiple SOCx registers for the same trigger and channel can be used to oversample the signal.

The various trigger sources that can be used to start an ADC conversion include the General-
Purpose Timers, the ePWM modules, an external pin, and by software. Also, the flag setting of
either ADCINT1 or ADCINT2 can be configured as a trigger source which can be used for
continuous conversion operation. The ADC interrupt logic can generate up to four interrupts.
The results for SOC 0 through 15 appear in result registers 0 through 15, respectively.

TMS320F28004x Microcontroller Workshop - Analog Subsystem 6-3

Analog-to-Digital Converter (ADC)

ADC SOCx Functional Diagram

TINT0 (CPU1 Timer 0) ADC_setupSOC(base, socNumber, trigger, channel, sampleWindow);
TINT1 (CPU1 Timer 1)
T
TINT2 (CPU1 Timer 2) r
ADCEXTSOC (GPIO) i ADCINT1
SOCA/C (ePWM1) g
Channel Sample Result ADCINT2
SOCB/D (ePWM1) g
e S Select Window Register E ADCINT3
O O ADCINT4
r C
SOCA/C (ePWM8) C
x x
SOCB/D (ePWM8)
ADC_readResult(resultBase, socNumber);

Software Trigger ADC_setInterruptSource(base, adcIntNum, socNumber);

ADC_[enable|disable]Interrupt(base, adcIntNum);
ADCINT1
ADCINT2
Re-Trigger ADC_setInterruptSOCTrigger(base, socNumber, trigger);
ADC_forceSOC(base, socNumber);

This block diagram is EOC Int Pulse: ADC_setInterruptPulseMode(base, pulseMode);

replicated 16 times (generation at beginning of conversion or one cycle prior to results)

The figure above is a conceptual view highlighting a single ADC start-of-conversion functional
flow from triggering to interrupt generation. This figure is replicated 16 times and the Driverlib
functions highlight the sections that they modify.

ADC SOC Driverlib Function

 Configure a start-of-conversion (SOC)
ADC_setupSOC(base, socNumber, trigger, channel, sampleWindow);

 base is the ADC base address: ADCx_BASE (x = A to C)

 socNumber values are:
 ADC_SOC_NUMBERx (x = 0 to 15)
 trigger values are:
 ADC_TRIGGER_SW_ONLY
 ADC_TRIGGER_CPU1_TINTx (x = 0 to 2)
 ADC_TRIGGER_GPIO
 ADC_TRIGGER_EPWMx_SOCA (x = 1 to 8)
 ADC_TRIGGER_EPWMx_SOCB (x = 1 to 8)
 channel values are:
 ADC_CH_ADCINx (x = 0 to 15)
 sampleWindow parameter is the acquisition window duration in SYSCLK
cycles: value between 1 and 512 cycles inclusive

6-4 TMS320F28004x Microcontroller Workshop - Analog Subsystem

 Analog-to-Digital Converter (ADC)

ADC Driverlib Functions

 Configure an interrupt start-of-conversion trigger
ADC_setInterruptSOCTrigger(base, socNumber, trigger);
 Set EOC source for an ADC interrupt
ADC_setInterruptSource(base, adcIntNum, socNumber);
ADC_[enable|disable]Interrupt(base, adcIntNum);
 Force an SOC conversion (software trigger)
ADC_forceSOC(base, socNumber);
 Configure ADC EOC interrupt pulse generation
ADC_setInterruptPulseMode(base, pulseMode);
 Read ADC result register
ADC_readResult(resultBase, socNumber);
 base is the ADC base address: ADCx_BASE (x = A to C)
 socNumber is: ADC_SOC_NUMBERx (x = 0 to 15)
 Trigger value is:
 ADC_INT_SOC_TRIGGER_NONE
 ADC_INT_SOC_TRIGGER_ADCINTx (x = 1 or 2)
 adcIntNum value is: ADC_INT_NUMBERx (x = 1 to 4)
 pulseMode value is: ADC_PULSE_END_OF_x (x = ACQ_WIN or CONV)
 resultBase value is: ADCxRESULT_BASE (x = A to C)

ADC Triggering
Example – ADC Triggering
Sample A1  A3  A5 when ePWM1 SOCB/D is generated and then generate ADCINT1:

SOCB/D (ETPWM1)
SOC0 Channel Sample Result0 no interrupt
A1 20 cycles
SOC1 Channel Sample
A3 26 cycles Result1 no interrupt

SOC2 Channel Sample

A5 22 cycles Result2 ADCINT1

Sample A2  A4  A6 continuously and generate ADCINT2:

Software Trigger

SOC3 Channel Sample Result3 no interrupt

A2 22 cycles
SOC4 Channel Sample
ADCINT2 A4 28 cycles Result4 no interrupt

SOC5 Channel Sample

Result5 ADCINT2
A6 24 cycles

Note: setting ADCINT2 flag does not need to generate an interrupt

The top example in the figure above shows channels A1, A3, and A5 being converted with a
trigger from EPWM1. After A5 is converted, ADCINT1 is generated. The bottom example shows
channels A2, A4, and A6 being converted initially by a software trigger. Then, after A6 is

TMS320F28004x Microcontroller Workshop - Analog Subsystem 6-5

Analog-to-Digital Converter (ADC)

converted, ADCINT2 is generated and also fed back as a trigger to start the process again.

Example – ADC Ping-Pong Triggering

Sample all channels continuously and provide Ping-Pong interrupts to CPU/system:

Software Trigger SOC0 Channel Sample

Result0 no interrupt
ADCINT2 B0 20 cycles
SOC1 Channel Sample Result1 no interrupt
B1 20 cycles
SOC2 Channel Sample
B2 20 cycles Result2 ADCINT1

ADCINT1
SOC3 Channel Sample
B3 20 cycles Result3 no interrupt

SOC4 Channel Sample no interrupt

B4 20 cycles Result4

SOC5 Channel Sample

B5 20 cycles Result5 ADCINT2

The ADC ping-pong triggering example in the figure above shows channels B0 through B5 being
converted, triggered initially by software. After channel B2 is converted, ADCINT1 is generated,
which also triggers channel B3. After channel B5 is converted, ADCINT2 is generated and is also
fed back to start the process again from the beginning. Additionally, ADCINT1 and ADCINT2 are
being used to manage the ping-pong interrupts for the interrupt service routines.

6-6 TMS320F28004x Microcontroller Workshop - Analog Subsystem

 Analog-to-Digital Converter (ADC)

ADC Conversion Priority

ADC Conversion Priority
 When multiple SOC flags are set at the same time –
priority determines the order in which they are converted
 Round Robin Priority (default)
 No SOC has an inherent higher priority than another
 Priority depends on the round robin pointer
 High Priority
 High priority SOC will interrupt the round robin wheel
after current conversion completes and insert itself as
the next conversion
 After its conversion completes, the round robin wheel
will continue where it was interrupted

 Round Robin Burst Mode

 Allows a single trigger to convert one or more SOCs in
the round robin wheel
 Uses BURSTTRIG instead of TRIGSEL for all round
robin SOCs (not high priority)

When multiple triggers are received at the same time, the ADC conversion priority determines the
order in which they are converted. Three different priority modes are supported. The default
priority mode is round robin, where no start-of-conversion has an inherently higher priority over
another, and the priority depends upon a round robin pointer. The round robin pointer operates in
a circular fashion, constantly wrapping around to the beginning. In high priority mode, one or
more than one start-of-conversion is assigned as high priority. The high priority start-of-
conversion can then interrupt the round robin wheel, and after it has been converted the wheel
will continue where it was interrupted. High priority mode is assigned first to the lower number
start-of-conversion and then in increasing numerical order. If two high priority start-of-conversion
triggers occur at the same time, the lower number will take precedence. Burst mode allows a
single trigger to convert one or more than one start-of-conversion sequentially at a time. This
mode uses a separate Burst Control register to select the burst size and trigger source.

TMS320F28004x Microcontroller Workshop - Analog Subsystem 6-7

Analog-to-Digital Converter (ADC)

Conversion Priority Functional Diagram

High Priority
SOC0
SOC1 SOC Priority
SOC2 Determines cutoff point
SOC3 for high priority and
round robin mode
SOC4
SOCPRIORITY
SOC5
SOC6 ADC_setSOCPriority(base, priMode);
SOC7
Round Robin

SOC8 RRPOINTER
SOC9
SOC10 Round Robin Pointer
SOC11 Points to the last converted
SOC12 round robin SOCx and
SOC13 determines order
of conversions
SOC14
SOC15

 base is the ADC base address: ADCx_BASE (x = A to C)

 priMode values are:
 ADC_PRI_ALL_ROUND_ROBIN
 ADC_PRI_ALL_HIPRI
 ADC_PRI_SOCx_HIPRI (x = 0 to 14)

In this conversion priority functional diagram, the Start-of-Conversion Priority Control Register
contains two bit fields. The Start-of-Conversion Priority bit fields determine the cutoff point
between high priority and round robin mode, whereas the Round-Robin Pointer bit fields contains
the last converted round robin start-of-conversion which determines the order of conversions.

Round Robin Priority Example

SOCPRIORITY configured as 0;
RRPOINTER configured as 15;
SOC0 is highest RR priority SOC
SOC
SOC 0
15 1
SOC7 trigger received SOC SOC
14 2

SOC7 is converted; SOC SOC

13 3
RRPOINTER now points to SOC7;
SOC8 is now highest RR priority
SOC SOC
12 RRPOINTER 4
SOC2 & SOC12 triggers received
simultaneously SOC SOC
11 5

SOC SOC
SOC12 is converted; 10 6
RRPOINTER points to SOC12; SOC SOC
SOC13 is now highest RR priority 9 SOC 7
8

SOC2 is converted;
RRPOINTER points to SOC2;
SOC3 is now highest RR priority

6-8 TMS320F28004x Microcontroller Workshop - Analog Subsystem

 Analog-to-Digital Converter (ADC)

High Priority Example

SOCPRIORITY configured as 4;
RRPOINTER configured as 15;
SOC4 is highest RR priority
SOC
SOC 4
SOC
SOC7 trigger received High Priority 15 5
SOC
0 SOC SOC
SOC7 is converted; 14 6
RRPOINTER points to SOC7;
SOC8 is now highest RR priority SOC
1
SOC SOC
13 RRPOINTER 7
SOC2 & SOC12 triggers received SOC
simultaneously 2

SOC SOC
SOC 12 8
SOC2 is converted; 3
RRPOINTER stays pointing to SOC7
SOC SOC
11 SOC 9
10
SOC12 is converted;
RRPOINTER points to SOC12;
SOC13 is now highest RR priority

Round Robin Burst Mode Diagram

ADC_[enable|disable]BurstMode(base);
Burst Enable
BURSTEN Disables/enables burst mode

BURSTSIZE
SOC Burst Size
Determines how many
BURSTTRIGSEL SOCs are converted per
burst trigger

Software, CPU1 Timer0-2 SOC Burst Trigger

ePWM1 ADCSOCA/C – B/D  Source Select
ePWM8 ADCSOCA/C – B/D Determines which trigger
starts a burst conversion
sequence

ADC_setBurstModeConfig(base, trigger, burstSize);

 base is the ADC base address: ADCx_BASE (x = A to C)
 trigger parameter uses the same values as the ADC_setupSOC() API
 burstSize parameter is a value between 1 and 16 inclusive

The Round-Robin Burst mode utilizes an ADC Burst Control register to enable the burst mode,
determine the burst size, and select the burst trigger source. This register is modified using the
two Driverlib functions shown in the figure.

TMS320F28004x Microcontroller Workshop - Analog Subsystem 6-9

Analog-to-Digital Converter (ADC)

Round Robin Burst Mode with High

Priority Example
SOCPRIORITY configured as 4;
RRPOINTER configured as 15;
SOC4 is highest RR priority
SOC
SOC 4
SOC
BURSTTRIG trigger received High Priority 15 5
SOC
0 SOC SOC
SOC4 & SOC5 is converted; 14 6
RRPOINTER points to SOC5;
SOC6 is now highest RR priority SOC
1
SOC SOC
13 RRPOINTER 7
BURSTTRIG & SOC1 triggers SOC
received simultaneously 2

SOC SOC
SOC 12 8
SOC1 is converted; 3
RRPOINTER stays pointing to SOC5
SOC SOC
11 SOC 9
10
SOC6 & SOC7 is converted;
RRPOINTER points to SOC7;
SOC8 is now highest RR priority

Note: BURSTEN = 1, BURSTSIZE = 1

Post Processing Block

Purpose of the Post Processing Block
 Offset Correction
 Remove an offset associated with an ADCIN channel possibly
caused by external sensors and signal sources
 Zero-overhead; saving cycles
 Error from Set-point Calculation
 Subtract out a reference value which can be used to automatically
calculate an error from a set-point or expected value
 Reduces the sample to output latency and software overhead
 Limit and Zero-Crossing Detection
 Automatically perform a check against a high/low limit or zero-
crossing and can generate a trip to the ePWM and/or an interrupt
 Decreases the sample to ePWM latency and reduces software overhead;
trip the ePWM based on an out of range ADC conversion without CPU
intervention
 Trigger-to-Sample Delay Capture
 Capable of recording the delay between when the SOC is
triggered and when it begins to be sampled
 Allows software techniques to reduce the delay error

6 - 10 TMS320F28004x Microcontroller Workshop - Analog Subsystem

 Analog-to-Digital Converter (ADC)

Post Processing Block - Diagram

Delay Capture ADCEVTSEL.PPBxTRIPLO
SOC Control Signals
SOC SOC ADCEVTSEL.PPBxTRIPHI
Trigger Start
Detect Detect ADCEVTSEL.PPBxZERO
latch latch
REQSTAMPx Σ DLYSTAMPx ADCEVTSTAT.PPBxTRIPLO

FREECOUNT
+ EVENTx
ADCEVTSTAT.PPBxTRIPHI

ADCEVTSTAT.PPBxZERO
Offset Correction
w/ Saturation
ADCPPBxOFFCAL Threshold Compare
Zero
ADC Output + - saturate
Crossing
Σ ADCRESULTy
Detect

ADCPPBxTRIPHI + INTx
Error/Bipolar Calculation
-
+ Twos
-
ADCPPBxOFFREF Σ Comp ADCPPBxRESULT
Inv +
Enable
ADCPPBxCONFIG.TWOSCOMPEN ADCPPBxTRIPLO -

ADCEVTINTSEL.PPBxZERO

ADCEVTINTSEL.PPBxTRIPHI

ADCEVTINTSEL.PPBxTRIPLO

To further enhance the capabilities of the ADC, each ADC module incorporates four post-
processing blocks (PPB), and each PPB can be linked to any of the ADC result registers. The
PPBs can be used for offset correction, calculating an error from a set-point, detecting a limit and
zero-crossing, and capturing a trigger-to-sample delay. Offset correction can simultaneously
remove an offset associated with an ADCIN channel that was possibly caused by external
sensors or signal sources with zero-overhead, thereby saving processor cycles. Error calculation
can automatically subtract out a computed error from a set-point or expected result register value,
reducing the sample to output latency and software overhead. Limit and zero-crossing detection
automatically performs a check against a high/low limit or zero-crossing and can generate a trip
to the ePWM and/or generate an interrupt. This lowers the sample to ePWM latency and reduces
software overhead. Also, it can trip the ePWM based on an out-of-range ADC conversion without
any CPU intervention which is useful for safety conscious applications. Sample delay capture
records the delay between when the SOCx is triggered and when it begins to be sampled. This
can enable software techniques to be used for reducing the delay error.

TMS320F28004x Microcontroller Workshop - Analog Subsystem 6 - 11

Analog-to-Digital Converter (ADC)

Post Processing Block Interrupt Event

 Each ADC module contains four Post Processing Blocks
 Each Post Processing Block can be associated with any
of the 16 ADCRESULTx registers

Post Processing Block 1

EVENTx ADCEVT1
INTx

Post Processing Block 2

EVENTx ADCEVT2
INTx

ADCEVTINT
Post Processing Block 3
EVENTx ADCEVT3
INTx

Post Processing Block 4

EVENTx ADCEVT4
INTx

ADC Clocking Flow

ADC Clocking Flow
SysCtl_setClock(SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(10) | SYSCTL_FMULT_NONE |
SYSCTL_SYSDIV(2) | SYSCTL_PLL_ENABLE );
XTAL PLLCLK SYSCLK
(20 MHz) IMULT/FMULT (200 MHz) SYSCLKDIV (100 MHz)
(x10.00) (/2) To CPU

SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCA);

PRESCALE ADCCLK (50 MHz) To ADC core

(/2)
ADC_setPrescaler(ADCA_BASE, ADC_CLK_DIV_2_0);
sampling
ACQPS window
(7+1)
ADC_setupSOC(…, …, …, …, 8);
sampling window = (ACQPS + 1)*(1/SYSCLK)

6 - 12 TMS320F28004x Microcontroller Workshop - Analog Subsystem

 Analog-to-Digital Converter (ADC)

ADC Timing
ADC Timing
 SYSCLK = 100 MHz (10 ns period)
 ADCCLK = 50 MHz (20 ns period)

Latch Sample Convert Write

2 cycles 8 cycles 10.5 ADCCLK cycles = 21 SYSCLK cycles 2 cycles

ADCINTCYCLE
Generate Early Generate Late
Interrupt Interrupt

SYSCLK ADCCLK

 Sample + Hold (sampling window) time = 80 ns

 Conversion time = 210 ns
 Sampling rate = 80 ns + 210 ns = 290 ns  3.45 MSPS
 Above timing using ADCINTCYCLE = 0 (default)
Maximum Sample Rate: 3.45 MSPS – see data sheet for details

ADC Conversion Result Registers

ADC Conversion Result Registers
ADC_readResult(resultBase, socNumber);
MSB LSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADCINx Digital AdcnResultRegs.

Voltage Results ADCRESULTx
3.3 V 0xFFF 0000|1111|1111|1111
1.65 V 0x7FF 0000|0111|1111|1111
0.00081 V 0x1 0000|0000|0000|0001
0V 0x0 0000|0000|0000|0000

 Selectable internal reference of 2.5 V or 3.3 V

 Ratiometric external reference set by VREFHI/VREFLO

 resultBase value is: ADCxRESULT_BASE (x = A to C)

 socNumber is: ADC_SOC_NUMBERx (x = 0 to 15)

Note: above table based on internal reference of 3.3 V; for external reference VREFHI
is VDDA maximum, however VREFHI is typically selected as 2.5 V or 3.0 V

TMS320F28004x Microcontroller Workshop - Analog Subsystem 6 - 13

Analog-to-Digital Converter (ADC)

Signed Input Voltages

How Can We Handle Signed Input Voltages?
Example: -1.65 V ≤ Vin ≤ +1.65 V
R
R
Vin R ADCA
1) Add 1.65 volts to the - R
-
1.65V + ADCIN0
analog input R
+

VREFLO

GND

2) Subtract “1.65” from the digital result

#include “Lab.h”
#define offset 0x07FF
void main(void)
{
int16 value; // signed

value = ADC_readResult(resultBase, socNumber) – offset;

}

Built-In ADC Calibration

Built-In ADC Calibration
 TI reserved OTP contains device specific calibration
data for the ADC, internal oscillators and buffered DAC
 The Boot ROM contains a Device_cal() routine that
copies the calibration data to their respective registers
 Device_cal() must be run to meet the specifications in
the datasheet
 The Bootloader automatically calls Device_cal() such that no
action is normally required by the user
 If the Bootloader is bypassed (e.g. during development)
Device_cal() should be called by the application:

#define Device_cal (void (*)(void))0x70280

void main(void)
{
(*Device_cal)(); // call Device_cal()
}

6 - 14 TMS320F28004x Microcontroller Workshop - Analog Subsystem

 Analog-to-Digital Converter (ADC)

Analog Subsystem External Reference

Analog Subsystem External Reference

Reference Generation ADC

Non-Inverting
Buffers
Voltage
VREFHIA
Reference CA
VREFLOA
REF3230
VREFHIB
REF3225 CB
REF3030 VREFLOB
REF3025
VREFHIC
(or similar) CC
VREFLOC

TMS320F28004x Microcontroller Workshop - Analog Subsystem 6 - 15

Comparator Subsystem (CMPSS)

Comparator Subsystem (CMPSS)

Comparator Subsystem
 Each CMPSS consists of:
 Two analog comparators
 Two programmable reference 12-bit DACs
 Two digital filters and one ramp generator
 Each comparator generates a digital output
 Indicates if voltage on positive input is greater than the
voltage on the negative input
 Positive input can be driven from an external pin or PGA
 Negative input can be driven by an external pin or 12-bit DAC
 Each comparator output can be digitally filtered to
remove spurious trip signals (majority vote)
 Ramp generator used for peak current mode control
 Ability to synchronize with EPWMSYNCO event,
SYSCLK, and a clear signal with EPWMBLANK
 DAC reference voltage can be either VDDA or VDAC

The F28004x includes independent Comparator Subsystem (CMPSS) modules that are useful for
supporting applications such as peak current mode control, switched-mode power, power factor
correction, and voltage trip monitoring. The Comparator Subsystem modules have the ability to
synchronize with a PWMSYNC event.

6 - 16 TMS320F28004x Microcontroller Workshop - Analog Subsystem

 Comparator Subsystem (CMPSS)

Comparator Subsystem Block Diagram

Comparator Subsystem Block Diagram
ChatCTL[CTRLtHS9L]
ChatSTS[ChatHSTS]
ASYbCH
SYSCLK > ChatDACCTL[SWLhADS9L] 0 CTRLtH
Catx_Ht SYSCLK SYbCH
1 To 9tWa X-BAR
+ ChatSTS[ChatHSTS]
DACHVALS D Q

>
0 2 CTRLthUTH
0 12-bit ChatH 0 Digital 3 To hUTtUT X-BAR
D Q 1 DACHVALA S
DACH 0 _ D RQ Cilter R

>
1 ChatCTL[CTRLthUTHS9L]

>
9b Catx_Hb 1 R Q
ChatCTL[ChatHLbV] hR
Ramp Denerator 1
ChatCTL[ChatHShURC9] 0 0
ChatSTS[ChatHLATCH]
ChatDACCTL[DACShURC9] 1 hR

ChatSTSCLR[HSYbCCLR9b] ChatCTL[ASYbCH9b]
ChatSTSCLR[HLATCHCLR]
9tWa1SYbCt9R
0 0 0
9tWa2SYbCt9R
1
9tWa3SYbCt9R 9tWaSYbCt9R 1
2

hR
... … ChatSTSCLR[LLATCHCLR]
9tWanSYbCt9R n-1 ChatSTSCLR[LSYbCCLR9b] ChatCTL[ASYbCL9b]
9tWaBLAbK
AbD hR
ChatDACCTL[BLAbK9b] 0 0
ChatDACCTL[RAatShURC9]
ChatSTS[ChatLLATCH]
1
9tWa1BLAbK Catx_Lt
0 SYSCLK > + hR
9tWa2BLAbK
1 R Q
9tWa3BLAbK DACLVALS D Q 0 ChatL 0
2 12-bit Digital ChatCTL[CTRLtLS9L]

>
R
... DACLVALA D RQ S

>
… DACL 0 Cilter
9tWanBLAbK D Q 1 _ 1 3 CTRLtL
n-1 Catx_Lb 1 ChatSTS[ChatLSTS]
2 To 9tWa X-BAR

>
9b ChatCTL[ChatLLbV] SYbCL
1
ChatDACCTL[BLAbKShURC9] SYSCLK ASYbCL
ChatDACCTL[SWLhADS9L] ChatCTL[ChatLShURC9] 0 To hUTtUT X-BAR

ChatCTL[CTRLthUTLS9L]

DAC Reference Comparator Truth Table

DACxVALA * DACREF Voltages Output
VDACx = A +
4096 Voltage A < Voltage B 0 Output
B -
Voltage A > Voltage B 1

Each CMPSS module is designed around a pair of analog comparators which generates a digital
output indicating if the voltage on the positive input is greater than the voltage on the negative
input. The comparator positive and negative input signals are independently selectable by using
the analog subsystem interconnect scheme. The positive input to the comparator is always
driven from an external pin. The negative input can be driven by either an external pin or an
internal programmable 12-bit digital-to-analog (DAC) as a reference voltage. Values written to
the DAC can take effect immediately or be synchronized with ePWM events. A falling-ramp
generator is optionally available to the control the internal DAC reference value for one
comparator in the module. Each comparator output is fed through a programmable digital filter
that can remove spurious trip signals. Also included is PWM blanking capability to clear-and-
reset existing or imminent trip conditions near the EPWM cycle boundaries.The output of the
CMPSS generates trip signals to the ePWM event trigger submodule and GPIO structure.

TMS320F28004x Microcontroller Workshop - Analog Subsystem 6 - 17

Programmable Gain Amplifier (PGA)

Programmable Gain Amplifier (PGA)

Programmable Gain Amplifier (PGA)
 Amplifies small input signals to increase the dynamic
range of the downstream ADC and CMPSS modules
 Reduces cost and design effort over external
standalone amplifiers
 On-chip integration ensures compatible with ADC and CMPSS
 Internally powered by VDDA and VSSA
 Adaptable to various performance needs
 Software selectable gain and filter settings
 Four programmable gain modes: 3x, 6x, 12x, 24x
 Embedded series resistors for RC filtering

 Hardware-based offset and gain trimming reduces

offset and gain errors
 Instead of software post-processing

PGA Block Diagram

PGA Block Diagram
PGA Input can be
To ADC and CMPSS used as a regular
ADC/CMPSS pin

Four Programmable Gain Modes:

3x, 6x, 12x, 24x
Filtered and
non-filtered
paths to ADC
and CMPSS

PGA Output
Filter pin can be
used as a regular
ADC/CMPSS pin

 Support for low-pass filtering by connecting an external capacitor to

PGA_OF pin:
 cut-off frequency based on standard RC equation
 PGA_OUT is an internal signal available for sampling and monitoring
by the internal ADC and CMPSS modules

6 - 18 TMS320F28004x Microcontroller Workshop - Analog Subsystem

 Digital-to-Analog Converter (DAC)

Digital-to-Analog Converter (DAC)

Digital-to-Analog Converter

 12-bit DAC provides a programmable reference output

voltage
 Analog output buffer is capable of driving an external
load
 Selectable reference voltage
 Can be used as a general-purpose DAC for generating a
DC voltage and AC waveforms (e.g. sine, square,
triangle, etc.)
 Ability to be synchronized with EPWMSYNCPER events

The buffered 12-bit DAC module can be used to provide a programmable reference output
voltage and it includes an analog output buffer that is capable of driving an external load. Values
written to the DAC can take effect immediately or be synchronized with ePWM events.

TMS320F28004x Microcontroller Workshop - Analog Subsystem 6 - 19

Digital-to-Analog Converter (DAC)

Buffered DAC Block Diagram

Buffered DAC Block Diagram
DAC_setReferenceVoltage(base, source);

Internal 1.65 V 1
VDAC 0 DACREF
0
Reference 2.5 V 1 0
1
Circuit
VREFHI DAC_[enable|disable]Output(base);
DAC_setShadowValue(base, value);
SYSCLK
VDDA

DAC D Q 0 DAC 12-bit DACOUT

AMP
VALS D Q 1 VALA DAC (x1 or x2)

VSSA
EPWM1SYNCPER 0
EPWM2SYNCPER 1
VSSA DAC_setGainMode(base, mode);
EPWM7SYNCPER 6 DAC_setLoadMode(base, mode);
EPWM8SYNCPER 7

DAC_setPWMSyncSignal(base, signal);

 DAC internal reference: 2.5 V and 3.3 V option Ideal Output

 3.3 V option outputs 1.65 V and then use 2x mode on DAC DACVALA * DACREF
DACOUT =
 2.5 V option outputs 2.5 V and then use 1x mode on DAC 4096

Two sets of DACVAL registers are present in the buffered DAC module: DACVALA and
DACVALS. DACVALA is a read-only register that actively controls the DAC value. DACVALS is a
writable shadow register that loads into DACVALA either immediately or synchronized with the
next PWMSYNC event. The ideal output of the internal DAC can be calculated as shown in the
equation above.

DAC Driverlib Functions

 Set the DAC reference voltage
DAC_setReferenceVoltage(base, source);
 Set the DAC gain mode
DAC_setGainMode(base, mode);
 Set the DAC load mode
DAC_setLoadMode(base, mode);
 Set DAC shadow value
DAC_setShadowValue(base, value);
 Enable / disable DAC output
DAC_[enable|disable]Output(base);
 Set DAC PWMSYNC signal
DAC_setPWMSyncSignal(base, signal);
 base is the ADC base address: DACx_BASE (x = A or B)
 source value is: DAC_REF_VDAC or DAC_REF_ADC_VREFHI
 mode (gain) value is: DAC_GAIN_ONE or DAC_GAIN_TWO
 mode (load) value is: DAC_LOAD_SYSCLK or DAC_LOAD_PWMSYNC
 value is the 12-bit code to be loaded into the active value register
 signal is the selected PWM signal (e.g. 2 selects PWM sync signal 2)

6 - 20 TMS320F28004x Microcontroller Workshop - Analog Subsystem

 Analog Subsystem Interconnect

Analog Subsystem Interconnect

Analog Subsystem Interconnect
Pins shared for:
 PGA functions
 ADC inputs
 DAC outputs
 CMPSS inputs
 AIO’s

Analog functions for:

 PGA inputs and
outputs
 ADC inputs
 CMPSS inputs
are grouped into
functional units by
PGAs
Note: AIO input functionality only
(name used to match legacy devices)

The Analog Subsystem Interconnect enables a very flexible pin usage, allowing for smaller device
packages. The DAC outputs, comparator subsystem inputs, PGA functions, and digital inputs are
multiplexed with the ADC inputs. This type of interconnect permits a single pin to route a signal
to multiple analog modules. The figure below is the generic analog group structure

Generic Analog Group Structure

 Determines routing of the analog pins interconnect

Analog Group x

TMS320F28004x Microcontroller Workshop - Analog Subsystem 6 - 21

Analog Subsystem Interconnect

Analog Group Connections

Analog Group Connections
Gx_ADCAB & GxADCC
 General-purpose ADC input
that connects to:
 Gx_ADCA or Gx_ADCB
 Gx_ADCC
 Connects to positive
comparator input
multiplexers
 Gx_ADCAB at position ‘3’
 Gx_ADCC at position ‘1’
 Connects to negative
comparator input
multiplexers
 Gx_ADCAB at position ‘0’
 Gx_ADCC at position ‘1’
 Connects to AIO
• Used for lower pin-count packages
• Gx_ADCC is combined with the PGA
input to allow ADC, CMPSS, or AIO to
be use if PGA is not used

The general-purpose ADC input pins, shown by the red and green lines, connects to the ADCs
and the input multiplexers which feed the positive and negative comparator subsystem inputs.
Also, the ADC input pins connect as inputs to the AIOs.

Analog Group Connections

PGAx_IN & PGAx_OUT & PGA_OF
 PGAx_IN
 Input to PGAx
 Connects to positive
comparator input
multiplexer at position ‘2’
 PGAx_OUT
 Output to PGAx (to ADCs)
 Connects to positive
comparator input
multiplexer at position ‘4’
 PGAx Filtered Output
 Connects to ADCs and
positive comparator input
multiplexer at position ‘0’
by passing PGA output
through switch + resistor
with an external capacitor
on the PGAx_OF pin
 Connects to AIO
• If switch is open, PGAx_OF pin can be
used as general-purpose ADC input or AIO

6 - 22 TMS320F28004x Microcontroller Workshop - Analog Subsystem

 Analog Subsystem Interconnect

The PGA input pin, shown by the red line, connects to the PGA and the input multiplexers which
feed the positive comparator subsystem inputs. The PGA output, shown by the green line,
connects to the ADCs and the input multiplexers which feed the positive comparator subsystem
inputs. The PGA filtered output, shown by the blue line, connects to the ADCs and the input
multiplexers which feed the positive comparator subsystem inputs, in addition to being an input to
the AIO.

Analog Group Connection – Example

In this example, we will determine the connections in Analog Group 1 for the 100 PZ package.

Analog Group Connections - Example

 Determine the connections in Analog Group 1 for the 100 PZ package

Using the Analog Pins and Internal Connection table, notice that group name G1_ADCAB is
connected to pin 10 and has a pin name as A3. This signal is always connected to ADCA and it
is multiplexed with the comparator subsystem inputs. It is also connected to AIO233. The
remaining pin numbers, pin names, and connections are determined the same way.

TMS320F28004x Microcontroller Workshop - Analog Subsystem 6 - 23

Analog Subsystem Interconnect

Analog Pins and Internal Connections

For this example, the complete Analog Group 1 connections are shown. Again, notice that pin
name ‘A3’ is connected to pin 10 as an input to ADCAIN3, and it is multiplexed with the
comparator subsystem inputs. Also, it is connected as an input to AIO233. The other remaining
connections can be mapped back to the Analog Pins and Internal Connection table.

Analog Group Connections - Example

Pin Name Group Name

Pin #

‘A3’ (10) A3
AIO233
‘A2/B6/PGA1_OF’ (9) A2, B6
AIO224
‘C0’ (19) C0
AIO237

‘PGA1_IN’ (18)
A11, B7

‘PGA1_GND’ (14)

6 - 24 TMS320F28004x Microcontroller Workshop - Analog Subsystem

 Lab 6: Analog-to-Digital Converter

Lab 6: Analog-to-Digital Converter

 Objective
The objective of this lab exercise is to become familiar with the programming and operation of the
on-chip analog-to-digital converter (ADC). The microcontroller (MCU) will be setup to sample a
single ADC input channel at a prescribed sampling rate and store the conversion result in a
circular memory buffer. In the second part of this lab exercise, the digital-to-analog converter
(DAC) will be explored.

Lab 6: ADC Sampling

+3.3 V Toggle
GND (GPIO59) (GPIO25)
data
ADC-A memory
CPU copies result
jumper
to buffer during
wire RESULT0
ADC ISR

ADCINA0

...
ePWM2 triggering
DAC-B ADC on period match
using SOCA trigger every
20 µs (50 kHz) View ADC
Sine buffer PWM
samples
Table

Code Composer
Studio

ePWM2

Recall that there are three basic ways to initiate an ADC start of conversion (SOC):
1. Using software
a. SOCx (where x = 0 to 15) causes a software initiated conversion
[ADC_TRIGGER_SW_ONLY]
2. Automatically triggered on user selectable conditions
a. CPU Timer 0/1/2 interrupt [ADC_TRIGGER_CPU1_TINTx]
b. ePWMxSOCA / ePWMxSOCB (x = 1 to 8) [ADC_TRIGGER_EPWMx_SOCA/B]
- ePWM underflow (CTR = 0)
- ePWM period match (CTR = PRD)
- ePWM underflow or period match (CTR = 0 or PRD)
- ePWM compare match (CTRU/D = CMPA/B/C/D)
c. ADC interrupt ADCINT1 or ADCINT2
- triggers SOCx selected by the ADC Interrupt Trigger SOC
[ADC_INT_SOC_TRIGGER_NONE or ADC_INT_SOC_TRIGGER_ADCINTx]
3. Externally triggered using a pin
a. SOCx trigger by ADCEXTSOC via INPUT5 X-BAR GPIO pin
[ADC_TRIGGER_GPIO]

One or more of these methods may be applicable to a particular application. In this lab exercise,
we will be using the ADC for data acquisition. Therefore, one of the ePWMs (ePWM2) will be
configured to automatically trigger the SOCA signal at the desired sampling rate (ePWM period

TMS320F28004x Microcontroller Workshop - Analog Subsystem 6 - 25

Lab 6: Analog-to-Digital Converter

match CTR = PRD SOC method 2b above). The ADC end-of-conversion interrupt will be used to
prompt the CPU to copy the results of the ADC conversion into a results buffer in memory. This
buffer pointer will be managed in a circular fashion, such that new conversion results will
continuously overwrite older conversion results in the buffer. In order to generate an interesting
input signal, the code also alternately toggles a GPIO pin (GPIO25) high and low in the ADC
interrupt service routine. The ADC ISR will also toggle LED5 on the LaunchPad as a visual
indication that the ISR is running. This pin will be connected to the ADC input pin, and sampled.
After taking some data, Code Composer Studio will be used to plot the results. A flow chart of the
code is shown in the following slide.

Lab 6: Code Flow Diagram

Start General Initialization ADC interrupt

• PLL and clocks
• Watchdog configure
• GPIO setup
• PIE initialization
Main Loop ADC ISR
while(1) • read the ADC result
ADC Initialization • write to result buffer
• convert channel A0 on { • adjust the buffer pointer
ePWM2 period match } • toggle the GPIO pin
• send interrupt on EOC • return from interrupt
to trigger ADC ISR
• setup a results buffer
in memory
return
ePWM2 Initialization
• clear counter
• set period register
• set to trigger ADC on
period match
• set the clock prescaler
• enable the timer

Notes
• Program performs conversion on ADCA channel 0 (ADCINA0 pin)
• ADC conversion is set at a 50 kHz sampling rate
• ePWM2 is triggering the ADC on period match using SOCA trigger
• Data is continuously stored in a circular buffer
• GPIO25 pin is also toggled in the ADC ISR
• ADC ISR will also toggle the LaunchPad LED5 as a visual indication that it is running

6 - 26 TMS320F28004x Microcontroller Workshop - Analog Subsystem

 Lab 6: Analog-to-Digital Converter

 Procedure

Open the Project

1. A project named Lab6 has been created for this lab exercise. Open the project by
clicking on Project  Import CCS Projects. The “Import CCS Eclipse Projects”
window will open then click Browse… next to the “Select search-directory” box. Navigate
to: C:\F28004x\Labs\Lab6\project and click Select Folder. Then click
Finish to import the project. All build options have been configured the same as the
previous lab exercise. The files used in this lab exercise are:

Adc_6.c Gpio.c
CodeStartBranch.asm Lab_5_6_7.cmd
Dac.c Main_6.c
DefaultIsr_6.c SineTable.c
device.c Watchdog.c
EPwm_6.c

Note: The Dac.c and SineTable.c files are used to generate a sine waveform in the
second part of this lab exercise.

Setup ADC Initialization and Enable Core/PIE Interrupts

2. In Main_6.c add code to call the InitAdca(),InitDacb() and InitEPwm()
functions. The InitEPwm() function is used to configure ePWM2 to trigger the ADC at
a 50 kHz rate. Details about the ePWM and control peripherals will be discussed in the
next module. The InitDacb() function will be used in the second part of this lab
exercise.
3. Edit Adc_6.c to configure SOC0 in the ADC as follows:
• SOC0 converts input ADCINA0
• SOC0 has a 8 SYSCLK cycle acquisition window
• SOC0 is triggered by the ePWM2 SOCA
• SOC0 triggers ADCINT1 on end-of-conversion
• All SOCs run round-robin
4. Using the “PIE Interrupt Assignment Table” find the location for the ADC interrupt
“INT_ADCA1” and fill in the following information:

PIE group #: # within group:

This information will be used in the next step.
5. Modify the end of Adc_6.c to do the following:
• Add the Driverlib function to re-map the ADC interrupt signal to call the ISR func-
tion. (Hint: #define name in driverlib/inc/hw_ints.h and label name in
DefaultIsr_6.c)
• Add the Driverlib function to enable the appropriate PIEIER and core IER
6. Save all changes to the files.
7. Inspect DefaultIsr_6.c. This file contains the ADC interrupt service routine.

TMS320F28004x Microcontroller Workshop - Analog Subsystem 6 - 27

Lab 6: Analog-to-Digital Converter

Build and Load

8. Click the “Build” button and watch the tools run in the Console window. Check for
errors in the Problems window.
9. Click the “Debug” button (green bug). The CCS Debug perspective view should open,
the program will load automatically, and you should now be at the start of main(). If the
device has been power cycled since the last lab exercise, be sure to configure the boot
mode to EMU_BOOT_RAM using the Scripts menu.

Run the Code

10. In Main_6.c place the cursor in the “main loop” section, right click on the mouse key
and select Run To Line.

Open a memory browser to view some of the contents of the ADC results buffer. The
address label for the ADC results buffer is AdcBuf (type &AdcBuf) in the “Data” memory
page. Then <enter> to view the contents of the ADC result buffer.

Note: Exercise care when connecting any jumper wires to the LaunchPad header pins
since the power to the USB connector is on!

Refer to the following diagram for the location of the pins that will need to be connected:

11. Using a jumper wire, connect the ADCINA0 (pin #70) to “GND” (pin #20) on the
LaunchPad. Then run the code again, and halt it after a few seconds. Verify that the
ADC results buffer contains the expected value of ~0x0000.

12. Adjust the jumper wire to connect the ADCINA0 (pin #70) to “+3.3V” (pin #11; GPIO-
59) on the LaunchPad. (Note: pin # GPIO-59 has been set to “1” in Gpio.c). Then run
the code again, and halt it after a few seconds. Verify that the ADC results buffer
contains the expected value of ~0x0FFF.

13. Adjust the jumper wire to connect the ADCINA0 (pin #70) to GPIO25 (pin #31) on the
LaunchPad. Then run the code again, and halt it after a few seconds. Examine the
contents of the ADC results buffer (the contents should be alternating ~0x0000 and
~0x0FFF values). Are the contents what you expected?

14. Open and setup a graph to plot a 50-point window of the ADC results buffer.
Click: Tools  Graph  Single Time and set the following values:

6 - 28 TMS320F28004x Microcontroller Workshop - Analog Subsystem

 Lab 6: Analog-to-Digital Converter

Acquisition Buffer Size 50

DSP Data Type 16-bit unsigned integer

Sampling Rate (Hz) 50000

Start Address AdcBuf

Display Data Size 50

Time Display Unit µs

Select OK to save the graph options.

15. Recall that the code toggled the GPIO25 pin alternately high and low. (Also, the ADC
ISR is toggling the LED5 on the LaunchPad as a visual indication that the ISR is running).
If you had an oscilloscope available to display GPIO25, you would expect to see a
square-wave. Why does Code Composer Studio plot resemble a triangle wave? What is
the signal processing term for what is happening here?

16. Recall that the program toggled the GPIO25 pin at a 50 kHz rate. Therefore, a complete
cycle (toggle high, then toggle low) occurs at half this rate, or 25 kHz. We therefore
expect the period of the waveform to be 40 µs. Confirm this by measuring the period of
the triangle wave using the “measurement marker mode” graph feature. In the graph
window toolbar, left-click on the ruler icon with the red arrow . Note when you hover
your mouse over the icon, it will show “Toggle Measurement Marker Mode”.
Move the mouse to the first measurement position and left-click. Again, left-click on the
Toggle Measurement Marker Mode icon. Move the mouse to the second
measurement position and left-click. The graph will automatically calculate the difference
between the two values taken over a complete waveform period. When done, clear the
measurement points by right-clicking on the graph and select Remove All
Measurement Marks (or Ctrl+Alt+M).

Using Real-time Emulation

Real-time emulation is a special emulation feature that offers two valuable capabilities:

A. Windows within Code Composer Studio can be updated at up to a 10 Hz rate while the
MCU is running. This not only allows graphs and watch windows to update, but also
allows the user to change values in watch or memory windows, and have those
changes affect the MCU behavior. This is very useful when tuning control law
parameters on-the-fly, for example.

B. It allows the user to halt the MCU and step through foreground tasks, while specified
interrupts continue to get serviced in the background. This is useful when debugging
portions of a real-time system (e.g., serial port receive code) while keeping critical
parts of your system operating (e.g., commutation and current loops in motor control).

We will only be utilizing capability “A” above during the workshop. Capability “B” is a
particularly advanced feature, and will not be covered in the workshop.

17. The memory and graph windows displaying AdcBuf should still be open. The jumper wire
between ADCINA0 (pin #70) and GPIO25 (pin #31) should still be connected. In real-
time mode, we will have our window continuously refresh at the default rate. To view the
refresh rate click:

TMS320F28004x Microcontroller Workshop - Analog Subsystem 6 - 29

Lab 6: Analog-to-Digital Converter

Window  Preferences…

and in the section on the left select the “Code Composer Studio” category. Click the sign
(‘+’ or ‘>’) to the left of “Code Composer Studio” and select “Debug”. In the section on the
right notice the default setting:

• “Continuous refresh interval (milliseconds)” = 500

Click Cancel to close the window.

Note: Decreasing the “Continuous refresh interval” causes all enabled continuous refresh
windows to refresh at a faster rate. This can be problematic when a large number of
windows are enabled, as bandwidth over the emulation link is limited. Updating too many
windows can cause the refresh frequency to bog down. In this case you can just
selectively enable continuous refresh for the individual windows of interest.

18. Next we need to enable the graph window for continuous refresh. Select the “Single
Time” graph. In the graph window toolbar, left-click on the yellow icon with the arrows
rotating in a circle over a pause sign . Note when you hover your mouse over the icon,
it will show “Enable Continuous Refresh”. This will allow the graph to continuously
refresh in real-time while the program is running.

19. Enable the Memory Browser for continuous refresh using the same procedure as the
previous step.

20. To enable and run real-time emulation mode, click the “Enable Silicon Real-time Mode”
toolbar button . A window may open and if prompted select Yes to the “Do you want to
enable realtime mode?” question. This will force the debug enable mask bit (DBGM) in
status register ST1 to ‘0’, which will allow the memory and register values to be passed to
the host processor for updating (i.e. debug events are enabled). Hereafter, Resume and
Suspend are used to run and halt real-time debugging. In the remaining lab exercises
we will run and halt the code in real-time emulation mode.

21. Run the code (real-time mode).

22. Carefully remove and replace the jumper wire from GPIO25 (pin #31). Are the values
updating in the Memory Browser and Single Time graph as expected?

23. Halt the code.

24. So far, we have seen data flowing from the MCU to the debugger in real-time. In this
step, we will flow data from the debugger to the MCU.
• Open and inspect Main_6.c. Notice that the global variable DEBUG_TOGGLE is
used to control the toggling of the GPIO25 pin. This is the pin being read with the
ADC.
• Highlight DEBUG_TOGGLE with the mouse, right click and select “Add Watch
Expression…” and then select OK. The global variable DEBUG_TOGGLE should
now be in the Expressions window with a value of “1”.
• Enable the Expressions window for continuous refresh
• Run the code in real-time mode and change the value to “0”. Are the results shown
in the memory and graph window as expected? Change the value back to “1”. As
you can see, we are modifying data memory contents while the processor is running
in real-time (i.e., we are not halting the MCU nor interfering with its operation in any
way)! When done, halt the CPU.

6 - 30 TMS320F28004x Microcontroller Workshop - Analog Subsystem

 Lab 6: Analog-to-Digital Converter

Setup DAC to Generate a Sine Waveform

Next, we will configure DACB to generate a fixed frequency sine wave. This signal will
appear on an analog output pin of the device (ADCINA1). Then using the jumper wire we will
connect the DACB output to the ADCA input (ADCINA0) and display the sine wave in a graph
window.

25. Notice the following code lines in the ADCA1 ISR in DefaultIsr_6.c:
//--- Write to DAC-B to create input to ADC-A0
if(SINE_ENABLE == 1)
{
DacOutput = DacOffset + ((QuadratureTable[iQuadratureTable++] ^ 0x8000) >> 5);
}
else
{
DacOutput = DacOffset;
}
if(iQuadratureTable > (SINE_PTS – 1)) // Wrap the index
{
iQuadratureTable = 0;
}
DAC_setShadowValue(DACB_BASE, DacOutput);

The variable DacOffset allows the user to adjust the DC output of DACB from the
Expressions window in CCS. The variable Sine_Enable is a switch which adds a fixed
frequency sine wave to the DAC offset. The sine wave is generated using a 25-point
look-up table contained in the SineTable.c file. We will plot the sine wave in a graph
window while manually adjusting the offset.

26. Open and inspect SineTable.c. (If needed, open the Project Explorer window in the
CCS Debug perspective view by clicking View  Project Explorer). The file
consists of an array of 25 signed integer points which represent four quadrants of
sinusoidal data. The 25 points are a complete cycle. In the source code we need to
sequentially access each of the 25 points in the array, converting each one from signed
16-bit to un-signed 12-bit format before writing it to the DACVALS register of DACB.
27. Add the following variables to the Expressions window:
• SINE_ENABLE
• DacOffset
28. Adjust the jumper wire to connect the ADCINA0 (pin #70) to DACB (pin #30) on the
LaunchPad. Refer to the following diagram for the pins that need to be connected.

29. Run the code (real-time mode).

30. At this point, the graph should be displaying a DC signal near zero. Click on the
DacOffset variable in the Expressions window and change the value to 800. This
changes the DC output of the DAC which is applied to the ADC input. The level of the
graph display should be about 800 and this should be reflected in the value shown in the
memory buffer (note: 800 decimal = 0x320 hex).

TMS320F28004x Microcontroller Workshop - Analog Subsystem 6 - 31

Lab 6: Analog-to-Digital Converter

31. Enable the sine generator by changing the variable SINE_ENABLE in the Expressions
window to 1.
32. You should now see sinusoidal data in the graph window.

33. Try removing and re-connecting the jumper wire to show this is real data is running in
real-time emulation mode. Also, you can try changing the DC offset variable to move the
input waveform to a different average value (the maximum distortion free offset is about
2000).

34. Halt the code.

Terminate Debug Session and Close Project

35. Terminate the active debug session using the Terminate button. This will close the
debugger and return Code Composer Studio to the CCS Edit perspective view.

36. Next, close the project by right-clicking on Lab6 in the Project Explorer window and
select Close Project.

End of Exercise

6 - 32 TMS320F28004x Microcontroller Workshop - Analog Subsystem

 Control Peripherals
Introduction
The C2000 high-performance control peripherals are an integral component for all digital control
systems. This module starts with a review of pulse width modulation (PWM) and then explains
how the ePWM is configured for generating PWM waveforms. Also, the use of the eCAP and the
eQEP will be discussed. Additionally, an overview of the Sigma Delta Filter Module will be
discussed.

Module Objectives
Module Objectives

 Pulse Width Modulation (PWM) review

 Generate a PWM waveform with the Pulse
Width Modulator Module (ePWM)
 Use the Capture Module (eCAP) to measure
the width of a waveform
 Explain the function of Quadrature Encoder
Pulse Module (eQEP)
 Describe the purpose of the Sigma Delta
Filter Module (SDFM)

TMS320F28004x Microcontroller Workshop - Control Peripherals 7-1

PWM Review

Chapter Topics
Control Peripherals ..................................................................................................................... 7-1
PWM Review ............................................................................................................................. 7-3
ePWM........................................................................................................................................ 7-5
ePWM Time-Base Sub-Module ............................................................................................ 7-7
ePWM Compare Sub-Module ............................................................................................. 7-10
ePWM Action Qualifier Sub-Module ................................................................................... 7-13
Asymmetric and Symmetric Waveform Generation using the ePWM ................................ 7-19
PWM Computation Example ............................................................................................... 7-20
ePWM Dead-Band Sub-Module .......................................................................................... 7-21
ePWM Chopper Sub-Module .............................................................................................. 7-23
ePWM Trip-Zone and Digital Compare Sub-Modules ........................................................ 7-25
ePWM Event-Trigger Sub-Module ...................................................................................... 7-31
High Resolution PWM (HRPWM)........................................................................................ 7-33
eCAP ....................................................................................................................................... 7-35
eQEP ....................................................................................................................................... 7-39
Sigma Delta Filter Module (SDFM) ......................................................................................... 7-42
Lab 7: Control Peripherals ...................................................................................................... 7-44

7-2 TMS320F28004x Microcontroller Workshop - Control Peripherals

 PWM Review

PWM Review
What is Pulse Width Modulation?
 PWM is a scheme to represent a
signal as a sequence of pulses
 fixed carrier frequency
 fixed pulse amplitude
 pulse width proportional to
instantaneous signal amplitude
 PWM energy ≈ original signal energy

t t
T
Original Signal PWM representation

Pulse width modulation (PWM) is a method for representing an analog signal with a digital
approximation. The PWM signal consists of a sequence of variable width, constant amplitude
pulses which contain the same total energy as the original analog signal. This property is
valuable in digital motor control as sinusoidal current (energy) can be delivered to the motor using
PWM signals applied to the power converter. Although energy is input to the motor in discrete
packets, the mechanical inertia of the rotor acts as a smoothing filter. Dynamic motor motion is
therefore similar to having applied the sinusoidal currents directly.

TMS320F28004x Microcontroller Workshop - Control Peripherals 7-3

PWM Review

Why use PWM with Power

Switching Devices?
 Desired output currents or voltages are known
 Power switching devices are transistors
 Difficult
to control in proportional region
 Easy to control in saturated region

 PWM is a digital signal ⇒ easy for MCU to output

DC Supply DC Supply

? PWM
Desired PWM approx.
signal to of desired
system signal
Unknown Gate Signal Gate Signal Known with PWM

Power switching devices can be difficult to control when operating in the proportional region, but
are easy to control in the saturation and cutoff regions. Since PWM is a digital signal by nature
and easy for an MCU to generate, it is ideal for use with power switching devices. Essentially,
PWM performs a DAC function, where the duty cycle is equivalent to the DAC analog amplitude
value.

7-4 TMS320F28004x Microcontroller Workshop - Control Peripherals

 ePWM

ePWM
ePWM Module Signals and Connections

ePWMx-1

EPWMxSYNCI EPWMxTZINT
INPUT PIE
EPWMxINT
X-Bar CLA
EQEPERR – TZ4 EPWMxA
eQEP
GPIO
CLOCKFAIL – TZ5 ePWMx EPWMxB
SYSCTRL MUX
EMUSTOP – TZ6
CPU
EPWMxSOCA
ePWM EPWMxSOCB ADC
X-Bar EPWMxSYNCO

ePWMx+1

Note: the order in which the ePWM modules are connected is determined by the device synchronization scheme

The ePWM modules are highly programmable, extremely flexible, and easy to use, while being
capable of generating complex pulse width waveforms with minimal CPU overhead or
intervention. Each ePWM module is identical with two PWM outputs, EPWMxA and EPWMxB,
and multiple modules can synchronized to operate together as required by the system application
design. The generated PWM waveforms are available as outputs on the GPIO pins. Additionally,
the EPWM module can generate ADC starter conversion signals and generate interrupts to the
PIE block. External trip zone signals can trip the output, as well as generate interrupts. The
outputs of the comparators are used as inputs to the ePWM X-Bar. Next, the internal details of
the ePWM module will be covered.

TMS320F28004x Microcontroller Workshop - Control Peripherals 7-5

ePWM

ePWM Synchronization Scheme

EXTSYNCIN1 EXTSYNCIN2

ePWM1
EPWM1
SYNCOUT
ePWM2
EPWM4 EXT
SYNCOUT SYNCOUT
ePWM3 ePWM4
EPWM7
SYNCOUT
ePWM5 ePWM7
ECAP1
SYNCOUT SYNCOUT
ePWM6 ePWM8 eCAP1
ECAP4
SYNCOUT
eCAP2 eCAP4
EPWM4SYNCIN

EPWM7SYNCIN eCAP3 eCAP5 eCAP6

ECAP1SYNCIN eCAP7

ECAP4SYNCIN

ECAP6SYNCIN

Various ePWM modules (and eCAP units) can be grouped together for synchronization.

ePWM Block Diagram

Time-Base Signals Event EPWaxSOCA
Counter Compare Signals Trigger EPWaxSOCB ADC
EPWaxSYNCI Digital Compare Signals (ET)
EPWaxINT
CTR = PRD PIE
Digital Action EPWaxTZINT
Compare Time-Base CTR = 0
Qualifier CTR = PRD
Signals (TB) CTR_Dir (AQ) CTR = 0

T1* EPWaxA Dead PWa Trip EPWaxA

EPWaxSYNCO Band Chopper Zone EPWaxB DPIO
T2* EPWaxB (DB) (PC) (TZ)
CTR = CaPA
EQEPxERR (TZ4)
Counter CTR = CaPB EQEPx TZ1 to TZ3 INPUT
Compare EaUSTOP (TZ6) X-BAR
CTR = CaPC* CPU
(CC) CLOCKFAIL (TZ5)
SYSCTRL
CTR = CaPD*
PIEERR
Digital
* Notes:
• T1 / T2 sources: TZ, DC, EPWaxSYNCI 28x RAa/ ECCDBLERR Compare EPWa
• CaPC / CaPD: sources for ET Flash ECC (DC) X-BAR

The ePWM module consists of eight submodules: time-base, counter-compare, action-qualifier,

dead-band generator, PWM chopper, trip-zone, digital-compare, and event-trigger.

7-6 TMS320F28004x Microcontroller Workshop - Control Peripherals

 ePWM

ePWM Time-Base Sub-Module

ePWM Time-Base Sub-Module
Time-Base Signals Event EPWaxSOCA
Counter Compare Signals Trigger EPWaxSOCB ADC
EPWaxSYbCI Digital Compare Signals (ET)
EPWaxIbT
CTR = PRD PIE
Digital Action EPWaxTZIbT
Compare Time-Base CTR = 0
Qualifier CTR = PRD
Signals (TB) CTR_Dir (AQ) CTR = 0

T1* EPWaxA Dead PWa Trip EPWaxA

EPWaxSYbCO Band Chopper Zone EPWaxB GPIO
T2* EPWaxB (DB) (PC) (TZ)
CTR = CaPA
EQEPxERR (TZ4)
Counter CTR = CaPB EQEPx TZ1 to TZ3 IbPUT
Compare EaUSTOP (TZ6) X-BAR
CTR = CaPC* CPU
(CC) CLOCKFAIL (TZ5)
SYSCTRL
CTR = CaPD*
PIEERR
Digital
* botes:
• T1 / T2 sources: TZ, DC, EPWaxSYbCI 28x RAa/ ECCDBLERR Compare EPWa
• CaPC / CaPD: sources for ET Flash ECC (DC) X-BAR

The time-base submodule consists of a dedicated 16-bit counter, along with built-in
synchronization logic to allow multiple ePWM modules to work together as a single system. A
clock pre-scaler divides the EPWM clock to the counter and a period register is used to control
the frequency and period of the generated waveform. The period register has a shadow register,
which acts like a buffer to allow the register updates to be synchronized with the counter, thus
avoiding corruption or spurious operation from the register being modified asynchronously by the
software.

TMS320F28004x Microcontroller Workshop - Control Peripherals 7-7

ePWM

Time-Base Count Modes

TBCTR

TBPRD
Asymmetrical
Waveform

Count Up Mode
TBCTR

TBPRD
Asymmetrical
Waveform

Count Down Mode

TBCTR

TBPRD
Symmetrical
Waveform

Count Up and Down Mode

The time-base counter operates in three modes: up-count, down-count, and up-down-count. In
up-count mode the time-base counter starts counting from zero and increments until it reaches
the period register value, then the time-base counter resets to zero and the count sequence starts
again. Likewise, in down-count mode the time-base counter starts counting from the period
register value and decrements until it reaches zero, then the time-base counter is loaded with the
period value and the count sequence starts again. In up-down-count mode the time-base counter
starts counting from zero and increments until it reaches the period register value, then the time-
base counter decrements until it reaches zero and the count sequence repeats. The up-count
and down-count modes are used to generate asymmetrical waveforms, and the up-down-count
mode is used to generate symmetrical waveforms.

7-8 TMS320F28004x Microcontroller Workshop - Control Peripherals

 ePWM

ePWM Phase Synchronization Example

Ext. SyncIn EPWM_[enable|disable]PhaseShiφtLoad(base);
EPWM_setPhaseShiφt(base, phaseCount);
Phase
φ=0°
En
o o .
SyncIn
EPWM1A
o
CTR=zero o
CTR=CMPB * o o EPWM1B
X o
SyncOut
To eCAP1
SyncIn
Phase
φ=120°
En
o o .
SyncIn
EPWM2A φ=120°
o
CTR=zero o
CTR=CMPB * o o EPWM2B
X o
SyncOut

Phase
φ=240°
En
o o .
SyncIn
EPWM3A
φ=120°

o
CTR=zero o
CTR=CMPB * o o EPWM3B
X o
SyncOut φ=240°
* Extended selection for EPWM_setSyncOutPulseMode(base, mode);
CMPC and CMPD available

Synchronization allows multiple ePWM modules to work together as a single system. The
synchronization is based on a synch-in signal, time-base counter equals zero, or time-base
counter equals compare B register, which can also be extended to compare C and compare D.
Additionally, the waveform can be phase-shifted.

Time-Base Functional Diagram

EPWM_setClockPrescaler(base, prescaler, highSpeedPrescaler);

EPWM_setTimeBasePeriod(base, periodCount);
EPWM_setPeriodLoadMode(base, loadMode);

Shadow
Period
Register

EPWMCLK Clock TBCLK 16-Bit TB Signals

Prescaler Counter
EPWMSYNCI EPWMSYNCO

EPWM_setTimeBaseCountMode(base, counterMode);

TBCLK = EPWMCLK / (HSPCLKDIV * CLKDIV)

Clock Prescaler = HSPCLKDIV * CLKDIV

TMS320F28004x Microcontroller Workshop - Control Peripherals 7-9

ePWM

Time-Base Driverlib Functions

 Set Time-Base clock (HSPCLKDIV and CLKDIV)
EPWM_setClockPrescaler(base, prescaler, highSpeedPrescaler);
 Set Time-Base count mode
EPWM_setTimeBaseCountMode(base, counterMode);
 Set Time-Base period value and period load mode
EPWM_setTimeBasePeriod(base, periodCount);
EPWM_setPeriodLoadMode(base, loadMode);
 Set EPWMSYNC out pulse event
EPWM_setSyncOutPulseMode(base, mode);
 base is the ePWM base address: EPWMx_BASE (x = 1 to 8)
 prescaler value is: EPWM_CLOCK_DIVIDER_x (x = 2^n where n is 0 to 7)
 highSpeedPrescaler value is: EPWM_HSCLOCK_DIVIDER_x (x = 1 or an
even value between 2 and 14 inclusive)
 counterMode value is: EPWM_COUNTER_MODE_x (x = UP, DOWN,
UP_DOWN, or STOP_FREEZE )
 periodCount can have a maximum value of 0xFFFF
 loadMode value is: EPWM_PERIOD_x (x = SHADOW_LOAD or DIRECT_LOAD)
 mode value is: EPWM_SYNC_OUT_PULSE_ON_x (x = SOFTWARE,
COUNTER_ZERO, COUNTER_COMPARE_y (y = B, C, or D), or
EPWM_SYNC_OUT_PULSE_DISABLED)

ePWM Compare Sub-Module

ePWM Counter Compare Sub-Module
Time-Base Signals Event EtWaxSOCA
Counter Compare Signals Trigger EtWaxSOCB ADC
EtWaxSYbCI Digital Compare Signals (ET)
EtWaxIbT
CTR = tRD tIE
Digital Action EtWaxTZIbT
Compare Time-Base CTR = 0
Qualifier CTR = tRD
Signals (TB) CTR_Dir (AQ) CTR = 0

T1* EtWaxA Dead tWa Trip EtWaxA

EtWaxSYbCO Band Chopper Zone EtWaxB GtIO
T2* EtWaxB (DB) (tC) (TZ)
CTR = CatA
EQEtxERR (TZ4)
Counter CTR = CatB EQEtx TZ1 to TZ3 IbtUT
Compare EaUSTOt (TZ6) X-BAR
CTR = CatC* CtU
(CC) CLOCKCAIL (TZ5)
SYSCTRL
CTR = CatD*
tIEERR
Digital
* botes:
• T1 / T2 sources: TZ, DC, EtWaxSYbCI 28x RAa/ ECCDBLERR Compare EtWa
• CatC / CatD: sources for ET Clash ECC (DC) X-BAR

The counter-compare submodule continuously compares the time-base count value to four
counter compare registers (CMPA, CMPB, CMPC, and CMPD) and generates four independent
compare events (i.e. time-base counter equals a compare register value) which are fed to the

7 - 10 TMS320F28004x Microcontroller Workshop - Control Peripherals

 ePWM

action-qualifier and event-trigger submodules. The counter compare registers are shadowed to
prevent corruption or glitches during the active PWM cycle. Typically CMPA and CMPB are used
to control the duty cycle of the generated PWM waveform, and all four compare registers can be
used to start an ADC conversion or generate an ePWM interrupt. For the up-count and down-
count modes, a counter match occurs only once per cycle, however for the up-down-count mode
a counter match occurs twice per cycle since there is a match on the up count and down count.

Counter Compare Event Waveforms

TBCTR .
. .. ..
= compare events are fed to the Action Qualifier Sub-Module
TBPRD
. . .
. . . . .
CMPA Asymmetrical
CMPB Waveform

Count Up Mode
TBCTR

TBPRD .. .. ..
. .. .. ..
CMPA Asymmetrical
CMPB Waveform

Count Down Mode

.. ..
TBCTR

TBPRD
. .
.. ... ..
CMPA Symmetrical
CMPB Waveform

Count Up and Down Mode

CMPC and CMPD available for use as event triggers

The above ePWM Compare Event Waveform diagram shows the compare matches which are fed
into the action qualifier. Notice that with the count up and countdown mode, there are matches
on the up-count and down-count.

TMS320F28004x Microcontroller Workshop - Control Peripherals 7 - 11

ePWM

Counter Compare Functional Diagram

EPWM_setCounterCompareValue(base, compModule, compCount);
Function applies to Compare A, B, C, and D

Shadow Shadow
Compare A Compare B
If shadow mode disabled

TB Signals Signals to
Counter Compare AQ & ET

Compare C Compare D
Shadow Shadow

Functions apply to Shadow A, B, C, and D

EPWM_setCounterCompareShadowLoadMode(base, compModule, loadMode);

Shadow mode – the compare register is double buffered

EPWM_disableCounterCompareShadowLoadMode(base, compModule);
Immediate mode – the shadow register is not used

Counter Compare Driverlib Functions

 Set Counter Compare value
EPWM_setCounterCompareValue(base, compModule,
compCount);
 Enable and set Counter Compare shadow load mode
EPWM_setCounterCompareShadowLoadMode(base,
compModule, loadMode);
 Disable Counter Compare shadow load mode
EPWM_disableCounterCompareShadowLoadMode(base,
compModule);
 base is the ePWM base address: EPWMx_BASE (x = 1 to 8)
 compModule value is: EPWM_COUNTER_COMPARE_x (x = A, B, C, or D)
 compCount can have a maximum value of 0xFFFF)
 loadMode value is:
 EPWM_COMP_LOAD_ON_CNTR_x (x = ZERO, PERIOD, or
ZERO_PERIOD)
 EPWM_COMP_LOAD_FREEZE
 EPWM_COMP_LOAD_ON_SYNC_CNTR_x (x = ZERO, PERIOD, or
ZERO_PERIOD)
 EPWM_COMP_LOAD_ON_SYNC_ONLY

7 - 12 TMS320F28004x Microcontroller Workshop - Control Peripherals

 ePWM

ePWM Action Qualifier Sub-Module

ePWM Action Qualifier Sub-Module
Time-Base Signals Event EtWaxSOCA
Counter Compare Signals Trigger EtWaxSOCB ADC
EtWaxSYbCI Digital Compare Signals (ET)
EtWaxIbT
CTR = tRD tIE
Digital Action EtWaxTZIbT
Compare Time-Base CTR = 0
Qualifier CTR = tRD
Signals (TB) CTR_Dir (AQ) CTR = 0

T1* EtWaxA Dead tWa Trip EtWaxA

EtWaxSYbCO Band Chopper Zone EtWaxB GtIO
T2* EtWaxB (DB) (tC) (TZ)
CTR = CatA
EQEtxERR (TZ4)
Counter CTR = CatB EQEtx TZ1 to TZ3 IbtUT
Compare EaUSTOt (TZ6) X-BAR
CTR = CatC* CtU
(CC) CLOCKFAIL (TZ5)
SYSCTRL
CTR = CatD*
tIEERR
Digital
* botes:
• T1 / T2 sources: TZ, DC, EtWaxSYbCI 28x RAa/ ECCDBLERR Compare EtWa
• CatC / CatD: sources for ET Flash ECC (DC) X-BAR

The action-qualifier submodule is the key element in the ePWM module which is responsible for
constructing and generating the switched PWM waveforms. It utilizes match events from the
time-base and counter-compare submodules for performing actions on the EPWMxA and
EPWMxB output pins. These first three submodules are the main blocks which are used for
generating a basic PWM waveform.

TMS320F28004x Microcontroller Workshop - Control Peripherals 7 - 13

ePWM

ePWM Action Qualifier Actions

for EPWMA and EPWMB

Time-Base Counter equals: Trigger Events: EPWM

S/W Output
Force Actions
Zero CMPA CMPB TBPRD T1 T2

SW Z CA CB P T1 T2 Do Nothing
X X X X X X X

SW Z CA CB P T1 T2
Clear Low
↓ ↓ ↓ ↓ ↓ ↓ ↓

SW Z CA CB P T1 T2
Set High
↑ ↑ ↑ ↑ ↑ ↑ ↑

SW Z CA CB P T1 T2
Toggle
T T T T T T T

Tx Event Sources = DCAEVT1, DCAEVT2, DCBEVT1, DCBEVT2, TZ1, TZ2, TZ3, EPWMxSYNCIN

The Action Qualifier actions are setting the pin high, clearing the pin low, toggling the pin, or do
nothing to the pin, based independently on count-up and count-down time-base match event.
The match events are when the time-base counter equals the period register value, the time-base
counter is zero, the time-base counter equals CMPA, the time-base counter equals CMPB, or a
Trigger event (T1 and T2) based on a comparator, trip, or sync signal. Note that zero and period
actions are fixed in time, whereas CMPA and CMPB actions are moveable in time by
programming their respective registers. Actions are configured independently for each output
using shadowed registers, and any or all events can be configured to generate actions on either
output. Also, the output pins can be forced to any action using software.

7 - 14 TMS320F28004x Microcontroller Workshop - Control Peripherals

 ePWM

Count Up Asymmetric Waveform

with Independent Modulation on EPWMA / B

TBCTR

. .
TBPRD
. .
. .
CMPA

. . .
CMPB

Z P CB CA Z P CB CA Z P
↑ X X ↓ ↑ X X ↓ ↑ X

EPWMA

Z P CB CA Z P CB CA Z P
↑ X ↓ X ↑ X ↓ X ↑ X

EPWMB

The next few figures show how the setting of the action qualifier with the compare matches are
used to modulate the output pins. Notice that the output pins for EPWMA and EPWMB are
completely independent. In the example above, the EPWMA output is being set high on the zero
match and cleared low on the compare A match. The EPWMB output is being set high on the
zero match and cleared low on the compare B match.

Count Up Asymmetric Waveform

with Independent Modulation on EPWMA

TBCTR

. .
TBPRD
. .
. .
CMPB

. . .
CMPA

CA CB CA CB
↑ ↓ ↑ ↓

EPWMA

Z Z Z
T T T

EPWMB

TMS320F28004x Microcontroller Workshop - Control Peripherals 7 - 15

ePWM

In the example above, the EPWMA output is being set high on the compare A match and being
cleared low on the compare B match, while the EPWMB output is being toggled on the zero
match.

Count Up-Down Symmetric Waveform

with Independent Modulation on EPWMA / B

TBCTR

TBPRD
... ...
CMPB
. . . .
. .
CMPA

.
CA CA CA CA
↑ ↓ ↑ ↓

EPWMA

CB CB CB CB
↑ ↓ ↑ ↓

EPWMB

In the example above, there are different output actions on the up-count and down-count using a
single compare register. The EPWMA and EPWMB outputs are being set high on the compare A
and B up-count matches and cleared low on the compare A and B down-count matches.

Count Up-Down Symmetric Waveform

with Independent Modulation on EPWMA

TBCTR

TBPRD .. ..
CMPB
. .
. .
CMPA

.
CA CB CA CB
↑ ↓ ↑ ↓

EPWMA

Z P Z P
↓ ↑ ↓ ↑

EPWMB

7 - 16 TMS320F28004x Microcontroller Workshop - Control Peripherals

 ePWM

And finally in the example above, again using different output actions on the up-count and down-
count, the EPWMA output is being set high on the compare A up-count match and being cleared
low on the compare B down-count match. The EPWMB output is being cleared low on the zero
match and being set high on the period match.

Action Qualifier Driverlib Functions

 Configure Action Qualifier output on ePWMA or ePWMB
EPWM_setActionQualifierAction(base, epwmOutput, output,
event);
 Set Action Qualifier trigger source for event T1 or T2
EPWM_setActionQualifierT1TriggerSource(base, trigger);
EPWM_setActionQualifierT2TriggerSource(base, trigger);
 base is the ePWM base address: EPWMx_BASE (x = 1 to 8)
 epwmOutput value is: EPWM_AQ_OUTPUT_x (x = A or B)
 output value is: EPWM_AQ_OUTPUT_x (x = NO_CHANGE, LOW, HIGH, or
TOGGLE)
 event value is:
 EPWM_AQ_OUTPUT_ON_TIMEBASE_x (x = ZERO, PERIOD,
UP_CMPA, DOWN_CMPA, UP_CMPB, or DOWN_CMPB)
 EPWM_AQ_OUTPUT_ON_T1_x (x = COUNT_UP or
COUNT_DOWN)
 EPWM_AQ_OUTPUT_ON_T2_x (x = COUNT_UP or
COUNT_DOWN)
 trigger value is: EPWM_AQ_TRIGGER_EVENT_TRIG_x (x = DCA_1, DCA_2,
DCB_1, DCB_2, TZ_1, TZ_2, TZ_3, or EPWM_SYNCIN)

Action Qualifier Driverlib Functions

 Enable and set Action Qualifier shadow load mode
EPWM_setActionQualifierShadowLoadMode(base, aqModule,
loadMode);

 Disable Action Qualifier shadow load mode

EPWM_disableActionQualifierShadowLoadMode(base,
aqModule);

 base is the ePWM base address: EPWMx_BASE (x = 1 to 8)

 aqModule value is: EPWM_ACTION_QUALIFIER_x (x = A or B)
 loadMode value is:
 EPWM_AQ_LOAD_ON_CNTR_x (x = ZERO, PERIOD, or
ZERO_PERIOD)
 EPWM_AQ_LOAD_FREEZE
 EPWM_AQ_LOAD_ON_SYNC_CNTR_x (x = ZERO, PERIOD, or
ZERO_PERIOD)
 EPWM_AQ_LOAD_ON_SYNC_ONLY

TMS320F28004x Microcontroller Workshop - Control Peripherals 7 - 17

ePWM

Action Qualifier Driverlib Functions

 Trigger continuous software forced output on ePWM (A or B)
EPWM_setActionQualifierContSWForceAction(base,
epwmOutput, output);
 Set continuous software force shadow reload mode
EPWM_setActionQualifierContSWForceShadowMode(base,
mode);
 Set one time software forced action output and force action
EPWM_setActionQualifierSWAction(base, epwmOutput,
output*);
EPWM_forceActionQualifierSWAction(base, epwmOutput);
 base is the ePWM base address: EPWMx_BASE (x = 1 to 8)
 epwmOutput value is: EPWM_AQ_OUTPUT_x (x = A or B)
 output value is: EPWM_AQ_x (x = SW_DISABLED, OUTPUT_LOW, or
OUTPUT_HIGH)
 mode value is:
 EPWM_AQ_SW_SH_LOAD_ON_x (x = CNTR_ZERO, CNTR_PERIOD,
or CNTR_ZERO_PERIOD)
 EPWM_AQ_SW_IMMEDIATE_LOAD
 output* value is: EPWM_AQ_OUTPUT_x (x = NO_CHANGE, LOW, HIGH, or
TOGGLE)

7 - 18 TMS320F28004x Microcontroller Workshop - Control Peripherals

 ePWM

Asymmetric and Symmetric Waveform Generation

using the ePWM
PWM switching frequency:
The PWM carrier frequency is determined by the value contained in the time-base period register,
and the frequency of the clocking signal. The value needed in the period register is:

 switching period 
Asymmetric PWM: period register =   − 1
 timer period 
switching period
Symmetric PWM: period register =
2(timer period)
Notice that in the symmetric case, the period value is half that of the asymmetric case. This is
because for up/down counting, the actual timer period is twice that specified in the period register
(i.e. the timer counts up to the period register value, and then counts back down).

PWM resolution:
The PWM compare function resolution can be computed once the period register value is
determined. The largest power of 2 is determined that is less than (or close to) the period value.
As an example, if asymmetric was 1000, and symmetric was 500, then:

= 1024 ≈ 1000
10
Asymmetric PWM: approx. 10 bit resolution since 2

Symmetric PWM: approx. 9 bit resolution since 2 = 512 ≈ 500

9

PWM duty cycle:

Duty cycle calculations are simple provided one remembers that the PWM signal is initially
inactive during any particular timer period, and becomes active after the (first) compare match
occurs. The timer compare register should be loaded with the value as follows:

Asymmetric PWM: TxCMPR = (100% - duty cycle) ∗ TxPR

Symmetric PWM: TxCMPR = (100% - duty cycle) ∗ TxPR

Note that for symmetric PWM, the desired duty cycle is only achieved if the compare registers
contain the computed value for both the up-count compare and down-count compare portions of
the time-base period.

TMS320F28004x Microcontroller Workshop - Control Peripherals 7 - 19

ePWM

PWM Computation Example

Symmetric PWM Computation Example
 Determine TBPRD and CMPA for 100 kHz, 25% duty
symmetric PWM from a 100 MHz time base clock
fPWM = 100 kHz
(TPWM = 10 ms)

. .
Period
Compare
CA CA
Counter ↑ ↓

fTBCLK = 100 MHz

(TTBCLK = 10 ns)
PWM Pin

1 . fTBCLK 1 100 MHz

TBPRD = = . = 500
2 fPWM 2 100 kHz
CMPA = (100% - duty cycle)*TBPRD = 0.75*500 = 375

Asymmetric PWM Computation Example

 Determine TBPRD and CMPA for 100 kHz, 25% duty
asymmetric PWM from a 100 MHz time base clock

.
fPWM = 100 kHz
(TPWM = 10 ms)
Period
Compare .
CA P
Counter ↑ ↓

fTBCLK = 100 MHz

(TTBCLK = 10 ns)
PWM Pin

fTBCLK 100 MHz

TBPRD = -1= - 1 = 999
fPWM 100 kHz
CMPA = (100% - duty cycle)*(TBPRD+1) - 1 = 0.75*(999+1) - 1 = 749

7 - 20 TMS320F28004x Microcontroller Workshop - Control Peripherals

 ePWM

ePWM Dead-Band Sub-Module

ePWM Dead-Band Sub-Module
Time-Base Signals Event EPWaxSOCA
Counter Compare Signals Trigger EPWaxSOCB ADC
EPWaxSYbCI Digital Compare Signals (ET)
EPWaxIbT
CTR = PRD PIE
Digital Action EPWaxTZIbT
Compare Time-Base CTR = 0
Qualifier CTR = PRD
Signals (TB) CTR_Dir (AQ) CTR = 0

T1* EPWaxA Dead PWa Trip EPWaxA

EPWaxSYbCO Band Chopper Zone EPWaxB DPIO
T2* EPWaxB (DB) (PC) (TZ)
CTR = CaPA
EQEPxERR (TZ4)
Counter CTR = CaPB EQEPx TZ1 to TZ3 IbPUT
Compare EaUSTOP (TZ6) X-BAR
CTR = CaPC* CPU
(CC) CLOCKFAIL (TZ5)
SYSCTRL
CTR = CaPD*
PIEERR
Digital
* botes:
• T1 / T2 sources: TZ, DC, EPWaxSYbCI 28x RAa/ ECCDBLERR Compare EPWa
• CaPC / CaPD: sources for ET Flash ECC (DC) X-BAR

The dead-band sub-module provides a means to delay the switching of a gate signal, thereby
allowing time for gates to turn off and preventing a short circuit. This sub-module supports
independently programmable rising-edge and falling-edge delays with various options for
generating the appropriate signal outputs on EPWMxA and EPWMxB.

Motivation for Dead-Band

supply rail

gate signals are to power

complementary PWM switching
device

 Transistor gates turn on faster than they shut off

 Short circuit if both gates are on at the same time!

Original EPWM
Shadow
RED
EPWMxA Dead EPWMxA Rising Edge Delay
EPWMxB Band EPWMxB FED
Falling Edge Delay

TMS320F28004x Microcontroller Workshop - Control Peripherals 7 - 21

ePWM

To explain further, power-switching devices turn on faster than they shut off. This issue would
momentarily provide a path from supply rail to ground, giving us a short circuit. The dead-band
sub-module alleviates this issue.

Dead-band control provides a convenient means of combating current shoot-through problems in

a power converter. Shoot-through occurs when both the upper and lower gates in the same
phase of a power converter are open simultaneously. This condition shorts the power supply and
results in a large current draw. Shoot-through problems occur because transistors open faster
than they close, and because high-side and low-side power converter gates are typically switched
in a complimentary fashion. Although the duration of the shoot-through current path is finite
during PWM cycling, (i.e. the closing gate will eventually shut), even brief periods of a short circuit
condition can produce excessive heating and over stress in the power converter and power
supply.

Dead-Band Block Diagram

.
PWMxA

.
Rising
Edge
0 Delay
° S4° In Out
0

.
°1
0
° S1° 0
° S6°
(14-bit ° ° S2 RED PWMxA
°1
°
counter)
°1 °1
0

° °
DEDB_
MODE
°
S8 1
. 0
° S7° PWMxB

.
0
1 S8 ° ° S3 FED 1
° S0 °

. °
Falling 1
0
° ° S5 ° ° Edge °1 °
°0 Delay °
0
°1 In Out
OUTSWAP
POLSEL OUT_MODE
(14-bit
IN_MODE counter)

.
PWMxB
HALFCYCLE

See the F28004x Driver Library User’s Guide for available functions

Two basic approaches exist for controlling shoot-through: modify the transistors, or modify the
PWM gate signals controlling the transistors. In the first case, the opening time of the transistor
gate must be increased so that it (slightly) exceeds the closing time. One way to accomplish this
is by adding a cluster of passive components such as resistors and diodes in series with the
transistor gate, as shown in the next figure.

by-pass diode

PWM
signal
R

Shoot-through control via power circuit modification

The resistor acts to limit the current rise rate towards the gate during transistor opening, thus
increasing the opening time. When closing the transistor however, current flows unimpeded from
the gate via the by-pass diode and closing time is therefore not affected. While this passive

7 - 22 TMS320F28004x Microcontroller Workshop - Control Peripherals

 ePWM

approach offers an inexpensive solution that is independent of the control microprocessor, it is

imprecise, the component parameters must be individually tailored to the power converter, and it
cannot adapt to changing system conditions.

The second approach to shoot-through control separates transitions on complimentary PWM

signals with a fixed period of time. This is called dead-band. While it is possible to perform
software implementation of dead-band, the C28x offers on-chip hardware for this purpose that
requires no additional CPU overhead. Compared to the passive approach, dead-band offers
more precise control of gate timing requirements. In addition, the dead time is typically specified
with a single program variable that is easily changed for different power converters or adapted
on-line.

ePWM Chopper Sub-Module

ePWM Chopper Sub-Module
Time-Base Signals Event EPWMxShCA
Counter Compare Signals Trigger EPWMxShCB ADC
EPWMxSYbCI Digital Compare Signals (ET)
EPWMxIbT
CTR = PRD PIE
Digital Action EPWMxTZIbT
Compare Time-Base CTR = 0
Qualifier CTR = PRD
Signals (TB) CTR_Dir (AQ) CTR = 0

T1* EPWMxA Dead PWM Trip EPWMxA

EPWMxSYbCh Band Chopper Zone EPWMxB GPIh
T2* EPWMxB (DB) (PC) (TZ)
CTR = CMPA
EQEPxERR (TZ4)
Counter CTR = CMPB EQEPx TZ1 to TZ3 IbPUT
Compare EMUSThP (TZ6) X-BAR
CTR = CMPC* CPU
(CC) CLhCKCAIL (TZ5)
SYSCTRL
CTR = CMPD*
PIEERR
Digital
* botes:
• T1 / T2 sources: TZ, DC, EPWMxSYbCI 28x RAM/ ECCDBLERR Compare EPWM
• CMPC / CMPD: sources for ET Clash ECC (DC) X-BAR

The PWM chopper submodule is used with pulse transformer-based gate drives to control the
power switching devices. This submodule modulates a high-frequency carrier signal with the
PWM waveform that is generated by the action-qualifier and dead-band submodules.
Programmable options are available to support the magnetic properties and characteristics of the
transformer and associated circuitry.

TMS320F28004x Microcontroller Workshop - Control Peripherals 7 - 23

ePWM

Purpose of the PWM Chopper

 Allows a high frequency carrier

signal to modulate the PWM
waveform generated by the Action
Qualifier and Dead-Band modules
 Used with pulse transformer-based
gate drivers to control power
switching elements

Shown in the figure below, a high-frequency carrier signal is ANDed with the ePWM outputs.
Also, this circuit provides an option to include a larger, one-shot pulse width before the sustaining
pulses.

Chopper Waveform
EPWMxA

EPWMxB

CHPFREQ

EPWMxA

EPWMxB

Programmable
Pulse Width With One-
OSHT (OSHTWTH) Shot Pulse
on EPWMxA
Sustaining
and/or
EPWMxA Pulses EPWMxB

See the F28004x Driver Library User’s Guide for available functions

7 - 24 TMS320F28004x Microcontroller Workshop - Control Peripherals

 ePWM

ePWM Trip-Zone and Digital Compare Sub-Modules

ePWM Trip-Zone and Digital Compare
Sub-Modules
Time-Base Signals Event EtWaxSOCA
Counter Compare Signals Trigger EtWaxSOCB ADC
EtWaxSYbCI Digital Compare Signals (ET)
EtWaxIbT
CTR = tRD tIE
Digital Action EtWaxTZIbT
Compare Time-Base CTR = 0
Qualifier CTR = tRD
Signals (TB) CTR_Dir (AQ) CTR = 0

T1* EtWaxA Dead tWa Trip EtWaxA

EtWaxSYbCO Band Chopper Zone EtWaxB DtIO
T2* EtWaxB (DB) (tC) (TZ)
CTR = CatA
EQEtxERR (TZ4)
Counter CTR = CatB EQEtx TZ1 to TZ3 IbtUT
Compare EaUSTOt (TZ6) X-BAR
CTR = CatC* CtU
(CC) CLOCKCAIL (TZ5)
SYSCTRL
CTR = CatD*
tIEERR
Digital
* botes:
• T1 / T2 sources: TZ, DC, EtWaxSYbCI 28x RAa/ ECCDBLERR Compare EtWa
• CatC / CatD: sources for ET Clash ECC (DC) X-BAR

The trip zone and digital compare sub-modules provide a protection mechanism to protect the
output pins from abnormalities, such as over-voltage, over-current, and excessive temperature
rise.

Trip-Zone Features
 Trip-Zone has a fast, clock independent logic path to high-impedance
the EPWMxA/B output pins
 Interrupt latency may not protect hardware when responding to over
current conditions or short-circuits through ISR software
 Supports: #1) one-shot trip for major short circuits or over
current conditions
#2) cycle-by-cycle trip for current limiting operation

Over
Current CPU
Sensors core P
Digital EPWMxA W
Compare M
EPWMxTZINT

Cycle-by-Cycle O
ePWM X-Bar U
TZ1 – TZ3 INPUT X-Bar Mode T
TZ4 EQEP1ERR P
eQEP1 EPWMxB U
TZ5 CLOCKFAIL One-Shot
SYSCTRL T
CPU TZ6 EMUSTOP Mode S

See ‘Trip-Zone Submodule Mode Control Logic’ figure in F28004x TRM for details

TMS320F28004x Microcontroller Workshop - Control Peripherals 7 - 25

ePWM

The trip-zone submodule utilizes a fast clock independent logic mechanism to quickly handle fault
conditions by forcing the EPWMxA and EPWMxB outputs to a safe state, such as high, low, or
high-impedance, thus avoiding any interrupt latency that may not protect the hardware when
responding to over current conditions or short circuits through ISR software. It supports one-shot
trips for major short circuits or over current conditions, and cycle-by-cycle trips for current limiting
operation. The trip-zone signals can be generated externally from any GPIO pin which is mapped
through the Input X-Bar (TZ1 – TZ3), internally from an inverted eQEP error signal (TZ4), system
clock failure (TZ5), or from an emulation stop output from the CPU (TZ6). Additionally, numerous
trip-zone source signals can be generated from the digital-compare subsystem.

The power drive protection is a safety feature that is provided for the safe operation of systems
such as power converters and motor drives. It can be used to inform the monitoring program of
motor drive abnormalities such as over-voltage, over-current, and excessive temperature rise. If
the power drive protection interrupt is unmasked, the PWM output pins will be put in a safe
immediately after the pin is driven low. An interrupt will also be generated.

Trip-Zone Sub-Module Control Logic

7 - 26 TMS320F28004x Microcontroller Workshop - Control Peripherals

 ePWM

Trip-Zone Driverlib Functions

 Enable / disable Trip-Zone signals
EPWM_[enable|disable]TripZoneSignals(base, tzSignal);
 Set Trip-Zone Action
EPWM_setTripZoneAction(base, tzEvent, tzAction);
 Enable / disable Trip-Zone interrupts
EPWM_[enable|disable]TripZoneInterrupt(base, tzInterrupt);

 base is the ePWM base address: EPWMx_BASE (x = 1 to 8)

 tzSignal is logical OR values of:
 EPWM_TZ_SIGNAL_CBCx (x = 1 to 6)
 EPWM_TZ_SIGNAL_x (x = DCAEVT2 or DCBEVT2) <CBC>
 EPWM_TZ_SIGNAL_OSHTx (x = 1 to 6)
 EPWM_TZ_SIGNAL_x (x = DCAEVT1 or DCBEVT1) <OSHT>
 tzEvent value is: EPWM_TZ_ACTION_EVENT_x (x = TZA, TZB, DCAEVT1,
DCAEVT2, DCBEVT1, or DCBEVT2)
 tzAction value is: EPWM_TZ_ACTION_x (x = HIGH_Z, HIGH, LOW, or DISABLE)
 tzInterrupt is logical OR values of: EPWM_TZ_INTERRUPT_x (x = CBC, OST,
DCAEVT1, DCAEVT2, DCBEVT1, or DCBEVT2)

Digital Compare Trip Inputs

TRIPIN1 & TZ1
GPIO INPUT TRIPIN2 & TZ2
TRIPIN3 & TZ3
MUX X-BAR TRIPIN6 Digital
TRIPIN4
TRIPIN5 Compare
TRIPIN7
ePWM TRIPIN8 Sub-
TRIPIN9
X-BAR TRIPIN10 Module
TRIPIN11
TRIPIN12
TRIPIN14 (ECCDBLERR)
TRIPIN15 (PIEERR)
TRIPIN15
TRIPIN14
TRIPIN1 & TZ1
TRIPIN2 & TZ2
TRIPIN3 & TZ3
TRIPIN6
TRIPIN4
TRIPIN5
TRIPIN7
TRIPIN8
TRIPIN9 TRIP COMBO
TRIPIN10
TRIPIN11
TRIPIN12

The digital compare submodules receive their trip signals from the Input X-BAR and ePWM X-
BAR.

TMS320F28004x Microcontroller Workshop - Control Peripherals 7 - 27

ePWM

The ePWM X-BAR is used to route various internal and external signals to the ePWM modules.
Eight trip signals from the ePWM X-BAR are routed to all of the ePWM modules.

ePWM X-BAR

The ePWM X-BAR architecture block diagram shown below is replicated 8 times. The ePWM X-
BAR can select a single signal or logically OR up to 32 signals. The table in the figure defines the
various trip sources that can be multiplexed to the trip-zone and digital compare submodules.

ePWM X-Bar Architecture

0.0 XBAR_enableEPWMMux(trip, muxes);
0.1 0
0.2 XBAR_disableEPWMMux(trip, muxes);
0.3
1.0
This block 1.1 1
diagram is 1.2 TRIPINx
replicated 1.3
8 times
XBAR_invertEPWMSignal(trip, invert);
31.0
31.1 31
31.2
31.3

XBAR_setEPWMMuxConfig(trip, muxConfig);
MUX 0 1 2 3 MUX 0 1 2 3
0 CMPSS1.CTRIPH CMPSS1.CTRIPH_OR_CTRIPL ADCAEVT1 ECAP1OUT 16 SD1FLT1.COMPH SD1FLT1.COMPH_OR_COMPL
1 CMPSS1.CTRIPL INPUTXBAR1 ADCCEVT1 17 SD1FLT1.COMPL INPUT7 CLAHALT
2 CMPSS2.CTRIPH CMPSS2.CTRIPH_OR_CTRIPL ADCAEVT2 ECAP2OUT 18 SD1FLT2.COMPH SD1FLT2.COMPH_OR_COMPL
3 CMPSS2.CTRIPL INPUTXBAR2 ADCCEVT2 19 SD1FLT2.COMPL INPUT8
4 CMPSS3.CTRIPH CMPSS3.CTRIPH_OR_CTRIPL ADCAEVT3 ECAP3OUT 20 SD1FLT3.COMPH SD1FLT3.COMPH_OR_COMPL
5 CMPSS3.CTRIPL INPUTXBAR3 ADCCEVT3 21 SD1FLT3.COMPL INPUT9
6 CMPSS4.CTRIPH CMPSS4.CTRIPH_OR_CTRIPL ADCAEVT4 ECAP4OUT 22 SD1FLT4.COMPH SD1FLT4.COMPH_OR_COMPL
7 CMPSS4.CTRIPL INPUTXBAR4 ADCCEVT4 23 SD1FLT4.COMPL INPUT10
8 CMPSS5.CTRIPH CMPSS5.CTRIPH_OR_CTRIPL ADCBEVT1 ECAP5OUT 24
9 CMPSS5.CTRIPL INPUTXBAR5 25 INPUT11
10 CMPSS6.CTRIPH CMPSS6.CTRIPH_OR_CTRIPL ADCBEVT2 ECAP6OUT 26
11 CMPSS6.CTRIPL INPUTXBAR6 27 INPUT12
12 CMPSS7.CTRIPH CMPSS7.CTRIPH_OR_CTRIPL ADCBEVT3 ECAP7OUT 28
13 CMPSS7.CTRIPL ADCSOCA 29 INPUT13
14 ADCBEVT4 EXTSYNCOUT 30
15 ADCSOCB 31 INPUT14

7 - 28 TMS320F28004x Microcontroller Workshop - Control Peripherals

 ePWM

Purpose of the Digital Compare

Sub-Module
 Generates ‘compare’ events that can:
 Tripthe ePWM
 Generate a Trip interrupt
 Sync the ePWM
 Generate an ADC start of conversion

 Digital compare module inputs are:

 Input X-Bar
 ePWM X-Bar
 Trip-zone input pins

A compare event is generated when one or more

of its selected inputs are either high or low
 Optional ‘Blanking’ can be used to temporarily
disable the compare action in alignment with
PWM switching to eliminate noise effects

Digital Compare Sub-Module Signals

EPWM_setTripZoneDigitalCompareEventCondition(base, dcType*, dcEvent);
Time-Base Sub-Module
DCAEVT1
DCAH Digital Trip Generate PWM Sync
TRIPIN1 & TZ1 Event A1
Event-Trigger Sub-Module
Compare
TRIPIN2 & TZ2 blanking
Generate SOCA
TRIPIN3 & TZ3 Digital Trip
Trip-Zone Sub-Module
Event A2 Trip PWMA Output
TRIPIN4 DCAL
Compare
Generate Trip Interrupt
● DCAEVT2

●
Time-Base Sub-Module
● DCBEVT1
DCBH Digital Trip Generate PWM Sync
TRIPIN12 Event B1
Compare Event-Trigger Sub-Module
TRIPIN14
Generate SOCB
TRIPIN15 blanking
Digital Trip Trip-Zone Sub-Module
TRIP COMBO DCBL
Event B2 Trip PWMB Output
Compare
Generate Trip Interrupt
DCBEVT2
EPWM_selectDigitalCompareTripInput(base, tripSource, dcType);
EPWM_[enable|disable]DigitalCompareTripCombinationInput(base, tripInput, dcType);

The digital-compare subsystem compares signals external to the ePWM module, such as a signal
from the CMPSS analog comparators, to directly generate PWM events or actions which are then
used by the trip-zone, time-base, and event-trigger submodules. These ‘compare’ events can trip
the ePWM module, generate a trip interrupt, sync the ePWM module, or generate an ADC start of

TMS320F28004x Microcontroller Workshop - Control Peripherals 7 - 29

ePWM

conversion. A compare event is generated when one or more of its selected inputs are either
high or low. The signals can originate from any external GPIO pin which is mapped through the
Input X-Bar and from various internal peripherals which are mapped through the ePWM X-Bar.
Additionally, an optional ‘blanking’ function can be used to temporarily disable the compare action
in alignment with PWM switching to eliminate noise effects.

Digital Compare Events

 The user selects the input for each of DCAH, DCAL,
DCBH, DCBL
 Each A and B compare uses its corresponding
DCyH/L inputs (y = A or B)
 The user selects the signal state that triggers each
compare from the following choices:

i. DCyH  low DCyL  don’t care

ii. DCyH  high DCyL  don’t care
iii. DCyL  low DCyH  don’t care
iv. DCyL  high DCyH  don’t care
v. DCyL  high DCyH  low

EPWM_setTripZoneDigitalCompareEventCondition(base, dcType, dcEvent);

Digital Compare Driverlib Functions

 Select Digital Compare trip inputs
EPWM_selectDigitalCompareTripInput(base, tripSource, dcType);
 Enable / disable Digital Compare trip combination inputs
EPWM_[enable|disable]DigitalCompareTripCombinationInput(
base, tripInput, dcType);
 Set Digital Compare conditions which cause Trip-Zone events
EPWM_setTripZoneDigitalCompareEventCondition(base,
dcType*, dcEvent);
 base is the ePWM base address: EPWMx_BASE (x = 1 to 8)
 tripSource value is:
 EPWM_DC_TRIP_TRIPINx (x = 1 to 12, 14, 15)
 EPWM_DC_TRIP_COMBINATION - selects trip signals enabled by the
EPWM_enableDigitalCompareTripCombinationInput() function
 dcType value is: EPWM_DC_TYPE_x (x = DCAH, DCAL, DCBH , or DCBL)
 tripInput value is: EPWM_DC_COMBINATIONAL_TRIPINx (x = 1 to 12, 14, 15)
 dcType* value is: EPWM_TZ_DC_OUTPUT_x (x = A1, A2, B1, or B2)
 dcEvent value is: EPWM_TZ_EVENT_x (x = DC_DISABLED, DCyH_LOW,
DCyH_HIGH, DCyL_LOW, DCyL_HIGH, or DCyL_HIGH_DCyH_LOW)
 where y in DCyH/DCyL represents DCAH/DCAL or DCBH/DCBL

7 - 30 TMS320F28004x Microcontroller Workshop - Control Peripherals

 ePWM

Digital Compare Driverlib Functions

Time-Base Sub-Module
DCxEVT1 Generate PWM Sync
Event-Trigger Sub-Module
Generate SOCx
(x = A or B)
Trip-Zone Sub-Module
Trip PWMx Output

DCxEVT2 Generate Trip Interrupt

 Enable / disable Digital Compare Sync Event

EPWM_[enable|disable]DigitalCompareSyncEvent(base,
dcModule);
 Enable / disable Digital Compare ADC trigger
EPWM_[enable|disable]DigitalCompareADCTrigger(base,
dcModule);
 Enable / disable Trip-Zone signals and Trip-Zone interrupts
 See Trip-Zone Driverlib Functions:
EPWM_[enable|disable]TripZoneSignals(base, tzSignal);
EPWM_[enable|disable]TripZoneInterrupt(base, tzInterrupt);
 base is the ePWM base address: EPWMx_BASE (x = 1 to 8)
 dcModule value is: EPWM_DC_MODULE_x (x = A or B)

ePWM Event-Trigger Sub-Module

ePWM Event-Trigger Sub-Module
Time-Base Signals Event EtWMxSOCA
Counter Compare Signals Trigger EtWMxSOCB ADC
EtWMxSYbCI Digital Compare Signals (ET)
EtWMxIbT
CTR = tRD tIE
Digital Action EtWMxTZIbT
Compare Time-Base CTR = 0
vualifier CTR = tRD
Signals (TB) CTR_Dir (Av) CTR = 0

T1* EtWMxA Dead tWM Trip EtWMxA

EtWMxSYbCO Band Chopper Zone EtWMxB GtIO
T2* EtWMxB (DB) (tC) (TZ)
CTR = CMtA
EvEtxERR (TZ4)
Counter CTR = CMtB EvEtx TZ1 to TZ3 IbtUT
Compare EMUSTOt (TZ6) X-BAR
CTR = CMtC* CtU
(CC) CLOCKFAIL (TZ5)
SYSCTRL
CTR = CMtD*
tIEERR
Digital
* botes:
• T1 / T2 sources: TZ, DC, EtWMxSYbCI 28x RAM/ ECCDBLERR Compare EtWM
• CMtC / CMtD: sources for ET Flash ECC (DC) X-BAR

The event-trigger submodule manages the events generated by the time-base, counter-compare,
and digital-compare submodules for generating an interrupt to the CPU and/or a start of
conversion pulse to the ADC when a selected event occurs.

TMS320F28004x Microcontroller Workshop - Control Peripherals 7 - 31

ePWM

Event-Trigger Interrupts and SOC

TBCTR

. .. . ..
. . . .
TBPRD

. .. .. ..
CMPD

.
CMPC

. . .
CMPB
CMPA

CTR = 0
CTR = PRD
CTR = 0 or PRD
CTRU = CMPA
CTRD = CMPA
CTRU = CMPB
CTRD = CMPB
CTRU = CMPC
CTRD = CMPC
CTRU = CMPD
CTRD = CMPD
DCAEVT1.soc / DCBEVT1.soc generates EPWMxSOCA/B pulse (x = 1 to 8)

These event triggers can occur when the time-base counter equals zero, period, zero or period,
the up or down count match of a compare register. Recall that the digital-compare subsystem
can also generate an ADC start of conversion based on one or more compare events. Notice
counter up and down are independent and separate.

Event-Trigger Driverlib Functions

 Enable / disable Event-Trigger ADC SOC
EPWM_[enable|disable]ADCTrigger(base, adcSOCType);

 Set Event-Trigger ADC SOC source

EPWM_setADCTriggerSource(base, adcSOCType, socSource);

 Set Event-Trigger ADC SOC prescale

EPWM_setADCTriggerEventPrescale(base, adcSOCType,
preScaleCount);

 base is the ePWM base address: EPWMx_BASE (x = 1 to 8)

 adcSOCType value is: EPWM_SOC_x (x = A or B)
 socSource value is:
 EPWM_SOC_DCxEVT1 (x = A or B)
 EPWM_SOC_TBCTR_x (x = ZERO, PERIOD, ZERO_OR_PERIOD)
 EPWM_SOC_TBCTR_U_CMPx (x = A, B, C, or D)
 EPWM_SOC_TBCTR_D_CMPx (x = A, B, C, or D)
 preScaleCount value is: 1 to 15 (0 disables the prescale)

7 - 32 TMS320F28004x Microcontroller Workshop - Control Peripherals

 ePWM

The event-trigger submodule also incorporates pre-scaling logic to issue an interrupt request or
ADC start of conversion at every event or up to every fifteenth event.

Event-Trigger Driverlib Functions

 Enable / disable Event-Trigger interrupt
EPWM_[enable|disable]Interrupt(base);

 Set Event-Trigger interrupt source

EPWM_setInterruptSource(base, interruptSource);

 Set Event-Trigger interrupt event counts

EPWM_setInterruptEventCount(base, eventCount);

 base is the ePWM base address: EPWMx_BASE (x = 1 to 8)

 interruptSource value is:
 EPWM_INT_TBCTR_x (x = ZERO, PERIOD, ZERO_OR_PERIOD)
 EPWM_INT_TBCTR_U_CMPx (x = A, B, C, or D)
 EPWM_INT_TBCTR_D_CMPx (x = A, B, C, or D)
 eventCount maximum value is: 15 (Determines the number of events that
have to occur before an interrupt is issued)

High Resolution PWM (HRPWM)

High-Resolution PWM (HRPWM)
PWM Period

Regular
Device Clock PWM Step
(i.e. 100 MHz) (i.e. 10 ns)

HRPWM divides a clock Calibration Logic tracks the

cycle into smaller steps number of Micro Steps per
ms ms ms ms ms ms
called Micro Steps clock to account for
(Step Size ~= 150 ps) Calibration Logic variations caused by
Temp/Volt/Process

HRPWM
Micro Step (~150 ps)

 Significantly increases the resolution of conventionally derived digital PWM

 Uses 8-bit extensions to Compare registers (CMPxHR), Period register
(TBPRDHR) and Phase register (TBPHSHR) for edge positioning control
 Typically used when PWM resolution falls below ~9-10 bits which occurs at
frequencies greater than ~200 kHz (with system clock of 100 MHz)
 Not all ePWM outputs support HRPWM feature (see device datasheet)

The ePWM module is capable of significantly increase its time resolution capabilities over the
standard conventionally derived digital PWM. This is accomplished by adding 8-bit extensions to

TMS320F28004x Microcontroller Workshop - Control Peripherals 7 - 33

ePWM

the counter compare register (CMPxHR), period register (TBPRDHR), and phase register
(TBPHSHR), providing a finer time granularity for edge positioning control. This is known as
high-resolution PWM (HRPWM) and it is based on micro edge positioner (MEP) technology. The
MEP logic is capable of positioning an edge very finely by sub-dividing one coarse system clock
of the conventional PWM generator with time step accuracy on the order of 150 picoseconds. A
self-checking software diagnostics mode is used to determine if the MEP logic is running
optimally, under all operating conditions such as for variations caused by temperature, voltage,
and process. HRPWM is typically used when the PWM resolution falls below approximately 9 or
10 bits which occurs at frequencies greater than approximately 200 kHz with an EPWMCLK of
100 MHz.

7 - 34 TMS320F28004x Microcontroller Workshop - Control Peripherals

 eCAP

eCAP
Capture Module (eCAP)

Timer
Trigger

pin
Timestamp
Values

 The eCAP module timestamps transitions on a

capture input pin
 Can be used to measure the time width of a pulse
t1
t2

 Auxiliary PWM generation

The capture units allow time-based logging of external signal transitions. It is used to accurately
time external events by timestamping transitions on the capture input pin. It can be used to
measure the speed of a rotating machine, determine the elapsed time between pulses, calculate
the period and duty cycle of a pulse train signal, and decode current/voltage measurements
derived from duty cycle encoded current/voltage sensors.

Capture units can be configured to trigger an A/D conversion that is synchronized with an
external event. There are several potential advantages to using the capture for this function over
the ADCSOC pin associated with the ADC module. First, the ADCSOC pin is level triggered, and
therefore only low to high external signal transitions can start a conversion. The capture unit
does not suffer from this limitation since it is edge triggered and can be configured to start a
conversion on either rising edges or falling edges. Second, if the ADCSOC pin is held high
longer than one conversion period, a second conversion will be immediately initiated upon
completion of the first. This unwanted second conversion could still be in progress when a
desired conversion is needed. In addition, if the end-of-conversion ADC interrupt is enabled, this
second conversion will trigger an unwanted interrupt upon its completion. These two problems
are not a concern with the capture unit. Finally, the capture unit can send an interrupt request to
the CPU while it simultaneously initiates the A/D conversion. This can yield a time savings when
computations are driven by an external event since the interrupt allows preliminary calculations to
begin at the start-of-conversion, rather than at the end-of-conversion using the ADC end-of-
conversion interrupt. The ADCSOC pin does not offer a start-of-conversion interrupt. Rather,
polling of the ADCSOC bit in the control register would need to be performed to trap the
externally initiated start of conversion.

TMS320F28004x Microcontroller Workshop - Control Peripherals 7 - 35

eCAP

eCAP Module Block Diagram – Capture Mode

ECAP_enableCaptureMode(base);
Delta Mode

Capture 1 Polarity
Register Select 1 Other
Sources

Event Qualifier
Reset Capture 2 Polarity [127:16]
Register Select 2
32-Bit
Event
Time-Stamp
Prescale
Counter
Capture 3 Polarity
Register Select 3 [15:0]

Input
Capture 4 Polarity X-BAR
Hi-Res
Register Select 4
Capture

DMA PIE Continuous / One-shot

Trigger (ECAPx) Capture Control

The eCAP module captures signal transitions on a dedicated input pin and sequentially loads a
32-bit time-base counter value in up to four 32-bit time-stamp capture registers (CAP1 – CAP4).
By using a 32-bit counter, rollover is minimized. Independent edge polarity can be configured as
rising or falling edge, and the module can be run in either one-shot mode for up to four time-
stamp events or continuous mode to capture up to four time-stamp events operating as a circular
buffer. The capture input pin is routed through the Input X-Bar, allowing any GPIO pin on the
device to be used as the input. Also, the input capture signal can be pre-scaled and interrupts
can be generated on any of the four capture events. The time-base counter can be run in either
absolute or difference (delta) time-stamp mode. In absolute mode the counter runs continuously,
whereas in difference mode the counter resets on each capture

7 - 36 TMS320F28004x Microcontroller Workshop - Control Peripherals

 eCAP

eCAP Module Block Diagram – APWM Mode

ECAP_enableAPWMMode(base);

Shadowed
Period
shadow
Period Register mode
immediate Register (CAP3)
mode
(CAP1)

32-Bit PWM
Output
Time-Stamp Compare
X-BAR
Counter Logic

Compare
immediate
mode Register Compare
shadow
(CAP2) Register mode
Shadowed (CAP4)

If the module is not used in capture mode, the eCAP module can be configured to operate as a
single channel asymmetrical PWM module (i.e. time-base counter operates in count-up mode).

eCAP Driverlib Function

 Enable capture or APWM mode
ECAP_enableCaptureMode(base);
ECAP_enableAPWMMode(base);
 Select eCAP input signal
ECAP_selectECAPInput(base, input);
 Stop / start time stamp counter
ECAP_[stop|start]Counter(base);
 base is the eCAP base address: ECAPx_BASE (x = 1 to 7)
 input value is:
 ECAP_INPUT_INPUTXBARx (x = 1 to 16)
 ECAP_INPUT_CANx_INT0 (x = A or B)
 ECAP_INPUT_ECAP_DELAY_CLOCK
 ECAP_INPUT_OUTPUTXBARx (x = 1 to 8)
 ECAP_INPUT_ADC_y_EVENTx (x = 1 to 4) (y = A, B, or C)
 ECAP_INPUT_SDFM1_FLTx_COMPARE_y (x = 1 to 4) (y = LOW,
HIGH, or HIGH_OR_LOW)
 ECAP_INPUT_CMPSSx_CTRIP_y (x = 1 to 7) (y = LOW, HIGH, or
HIGH_OR_LOW)

TMS320F28004x Microcontroller Workshop - Control Peripherals 7 - 37

eCAP

eCAP Driverlib Function

 Enable / disable load of time stamp on capture event (CAP1 –CAP4)
ECAP_[enable|disable]TimeStampCapture(base);
 Set capture mode (continuous/wrap or one-shot/stop mode)
ECAP_setCaptureMode(base, mode, event);
 Sets the capture event polarity (rising or falling edge)
ECAP_setEventPolarity(base, event, polarity);
 Enable / disable counter reset on event (delta / absolute time stamp)
ECAP_[enable|disable]CounterResetOnEvent(base, event);
 Set and enable / disable capture event interrupt source
ECAP_[enable|disable]Interrupt(base, intFlags);
 Set eCAP input event filter prescale counter
ECAP_setEventPrescaler(base, preScalerValue);
 base is the eCAP base address: ECAPx_BASE (x = 1 to 7)
 mode value is: ECAP_CONTINUOUS_CAPTURE_MODE or
ECAP_ONE_SHOT_CAPTURE_MODE
 event value is: ECAP_EVENT_x (x = 1 to 4)
 polarity value is: ECAP_EVNT_RISING_EDGE or ECAP_EVNT_FALLING_EDGE
 intFlags value is: ECAP_ISR_SOURCE_CAPTURE_x (x = EVENT_1, EVENT_2,
EVENT_3, EVENT_4, OVERFLOW, PERIOD, COMPARE)
 preScalerValue value is: 1, 2, …31 (divide is 2x - i.e. 5 is /10; 1 = no prescale)

The capture unit interrupts offer immediate CPU notification of externally captured events. In
situations where this is not required, the interrupts can be masked and flag testing/polling can be
used instead. This offers increased flexibility for resource management. For example, consider a
servo application where a capture unit is being used for low-speed velocity estimation via a
pulsing sensor. The velocity estimate is not used until the next control law calculation is made,
which is driven in real-time using a timer interrupt. Upon entering the timer interrupt service
routine, software can test the capture interrupt flag bit. If sufficient servo motion has occurred
since the last control law calculation, the capture interrupt flag will be set and software can
proceed to compute a new velocity estimate. If the flag is not set, then sufficient motion has not
occurred and some alternate action would be taken for updating the velocity estimate. As a
second example, consider the case where two successive captures are needed before a
computation proceeds (e.g. measuring the width of a pulse). If the width of the pulse is needed
as soon as the pulse ends, then the capture interrupt is the best option. However, the capture
interrupt will occur after each of the two captures, the first of which will waste a small number of
cycles while the CPU is interrupted and then determines that it is indeed only the first capture. If
the width of the pulse is not needed as soon as the pulse ends, the CPU can check, as needed,
the capture registers to see if two captures have occurred, and proceed from there.

7 - 38 TMS320F28004x Microcontroller Workshop - Control Peripherals

 eQEP

eQEP
What is an Incremental Quadrature
Encoder?
A digital (angular) position sensor

photo sensors spaced θ/4 deg. apart

slots spaced θ deg. apart θ/4

light source (LED)
θ

Ch. A

Ch. B
shaft rotation

Incremental Optical Encoder Quadrature Output from Photo Sensors

The eQEP module interfaces with a linear or rotary incremental encoder for determining position,
direction, and speed information from a rotating machine that is typically found in high-
performance motion and position-control systems.

How is Position Determined from

Quadrature Signals?
Position resolution is θ/4 degrees

(00) (11)
increment decrement
(A,B) = counter 10 counter
(10) (01)

Illegal
Ch. A Transitions;
00 generate 11
phase error
interrupt

Ch. B

01

Quadrature Decoder
State Machine

TMS320F28004x Microcontroller Workshop - Control Peripherals 7 - 39

eQEP

A quadrature decoder state machine is used to determine position from two quadrature signals.

eQEP Module Block Diagram

Measure the elapsed time
between the unit position events;
used for low speed measurement
Quadrature
Generate periodic
Capture
interrupts for velocity Quadrature - Direction -
calculations clock mode count mode
Monitors the quadrature
clock to indicate proper
operation of the motion EQEPxA/XCLK
control system
32-Bit Unit EQEPxB/XDIR
Time-Base Quadrature
QEP Decoder EQEPxI
Watchdog
CPUx.SYSCLK EQEPxS

Position/Counter
Compare
Generate the direction and
clock for the position counter
Generate a sync output in quadrature count mode
and/or interrupt on a
position compare match

See the F28004x Driver Library User’s Guide for available functions

The inputs include two pins (QEPA and QEPB) for quadrature-clock mode or direction-count
mode, an index pin (QEPI), and a strobe pin (QEPS). These pins are configured using the GPIO
multiplexer and need to be enabled for synchronous input. In quadrature-clock mode, two square
wave signals from a position encoder are inputs to QEPA and QEPB which are 90 electrical
degrees out of phase. This phase relationship is used to determine the direction of rotation. If
the position encoder provides direction and clock outputs, instead of quadrature outputs, then
direction-count mode can be used. QEPA input will provide the clock signal and QEPB input will
have the direction information. The QEPI index signal occurs once per revolution and can be
used to indicate an absolute start position from which position information is incrementally
encoded using quadrature pulses. The QEPS strobe signal can be connected to a sensor or limit
switch to indicate that a defined position has been reached.

7 - 40 TMS320F28004x Microcontroller Workshop - Control Peripherals

 eQEP

eQEP Module Connections

Ch. A

Quadrature Ch. B
Capture

EQEPxA/XCLK
32-Bit Unit EQEPxB/XDIR
Time-Base
Quadrature
QEP Decoder EQEPxI Index
Watchdog
CPUx.SYSCLK EQEPxS Strobe
from homing sensor

Position/Counter
Compare

The above figure shows a summary of the connections to the eQEP module.

TMS320F28004x Microcontroller Workshop - Control Peripherals 7 - 41

Sigma Delta Filter Module (SDFM)

Sigma Delta Filter Module (SDFM)

Sigma Delta Filter Module (SDFM)
Isolation Boundary
Digital
Isolator
0100111010…

Digital
Isolator

 SDFM is a four-channel digital filter designed specifically for current

measurement and resolver position decoding in motor control applications
 Each channel can receive an independent modulator bit stream
 Bit streams are processed by four individually programmable digital
decimation filters
 Filters include a fast comparator for immediate digital threshold comparisons
for over-current monitoring
 Filter-bypass mode available to enable data logging, analysis, and
customized filtering

The SDFM is a four-channel digital filter designed specifically for current measurement and
resolver position decoding in motor control applications. Each channel can receive an
independent delta-sigma modulator bit stream which is processed by four individually
programmable digital decimation filters. The filters include a fast comparator for immediate digital
threshold comparisons for over-current and under-current monitoring. Also, a filter-bypass mode
is available to enable data logging, analysis, and customized filtering. The SDFM pins are
configured using the GPIO multiplexer. A key benefit of the SDFM is it enables a simple, cost-
effective, and safe high-voltage isolation boundary.

7 - 42 TMS320F28004x Microcontroller Workshop - Control Peripherals

 Sigma Delta Filter Module (SDFM)

SDFM Block Diagram

Isolated Phase Current-Sense Example

TMS320F28004x

SDFM enables galvanic isolation when utilized in conjunction with isolated sigma delta modulators

TMS320F28004x Microcontroller Workshop - Control Peripherals 7 - 43

Lab 7: Control Peripherals

Lab 7: Control Peripherals

 Objective
The objective of this lab exercise is to become familiar with the programming and operation of the
control peripherals and their interrupts. ePWM1A will be setup to generate a 2 kHz, 25% duty
cycle symmetrical PWM waveform. The waveform will then be sampled with the on-chip analog-
to-digital converter and displayed using the graphing feature of Code Composer Studio. Next,
eCAP1 will be setup to detect the rising and falling edges of the waveform. This information will
be used to determine the width of the pulse and duty cycle of the waveform. The results of this
step will be viewed numerically in a memory window.

Lab 7: Control Peripherals

ePWM1
TB Counter
Compare jumper CPU copies
data
Action Qualifier wire ADC memory
result to
RESULT0 buffer during
ADC ISR
Input X-BAR
ADC-
Capture 1 Register INA0

...
Capture 2 Register
Capture 3 Register
Capture 4 Register

eCAP1 View ADC

buffer PWM
ePWM2 triggering samples
ADC on period match
using SOCA trigger every
20 µs (50 kHz) ePWM2 Code Composer
Studio

 Procedure

Open the Project

1. A project named Lab7 has been created for this lab exercise. Open the project by
clicking on Project  Import CCS Projects. The “Import CCS Eclipse Projects”
window will open then click Browse… next to the “Select search-directory” box. Navigate
to: C:\F28004x\Labs\Lab7\project and click Select Folder. Then click
Finish to import the project. All build options have been configured the same as the
previous lab exercise. The files used in this lab exercise are:

7 - 44 TMS320F28004x Microcontroller Workshop - Control Peripherals

 Lab 7: Control Peripherals

Adc.c EPwm_7.c
CodeStartBranch.asm Gpio.c
Dac.c Lab_5_6_7.cmd
DefaultIsr_7.c Main_7.c
device.c SineTable.c
ECap_7.c Watchdog.c

Note: The ECap_7.c file will be added and used with eCAP1 to detect the rising and
falling edges of the waveform in the second part of this lab exercise.

Generate PWM Waveform

2. Open and inspect Gpio.c. Notice the Driverlib functions used to configure ePWM1A as
an output on the GPIO0 pin.
3. Edit EPwm_7.c to configure ePWM1A as described in the objective for this lab exercise
(i.e. generate a 2 kHz, 25% duty cycle symmetrical PWM waveform):
• Set the timebase period and counter compare values by using the #define global
variable names in the beginning of Lab.h, which is located in the Project
Explorer window in the includes folder under /Lab_common/include
• Set the action qualifier to generate the specified waveform
• Enable the timebase count mode to generate a symmetrical PWM waveform
Note that the deadband, PWM chopper, and all trip zone and DC compare actions have
been disabled. Save your work.

Build and Load

4. Click the “Build” button and watch the tools run in the Console window. Check for
errors in the Problems window.
5. Click the “Debug” button (green bug). The CCS Debug perspective view should open,
the program will load automatically, and you should now be at the start of main(). If the
device has been power cycled since the last lab exercise, be sure to configure the boot
mode to EMU_BOOT_RAM using the Scripts menu.

Run the Code – PWM Waveform

6. Using a jumper wire, connect the PWM1A (pin #80) to ADCINA0 (pin #70) on the
LaunchPad. Refer to the following diagram for the pins that need to be connected.

7. Open a memory browser to view some of the contents of the ADC results buffer. The
address label for the ADC results buffer is AdcBuf (type &AdcBuf) in the “Data” memory

TMS320F28004x Microcontroller Workshop - Control Peripherals 7 - 45

Lab 7: Control Peripherals

page. We will be running our code in real-time mode, and we will need to have the
memory window continuously refresh.

8. Run the code (real-time mode). Watch the window update. Verify that the ADC result
buffer contains the updated values.

9. Open and setup a graph to plot a 50-point window of the ADC results buffer.
Click: Tools  Graph  Single Time and set the following values:

Acquisition Buffer Size 50

DSP Data Type 16-bit unsigned integer

Sampling Rate (Hz) 50000

Start Address AdcBuf

Display Data Size 50

Time Display Unit ms

Select OK to save the graph options.

10. The graphical display should show the generated 2 kHz, 25% duty cycle symmetric PWM
waveform. The period of a 2 kHz signal is 500 ms. You can confirm this by measuring the
period of the waveform using the “measurement marker mode” graph feature. Disable
continuous refresh for the graph before taking the measurements. In the graph window
toolbar, left-click on the ruler icon with the red arrow. Note when you hover your mouse
over the icon, it will show “Toggle Measurement Marker Mode”. Move the mouse to
the first measurement position and left-click. Again, left-click on the Toggle
Measurement Marker Mode icon. Move the mouse to the second measurement
position and left-click. The graph will automatically calculate the difference between the
two values taken over a complete waveform period. When done, clear the measurement
points by right-clicking on the graph and select Remove All Measurement Marks.
Then enable continuous refresh for the graph.

Frequency Domain Graphing Feature of Code Composer Studio

11. Code Composer Studio also has the ability to make frequency domain plots. It does this
by using the PC to perform a Fast Fourier Transform (FFT) of the DSP data. Let's make
a frequency domain plot of the contents in the ADC results buffer (i.e. the PWM
waveform).
Click: Tools  Graph  FFT Magnitude and set the following values:

7 - 46 TMS320F28004x Microcontroller Workshop - Control Peripherals

 Lab 7: Control Peripherals

Acquisition Buffer Size 50

DSP Data Type 16-bit unsigned integer

Sampling Rate (Hz) 50000

Start Address AdcBuf

Data Plot Style Bar

FFT Order 10

Select OK to save the graph options.

12. On the plot window, hold the mouse left-click key and move the marker line to observe
the frequencies of the different magnitude peaks. Do the peaks occur at the expected
frequencies?
13. Halt the code.

Setup eCAP1 to Measure Width of Pulse

The first part of this lab exercise generated a 2 kHz, 25% duty cycle symmetric PWM
waveform which was sampled with the on-chip analog-to-digital converter and displayed
using the graphing feature of Code Composer Studio. Next, eCAP1 will be setup to detect
the rising and falling edges of the waveform. This information will be used to determine the
period and duty cycle of the waveform. The results of this step will be viewed numerically in
a memory window and can be compared to the results obtained using the graphing features
of Code Composer Studio.

14. Add (copy) ECap_7.c to the project from C:\F28004x\Labs\Lab7\source.

15. In Main_7.c, add code to call the InitECap()function. There are no passed
parameters or return values, so the call code is simply:
InitECap();
16. In Gpio.c and notice the Driverlib functions for configuring GPIO24 as the input. Next,
notice the Driverlib function setting GPIO24 as the signal source for Input X-BAR
INPUT7. The GPIO24 pin via INPUT7 will be routed as the input to eCAP1.
17. Open DefaultIsr_7.c and locate the eCAP1 interrupt service routine (ecap1ISR).
Notice that PwmDuty is calculated by CAP2 – CAP1 (rising to falling edge) and that
PwmPeriod is calculated by CAP3 – CAP1 (rising to rising edge).
18. Open and edit ECap_7.c to:
• Set the event polarity to capturing the rising and falling edges of the PWM
waveform in order to calculate the PWM duty and PWM period
• Enable eCAP interrupt after three (3) capture events
Also, notice the Driverlib function that is used to select Input X-BAR INPUT7 as the
source for eCAP1. In Gpio.c the GPIO24 pin has been configured as the source for
INPUT7.
19. Using the “PIE Interrupt Assignment Table” find the location for the eCAP1 interrupt
“INT_ECAP1” and fill in the following information:

PIE group #: # within group:

TMS320F28004x Microcontroller Workshop - Control Peripherals 7 - 47

Lab 7: Control Peripherals

This information will be used in the next step.

20. Modify the end of ECap_7.c to do the following:
• Add the Driverlib function to re-map the ECAP1 interrupt signal to call the ISR
function. (Hint: #define name in driverlib/inc/hw_ints.h and label name
in DefaultIsr_7.c)
• Add the Driverlib function to enable the appropriate PIEIER and core IER

Build and Load

21. Save all changes to the files and build the project by clicking Project  Build
Project, or by clicking on the “Build” button if you have added it to the tool bar. Select
Yes to “Reload the program automatically”.

Run the Code – Pulse Width Measurement

22. Using a jumper wire, connect the ePWM1A (pin #80) to eCAP1 (pin #55, feed from the
Input X-BAR using GPIO24) on the LaunchPad. Refer to the following diagram for the
pins that need to be connected.

23. Open a memory browser to view the address label PwmPeriod. (Type &PwmPeriod in
the address box). The address label PwmDuty (address &PwmDuty) should appear in
the same memory browser window. Scroll the window up, if needed.

24. Set the memory browser properties format to “32-Bit UnSigned Int”. We will be running
our code in real-time mode, and we will need to have the memory browser continuously
refresh.

25. Run the code (real-time mode). Notice the values for PwmDuty and PwmPeriod.

26. Halt the code.

Questions:
• How do the captured values for PwmDuty and PwmPeriod relate to the compare register
and time-base period settings for ePWM1A?
• What is the value of PwmDuty in memory?

• What is the value of PwmPeriod in memory?

• How does it compare with the expected value?

7 - 48 TMS320F28004x Microcontroller Workshop - Control Peripherals

 Lab 7: Control Peripherals

Internal Pulse Width Measurement Using Input X-BAR

27. Modify Gpio.c to use GPIO0 as the signal source to Input X-BAR INPUT7 rather than
GPIO24. (Hint: you only need to modify the Input X-BAR Driverlib function). Recall that
in Gpio.c ePWM1A has been configured as an output on the GPIO0 pin. This
modification will internally route the PWM output as the input to the eCAP1. Therefore,
remove the jumper wire since it is not needed.

28. Save all changes and build the project. Select Yes to “Reload the program
automatically”.

29. Run the code (real-time mode) and verify that the results are the same.

30. Halt the code.

Modulate the PWM Waveform

Next, we will experiment with the code by observing the effects of changing the ePWM1 CMPA
register using real-time emulation. Be sure that the jumper wire is connecting PWM1A (pin #80)
to ADCINA0 (pin #70), and the Single Time graph is displayed. The graph must be enabled for
continuous refresh.

31. Run the code (real-time mode).

32. Open the Registers window by clicking: View  Registers

33. In the Registers window scroll down and expand “EPwm1Regs”. Then scroll down and
expand “CMPA”. In the Value field for “CMPA” right-click and set the Number Format to
Decimal. The Registers window must be enabled for continuous refresh.

34. Change the “CMPA” 18750 value (within a range of 2500 and 22500). Notice the effect
on the PWM waveform in the graph. Also, notice the value for PwmDuty changes in the
Memory Browser window.

You have just modulated the PWM waveform by manually changing the CMPA value. Next, we
will modulate the PWM automatically by having the ADC ISR change the CMPA value.

35. In DefaultIsr_7.c notice the code in the ADCA1 interrupt service routine used to
modulate the PWM1A output between 10% and 90% duty cycle

36. In Main_7.c add “PWM_MODULATE” to the Expressions window. Simply highlight

PWM_MODULATE with the mouse, right click and select “Add Watch Expression…”
and then select OK. The global variable PWM_MODULATE should now be in the
Expressions window with a value of “0”.

37. With the code still running in real-time mode, change the “PWM_MODULATE” from “0” to
“1” and observe the PWM waveform in the graph. The value for PwmDuty will update
continuously in the Memory Browser window. Also, in the Registers window notice the
CMPA value being continuously updated.

38. Halt the code.

Terminate Debug Session and Close Project

39. Terminate the active debug session using the Terminate button. This will close the
debugger and return Code Composer Studio to the CCS Edit perspective view.

TMS320F28004x Microcontroller Workshop - Control Peripherals 7 - 49

Lab 7: Control Peripherals

40. Next, close the project by right-clicking on Lab7 in the Project Explorer window and
select Close Project.

End of Exercise

7 - 50 TMS320F28004x Microcontroller Workshop - Control Peripherals

 Direct Memory Access
Introduction
This module explains the operation of the direct memory access (DMA) controller. The DMA has
six channels with independent PIE interrupts.

Module Objectives
Module Objectives

 Understand the operation of the

Direct Memory Access (DMA)
controller
 Show how to use the DMA to transfer
data between peripherals and/or
memory without intervention from
the CPU

TMS320F28004x Microcontroller Workshop - Direct Memory Access 8-1

Direct Memory Access (DMA)

Chapter Topics
Direct Memory Access................................................................................................................ 8-1
Direct Memory Access (DMA) ................................................................................................... 8-3
Basic Operation ..................................................................................................................... 8-4
DMA Examples ..................................................................................................................... 8-6
Channel Priority Modes ......................................................................................................... 8-9
DMA Throughput ................................................................................................................. 8-10
DMA Driverlib Functions ..................................................................................................... 8-11
Lab 8: Servicing the ADC with DMA ....................................................................................... 8-13

8-2 TMS320F28004x Microcontroller Workshop - Direct Memory Access

 Direct Memory Access (DMA)

Direct Memory Access (DMA)

DMA Triggers, Sources, and Destinations
PIE
DINTCH1-6 CAN
ADC
Result LIN
Registers
SPI
PMBus
DMA
FSI
GS0 RAM 6-channels
SDFM
Triggers
GS3 RAM
ePWM
ADCA/B/C(INT1-4, EVT) eCAP
XINT(1-5) TINT(0-2) eQEP
EPWM1-8(SOCA-B)
ECAP1-7 SD1FLT(1-4) CMPSS
SPITX/RX(A/B)
CANAIF/CANBIF(1-3) PGA
LINATX/RX
FSITXA/FSIRXA DAC
software

The DMA module provides a hardware method of transferring data between peripherals and/or
memory without intervention from the CPU, effectively freeing up the CPU for other functions.
Using the DMA is ideal when an application requires a significant amount of time spent moving
large amounts of data from off-chip peripheral to on-chip memory, or from a peripheral such as
the ADC result register to a memory RAM block, or between two peripherals. Additionally, the
DMA is capable of rearranging the data for optimal CPU processing such as binning and “ping-
pong” buffering.

Specifically, the DMA can read data from the ADC result registers, transfer to or from memory
blocks G0 through G3, transfer to or from the various peripherals, and also modify registers in the
ePWM. A DMA transfer is started by a peripheral or software trigger. There are six independent
DMA channels, where each channel can be configured individually and each DMA channel has
its own unique PIE interrupt for CPU servicing. All six DMA channels operate the same way,
except channel 1 can be configured at a higher priority over the other five channels. At its most
basic level the DMA is a state machine consisting of two nested loops and tightly coupled
address control logic which gives the DMA the capability to rearrange the blocks of data during
the transfer for post processing. When a DMA transfers is completed, the DMA can generate an
interrupt.

TMS320F28004x Microcontroller Workshop - Direct Memory Access 8-3

Direct Memory Access (DMA)

Basic Operation
DMA Definitions
 Word
 16 or 32 bits
 Word size is configurable per DMA channel
 Burst
 Consists of multiple words
 Smallest amount of data transferred at one time
 Burst Size
 Number of words per burst
 Specified by BURST_SIZE register
 5-bit ‘N-1’ value (maximum of 32 words/burst)

 Transfer
 Consists of multiple bursts
 Transfer Size
 Number of bursts per transfer
 Specified by TRANSFER_SIZE register
 16-bit ‘N-1’ value - exceeds any practical requirements

Simplified State Machine Operation

The DMA state machine at its most basic
level is two nested loops

Start Transfer

Move Word

Burst Size times

Transfer Size times

DMA can be configured to

End Transfer re-initialize at the end of the
transfer (continuous mode)

8-4 TMS320F28004x Microcontroller Workshop - Direct Memory Access

 Direct Memory Access (DMA)

Basic Address Control Registers

32
SRC_ADDR
Active pointers
DST_ADDR

Pointer shadow registers SRC_ADDR_SHADOW

copied to active pointers at
start of transfer DST_ADDR_SHADOW

Signed value added to active SRC_BURST_STEP

pointer after each word DST_BURST_STEP

Signed value added to active SRC_TRANSFER_STEP

pointer after each burst DST_TRANSFER_STEP

Simplified State Machine Example

3 words/burst Start Transfer

2 bursts/transfer
Wait for event
to start/continue
transfer

Read/Write Data

Moved N Add Burst Step

“Burst Size” to Address
Words? Pointer
Y

Moved N Add Transfer

“Transfer Size” Step to Address
Bursts? Pointer
Y

End Transfer

TMS320F28004x Microcontroller Workshop - Direct Memory Access 8-5

Direct Memory Access (DMA)

DMA Interrupts
Mode #1: Start Transfer
Interrupt
at start of Wait for event
transfer to start/continue
transfer

 Each DMA channel has its

own PIE interrupt Read/Write Data
 The mode for each
interrupt can be configured
individually Moved N Add Burst Step
 The CHINTMODE bit in the “Burst Size” to Address
MODE register selects the Words? Pointer
interrupt mode Y

Moved N Add Transfer

“Transfer Size” Step to Address
Bursts? Pointer
Mode #2: Y
Interrupt
at end of
transfer End Transfer

DMA Examples
Simple Example
Objective: Move 4 words from memory location 0xF000 to
memory location 0x4000 and interrupt CPU at end of transfer
BURST_SIZE* 0x0001 2 words/burst
Start Transfer
TRANSFER_SIZE* 0x0001 2 bursts/transfer

* Size registers are N-1 Wait for event

to start/continue
transfer
Source Registers Addr Value
SRC_ADDR 0x0000F000
0x0000F001
0x0000F002
0x0000F003
0x00000000 0xF000 0x1111 Read/Write Data

0xF001 0x2222
SRC_ADDR_SHADOW 0x0000F000 Moved Add Burst Step
0xF002 0x3333 N
SRC_BURST_STEP 0x0001 “Burst Size” to Address
0xF003 0x4444 Words? Pointer
SRC_TRANSFER_STEP 0x0001
Y

Moved N Add Transfer

Destination Registers Addr Value “Transfer Size” Step to Address
Bursts? Pointer
DST_ADDR 0x00000000
0x00004000
0x00004001
0x00004002
0x00004003 0x4000 0x0000
0x1111 Y
0x4001 0x0000
0x2222 Interrupt to PIE
DST_ADDR_SHADOW 0x00004000
0x4002 0x0000
0x3333
DST_BURST_STEP 0x0001 End Transfer
0x4003 0x0000
0x4444
DST_TRANSFER_STEP 0x0001

Note: This example could also have been done using 1 word/burst and 4 bursts/transfer, or 4 words/burst
and 1 burst/transfer. This would affect Round-Robin progression, but not interrupts.

8-6 TMS320F28004x Microcontroller Workshop - Direct Memory Access

 Direct Memory Access (DMA)

Data Binning Example

Objective: Bin 3 samples of 5 ADC channels, then interrupt the CPU
GS1 RAM

0xF000
CH0 0xF001
ADCA Results
0xF002
1nd
23rd
st Conversion
Conversion Sequence
Sequence 0xF003
CH1 0xF004
0x0B00 CH0 0xF005
0x0B01 CH1 0xF006
0x0B02 CH2 CH2 0xF007
0x0B03 CH3 0xF008
0x0B04 CH4 0xF009
CH3 0xF00A
0xF00B
0xF00C
CH4 0xF00D
0xF00E

Data Binning Example Register Setup

Objective: Bin 3 samples of 5 ADC channels, then interrupt the CPU

ADC Registers:
SOC0 – SOC4 configured to CH0 – CH4, respectively,
ADCA configured to re-trigger (continuous conversion)

GS1 RAM
DMA Registers:
BURST_SIZE* 0x0004 5 words/burst 0xF000 CH0
TRANSFER_SIZE* 0x0002 3 bursts/transfer 0xF001 CH0
0xF002 CH0
SRC_ADDR_SHADOW 0x00000B00 0xF003 CH1
ADCA Results
SRC_BURST_STEP 0x0001 CH1
0xF004
SRC_TRANSFER_STEP 0xFFFC (-4) CH0 CH1
0x0B00 0xF005
DST_ADDR_SHADOW 0x0000F000 starting address** 0x0B01 CH1 0xF006 CH2
DST_BURST_STEP 0x0003 0x0B02 CH2 0xF007 CH2
DST_TRANSFER_STEP 0xFFF5 (-11) 0x0B03 CH3 0xF008 CH2
0x0B04 CH4 0xF009 CH3
0xF00A CH3
0xF00B CH3
0xF00C CH4
0xF00D CH4
* Size registers are N-1 0xF00E CH4
** Typically use a relocatable symbol in your code, not a hard value

TMS320F28004x Microcontroller Workshop - Direct Memory Access 8-7

Direct Memory Access (DMA)

Ping-Pong Buffer Example

Objective: Buffer ADC ch. 0 ping-pong style, 50 samples per buffer

ADCA Result Register GS0 RAM

0x0B00 ADCRESULT0 0xC140

SOC0 configured to ADCINA0

with 1 conversion per trigger 50 word
‘Ping’ buffer

DMA
Interrupt

50 word
‘Pong’ buffer

DMA
Interrupt

Ping-Pong Example Register Setup

Objective: Buffer ADC ch. 0 ping-pong style, 50 samples per buffer

ADC Registers:
Convert ADCA Channel ADCINA0 – 1 conversion per trigger (i.e. ePWM2SOCA)

DMA Registers: Start Transfer

BURST_SIZE* 0x0000 1 word/burst

0x0031 Wait for event to
TRANSFER_SIZE* 50 bursts/transfer start/continue transfer

SRC_ADDR_SHADOW 0x00000B00 starting address Read/Write Data

SRC_BURST_STEP don’t care since BURST_SIZE = 0
Moved N Add Burst Step
SRC_TRANSFER_STEP 0x0000 “Burst Size” to Address
Words? Pointer
Y
DST_ADDR_SHADOW 0x0000C140 starting address**
DST_BURST_STEP don’t care since BURST_SIZE = 0 Moved N Add Transfer Step
“Transfer Size” to Address Pointer
DST_TRANSFER_STEP 0x0001 Bursts?
Y

Other: DMA configured to re-init after transfer (CONTINUOUS = 1) End Transfer

* Size registers are N-1

** DST_ADDR_SHADOW must be changed between ping and pong buffer address in
the DMA ISR. Typically use a relocatable symbol in your code, not a hard value.

8-8 TMS320F28004x Microcontroller Workshop - Direct Memory Access

 Direct Memory Access (DMA)

Channel Priority Modes

Channel Priority Modes
 Round Robin Mode:
 All channels have equal priority DMA Y
 After each enabled channel has event?
transferred a burst of words, the
next enabled channel is serviced
in round robin fashion CH6 N CH1
 Channel 1 High Priority Mode:
 Same as Round Robin except CH1
can interrupt DMA state machine
 If CH1 trigger occurs, the current
word (not the complete burst) on
any other channel is completed CH5 CH2
and execution is halted
 CH1 is serviced for complete burst
 When completed, execution
returns to previous active channel
 This mode is intended primarily CH4 CH3
for the ADC, but can be used by
any DMA event configured to
trigger CH1

Priority Modes and the State Machine

Start Transfer Point where other
pending channels
are serviced
Wait for event
to start/continue
transfer

Read/Write Data
Point where
CH1 can
interrupt other
Moved N Add Burst Step
channels in
“Burst Size” to Address
CH1 Priority Mode
Words? Pointer
Y

Moved N Add Transfer

“Transfer Size” Step to Address
Bursts? Pointer
Y

End Transfer

TMS320F28004x Microcontroller Workshop - Direct Memory Access 8-9

Direct Memory Access (DMA)

DMA Throughput
DMA Throughput
4 cycles/word
1 cycle delay to start each burst
1 cycle delay returning from CH1
high priority interrupt
 32-bit transfer doubles throughput
Example: 128 16-bit words from ADC to RAM
8 bursts * [(4 cycles/word * 16 words/burst) + 1] = 520 cycles

Example: 64 32-bit words from ADC to RAM

8 bursts * [(4 cycles/word * 8 words/burst) + 1] = 264 cycles

DMA vs. CPU Access Arbitration

 DMA has priority over CPU
 Ifa multi-cycle CPU access is already in
progress, DMA stalls until current CPU
access finishes
 The DMA will interrupt back-to-back CPU
accesses
 Can the CPU be locked out?
 Generally No!
 DMA is multi-cycle transfer; CPU will sneak
in an access when the DMA is accessing the
other end of the transfer (e.g. while DMA
accesses destination location, the CPU can
access the source location)

8 - 10 TMS320F28004x Microcontroller Workshop - Direct Memory Access

 Direct Memory Access (DMA)

DMA Driverlib Functions

DMA Driverlib Functions
 Initialize the DMA controller (hard reset)
DMA_initController();
 Set DMA channel priority mode (round-robin or CH1 high priority)
DMA_setPriorityMode(ch1IsHighPri);
 Configures the DMA channel trigger and mode
DMA_configMode(base, trigger, config);
 Enable /disable peripheral trigger for DMA transfer
DMA_[enable|disable]Trigger(base);
 Start / stop DMA channel (‘start’ – wait for first trigger event)
DMA_[start|stop]Channel(base);

 ch1IsHighPri value is ‘false’ for round-robin or ‘true’ for CH1 high priority
 base is the DMA channel base address: DMA_CHx_BASE (x = 1 to 6)
 trigger value is located in dma.h – see table on next slide for values
 config value is the logical OR of:
 DMA_CFG_ONESHOT_x (x = DISABLE or ENABLE)
 DMA_CFG_CONTINUOUS_x (x = DISABLE or ENABLE)
 DMA_CFG_SIZE_xBIT (x = 16 or 32)

Peripheral Interrupt Trigger Sources

DMA_configMode(base, trigger, config);

DMA_TRIGGER_SOFTWARE DMA_TRIGGER_XINT2 DMA_TRIGGER_EPWM7SOCB DMA_TRIGGER_SPIATX

DMA_TRIGGER_ADCA1 DMA_TRIGGER_XINT3 DMA_TRIGGER_EPWM8SOCA DMA_TRIGGER_SPIARX

DMA_TRIGGER_ADCA2 DMA_TRIGGER_XINT4 DMA_TRIGGER_EPWM8SOCB DMA_TRIGGER_SPIBTX

DMA_TRIGGER_ADCA3 DMA_TRIGGER_XINT5 DMA_TRIGGER_TINT0 DMA_TRIGGER_SPIBRX

DMA_TRIGGER_ADCA4 DMA_TRIGGER_EPWM1SOCA DMA_TRIGGER_TINT1 DMA_TRIGGER_LINATX

DMA_TRIGGER_ADCAEVT DMA_TRIGGER_EPWM1SOCB DMA_TRIGGER_TINT2 DMA_TRIGGER_LINARX

DMA_TRIGGER_ADCB1 DMA_TRIGGER_EPWM2SOCA DMA_TRIGGER_ECAP1 DMA_TRIGGER_FSITXA

DMA_TRIGGER_ADCB2 DMA_TRIGGER_EPWM2SOCB DMA_TRIGGER_ECAP2 DMA_TRIGGER_FSIRXA

DMA_TRIGGER_ADCB3 DMA_TRIGGER_EPWM3SOCA DMA_TRIGGER_ECAP3 DMA_TRIGGER_CANAIF1

DMA_TRIGGER_ADCB4 DMA_TRIGGER_EPWM3SOCB DMA_TRIGGER_ECAP4 DMA_TRIGGER_CANAIF2

DMA_TRIGGER_ADCBEVT DMA_TRIGGER_EPWM4SOCA DMA_TRIGGER_ECAP5 DMA_TRIGGER_CANAIF3

DMA_TRIGGER_ADCC1 DMA_TRIGGER_EPWM4SOCB DMA_TRIGGER_ECAP6 DMA_TRIGGER_CANBIF1

DMA_TRIGGER_ADCC2 DMA_TRIGGER_EPWM5SOCA DMA_TRIGGER_ECAP7 DMA_TRIGGER_CANBIF2

DMA_TRIGGER_ADCC3 DMA_TRIGGER_EPWM5SOCB DMA_TRIGGER_SDFM1FLT1 DMA_TRIGGER_CANBIF3

DMA_TRIGGER_ADCC4 DMA_TRIGGER_EPWM6SOCA DMA_TRIGGER_SDFM1FLT2

DMA_TRIGGER_ADCCEVT DMA_TRIGGER_EPWM6SOCB DMA_TRIGGER_SDFM1FLT3

DMA_TRIGGER_XINT1 DMA_TRIGGER_EPWM7SOCA DMA_TRIGGER_SDFM1FLT4

TMS320F28004x Microcontroller Workshop - Direct Memory Access 8 - 11

Direct Memory Access (DMA)

DMA Driverlib Functions

 Configure the source and destination addresses of the DMA channel
DMA_configAddresses(base, const void * destAddr, const void *
srcAddr);
 Configures the burst size and the address step size
DMA_configBurst (base, size, srcStep, destStep);
 Configures the transfer size and the address step size
DMA_configTransfer (base, transferSize, srcStep, destStep);
 Set the channel interrupt mode
DMA_setInterruptMode(base, mode);
 Enable / disable DMA channel CPU interrupt
DMA_[enable|disable]Interrupt (base);

 base is the DMA channel base address: DMA_CHx_BASE (x = 1 to 6)

 destAddr is a pointer to the destination address
 srcAddr is a pointer to the source address
 size values is the number of words per burst (range from 1 to 32 words)
 srcStep and destStep value is the step size (signed values from -4096 to 4095)
 transferSize value is the number of bursts per transfer (max value of 65536)
 mode value is: DMA_INT_AT_BEGINNING or DMA_INT_AT_END

8 - 12 TMS320F28004x Microcontroller Workshop - Direct Memory Access

 Lab 8: Servicing the ADC with DMA

Lab 8: Servicing the ADC with DMA

 Objective
The objective of this lab exercise is to become familiar with operation of the DMA. In the previous
lab exercise, the CPU was used to store the ADC conversion result in the memory buffer during
the ADC ISR. In this lab exercise the DMA will be configured to transfer the results directly from
the ADC result registers to the memory buffer. ADC channel A0 will be buffered ping-pong style
with 50 samples per buffer. As an operational test, the 2 kHz, 25% duty cycle symmetric PWM
waveform (ePWM1A) will be displayed using the graphing feature of Code Composer Studio.

Lab 8: Servicing the ADC with DMA

ePWM1 ADC DMA

TB Counter ADCINA0 RESULT0
Compare
Action Qualifier
jumper
wire ping
data
memory
ePWM2 triggering ADC on period pong
match using SOCA trigger every
20 µs (50 kHz)
ePWM2 CPU writes data
to AdcBuf during
DMA ISR

data
Objective: memory
Configure the DMA to buffer Display
ADCA Channel A0 ping-pong using CCS
style with 50 samples per buffer

 Procedure

Open the Project

1. A project named Lab8 has been created for this lab exercise. Open the project by
clicking on Project  Import CCS Projects. The “Import CCS Eclipse Projects”
window will open then click Browse… next to the “Select search-directory” box. Navigate
to: C:\F28004x\Labs\Lab8\project and click Select Folder. Then click
Finish to import the project. All build options have been configured the same as the
previous lab exercise. The files used in this lab exercise are:

TMS320F28004x Microcontroller Workshop - Direct Memory Access 8 - 13

Lab 8: Servicing the ADC with DMA

Adc.c EPwm.c
CodeStartBranch.asm Gpio.c
Dac.c Lab_8.cmd
DefaultIsr_8.c Main_8.c
device.c SineTable.c
Dma_8.c Watchdog.c
ECap.c

Inspect Lab_8.cmd
2. Open and inspect Lab_8.cmd. Notice that a section called “dmaMemBufs” is being
linked to RAMGS2. This section links the destination buffer for the DMA transfer to a DMA
accessible memory space. Close the inspected file.

Setup DMA Initialization

The DMA controller needs to be configured to buffer ADC channel A0 ping-pong style with 50
samples per buffer. One conversion will be performed per trigger with the ADC operating in
single sample mode.

3. Edit Dma_8.c to implement the DMA operation as described in the objective for this lab
exercise:
• Enable the peripheral interrupt trigger for channel 1 DMA transfer
• Generate an interrupt at the beginning of a new transfer
• Enable the DMA channel CPU interrupt

Note: the DMA has been configured for an ADC interrupt “ADCA1” to trigger the start of a
DMA CH1 transfer. Additionally, the DMA is set for 16-bit data transfers with one burst
per trigger and auto re-initialization at the end of the transfer. At the end of the code the
channel is enabled to run.

4. Open Main_8.c and add a line of code in main() to call the InitDma() function.
There are no passed parameters or return values. You just type
InitDma();
at the desired spot in main().

Setup PIE Interrupt for DMA

Recall that ePWM2 is triggering the ADC at a 50 kHz rate. In the previous lab exercise, the ADC
generated an interrupt to the CPU, and the CPU read the ADC result register in the ADC ISR.
For this lab exercise, the ADC is instead triggering the DMA, and the DMA will generate an
interrupt to the CPU. The CPU will read the ADC result register in the DMA ISR.

5. Edit Adc.c to comment out the code used to enable the ADCA1 interrupt in PIE group 1.
This is no longer being used. The DMA interrupt will be used instead.

6. Using the “PIE Interrupt Assignment Table” find the location for the DMA Channel 1
interrupt “INT_DMA_CH1” and fill in the following information:

PIE group #: # within group:

This information will be used in the next step.

7. Modify the end of Dma_8.c to do the following:

8 - 14 TMS320F28004x Microcontroller Workshop - Direct Memory Access

 Lab 8: Servicing the ADC with DMA

• Add the Driverlib function to re-map the DMA_CH1 interrupt signal to call the ISR
function. (Hint: #define name in driverlib/inc/hw_ints.h and label name
in DefaultIsr_8.c)
• Add the Driverlib function to enable the appropriate PIEIER and core IER
8. Inspect DefaultIsr_8.c and notice that this file contains the DMA interrupt service
routine which implements the ping-pong style buffer. Save all modified files.

Build and Load

9. Click the “Build” button and watch the tools run in the Console window. Check for
errors in the Problems window.
10. Click the “Debug” button (green bug). The CCS Debug perspective view should open,
the program will load automatically, and you should now be at the start of main(). If the
device has been power cycled since the last lab exercise, be sure to configure the boot
mode to EMU_BOOT_RAM using the Scripts menu.

Run the Code – Test the DMA Operation

Note: For the next step, check to be sure that the jumper wire connecting PWM1A (pin #80) to
ADCINA0 (pin #70) is in place on the LaunchPad.

11. Run the code (real-time mode). Open and watch the memory browser update. Verify
that the ADC result buffer contains updated values.

12. Open and setup a graph to plot a 50-point window of the ADC results buffer.
Click: Tools  Graph  Single Time and set the following values:

Acquisition Buffer Size 50

DSP Data Type 16-bit unsigned integer

Sampling Rate (Hz) 50000

Start Address AdcBuf

Display Data Size 50

Time Display Unit µs

Select OK to save the graph options.

13. The graphical display should show the generated 2 kHz, 25% duty cycle symmetric PWM
waveform. Notice that the results match the previous lab exercise.
14. Halt the code.

Terminate Debug Session and Close Project

15. Terminate the active debug session using the Terminate button. This will close the
debugger and return Code Composer Studio to the CCS Edit perspective view.

TMS320F28004x Microcontroller Workshop - Direct Memory Access 8 - 15

Lab 8: Servicing the ADC with DMA

16. Next, close the project by right-clicking on Lab8 in the Project Explorer window and
select Close Project.

End of Exercise

8 - 16 TMS320F28004x Microcontroller Workshop - Direct Memory Access

 Control Law Accelerator
Introduction
This module explains the operation of the control law accelerator (CLA). The CLA is an
independent, fully programmable, 32-bit floating-point math processor. It executes algorithms
independently and in parallel with the CPU. This extends the capabilities of the C28x CPU by
adding parallel processing. The CLA has direct access to the ADC result registers. Additionally,
the CLA has access to all ePWM, high-resolution PWM, eCAP, eQEP, CMPSS, DAC, SDFM,
PGA, SPI, LIN, FSI, PMBUS, CLB and GPIO data registers. This allows the CLA to read ADC
samples “just-in-time” and significantly reduces the ADC sample to output delay enabling faster
system response and higher frequency operation. The CLA responds to peripheral interrupts
independently of the CPU. Utilizing the CLA for time-critical tasks frees up the CPU to perform
other system, diagnostics, and communication functions concurrently. Additionally, the CLA has
the capability of running a background task.

Module Objectives
Module Objectives

 Explain the purpose and operation of the

Control Law Accelerator (CLA)
 Describe the CLA initialization procedure
 Review the CLA registers, instruction set,
and programming flow

TMS320F28004x Microcontroller Workshop - Control Law Accelerator 9-1

Control Law Accelerator (CLA)

Chapter Topics
Control Law Accelerator............................................................................................................. 9-1
Control Law Accelerator (CLA) ................................................................................................. 9-3
CLA Block Diagram ............................................................................................................... 9-4
CLA Tasks ............................................................................................................................. 9-4
CLA Memory and Register Access ....................................................................................... 9-5
CLA Control and Execution Registers .................................................................................. 9-6
Task Trigger .......................................................................................................................... 9-6
Software Trigger .................................................................................................................... 9-7
Background Task .................................................................................................................. 9-8
Memory Configuration ........................................................................................................... 9-9
Task Vector ......................................................................................................................... 9-10
CLA Initialization ................................................................................................................. 9-10
Enabling CLA Support in CCS ............................................................................................ 9-11
CLA Task C Programming .................................................................................................. 9-11
C2000Ware – CLA Software Support ................................................................................. 9-13
CLA Compiler Scratchpad Memory Area ............................................................................ 9-13
CLA Initialization Code Example ......................................................................................... 9-14
CLA Task C Code Example ................................................................................................ 9-14
CLA Code Debugging ......................................................................................................... 9-15
Lab 9: CLA Floating-Point FIR Filter ....................................................................................... 9-16

9-2 TMS320F28004x Microcontroller Workshop - Control Law Accelerator

 Control Law Accelerator (CLA)

Control Law Accelerator (CLA)

Control Law Accelerator (CLA)

C28x CPU
ADC PWM
CLA

 The CLA is a 32-bit floating-point processor that responds

to peripheral triggers and executes code independent of
the main CPU
 Designed for fast trigger response and oriented toward
math computations
 Direct access to ePWM, HRPWM, eCAP, eQEP, ADC, DAC,
CMPSS, PGA, SDFM, SPI, LIN, FSI, PMBus, CLB, and GPIO
 Frees up the CPU for other tasks (communications,
systems, and diagnostics)

The CLA is an independent 32-bit floating-point math hardware accelerator which executes real-
time control algorithms in parallel with the main C28x CPU, effectively doubling the computational
performance. The CLA responds directly to peripheral triggers, which can free up the C28x CPU
for other tasks, such as communications and diagnostics. With direct access to the various
control and communication peripherals, the CLA minimizes latency, enables a fast trigger
response, and avoids CPU overhead. Also, with direct access to the ADC results registers, the
CLA is able to read the result on the same cycle that the ADC sample conversion is completed,
providing “just-in-time” reading, which reduces the sample to output delay.

TMS320F28004x Microcontroller Workshop - Control Law Accelerator 9-3

Control Law Accelerator (CLA)

CLA Block Diagram

CLA Block Diagram
Task Triggers
(Peripheral Interrupts)
Task1 Trigger
Task2 Trigger
Task3 Trigger
Task4 Trigger CLA CLA_INT1-8 INT11 C28x
MPERINT1-8 PIE
Task5 Trigger Control & Execution LVF, LUF INT12 CPU
Registers
Task6 Trigger
Task7 Trigger
Task8 Trigger

CLA Program Bus

CLA Data Bus

Program Data MSG RAMs Registers

CPU to CLA ePWM eCAP ADC GPIO
RAM RAM
CLA to CPU HRPWM eQEP SPI PMBus
CMPSS DAC LIN CLB
SDFM PGA FSI

CLA Tasks
CLA Tasks
Task Triggers
(Peripheral Interrupts)
Task1 Trigger
Task2 Trigger
Task3 Trigger
Task4 Trigger CLA CLA_INT1-8 INT11 C28x
MPERINT1-8 PIE
Task5 Trigger Control & Execution LVF, LUF INT12 CPU
Registers
Task6 Trigger
Task7 Trigger
Task8 Trigger

 A Task is similar to an interrupt service routine

 CLA supports 8 tasks (Task1-8)
 A task is started by a peripheral interrupt trigger
 Triggers are enabled in the CLA1TASKSRCSELx register
 When a trigger occurs the CLA begins execution at
the associated task vector entry (MVECT1-8)
 Once a task begins it runs to completion (no nesting)
 Capable of running a continuous background task

Programming the CLA consists of initialization code, which is performed by the CPU, and tasks.
A task is similar to an interrupt service routine, and once started it runs to completion. Each task

9-4 TMS320F28004x Microcontroller Workshop - Control Law Accelerator

 Control Law Accelerator (CLA)

is capable of being triggered by a variety of peripherals without CPU intervention, which makes
the CLA very efficient since it does not use interrupts for hardware synchronization, nor must the
CLA do any context switching. Unlike the traditional interrupt-based scheme, the CLA approach
becomes deterministic. The CLA supports eight independent tasks and each is mapped back to
an event trigger. Also, the CLA is capable of running a continuous background task. Since the
CLA is a software programmable accelerator, it is very flexible and can be modified for different
applications.

CLA Memory and Register Access

CLA Memory and Register Access
CLA Program Memory Message RAMs
 Contains CLA program code  Used to pass data between
 Mapped to the CPU at reset the CPU and CLA
 Initialized by the CPU  Always mapped to both
the CPU and CLA

LS0 – LS7 RAM LS0 – LS7 RAM PF1, PF2, PF3, and PF8
Program Data MSG RAMs Registers
CPU to CLA ePWM eCAP ADC GPIO
RAM RAM
CLA to CPU HRPWM eQEP SPI PMBus
(2Kw each) (2Kw each) (128w/128w) CMPSS DAC LIN CLB
SDFM PGA FSI

CLA Data Memory

 Contains variables and coefficients
used by the CLA program code Peripheral Register Access
 Mapped to the CPU at reset  Provides direct access to
 Initialized by CPU peripherals

The CLA has access to the LSx RAM blocks and each memory block can be configured to be
either dedicated to the CPU or shared between the CPU and CLA. After reset the memory block
is mapped to the CPU, where it can be initialized by the CPU before being shared with the CLA.
Once it is shared between the CPU and CLA it then can be configured to be either program
memory or data memory. When configured as program memory it contains the CLA program
code, and when configured as data memory it contains the variable and coefficients that are used
by the CLA program code. Additionally, dedicated message RAMs are used to pass data
between the CPU and CLA, and CLA and CPU.

TMS320F28004x Microcontroller Workshop - Control Law Accelerator 9-5

Control Law Accelerator (CLA)

CLA Control and Execution Registers

CLA Control and Execution Registers
CLA1TASKSRCSELx MIFR MIER
• •
•
•
•
• 1
Task CLA_INT1-8
LVF, LUF
CLA INT11 C28x
Source PIE
INT12 CPU
Core
Triggers •
•
•
•
•
• 0
MR0

MIFRC S/W Trigger

MR1
MAR0
MR2
MVECTBGRNDACTIVE MAR1
MVECTBGRND MR3
MPC MVECT1-8
Program Data
Memory CLA Program Bus CLA Data Bus Memory

LSxCLAPGM

 CLA1TASKSRCSELx – Task Interrupt Source Select (Task 1-8)  MPC – 16-bit Program Counter (initialized by
 MVECT1-8 – Task Interrupt Vector (MVECT1/2/3/4/5/6/7/8) appropriate MVECTx register or MVECTBGRND)

 MVECTBGRND – Background Task Vector  MVECTBGRNDACTIVE – saves return address

 LSxCLAPGM – Memory Map Configuration (LS0 – LS7 RAM)  MR0-3 – CLA Floating-Point Result Registers (32 bit)
 MAR0-1 – CLA Auxiliary Registers (16 bit)

Task Trigger
Task Trigger Driverlib Functions
CLA1TASKSRCSELx MIFR MIER
• •
•
•
•
• 1
Task

Source CLA Core

Triggers •
•
•
•
•
• 0

MIFRC S/W Trigger

 Configure the CLA task trigger source (CLA1TASKSRCSELx)

CLA_setTriggerSource(taskNumber, trigger);
 Enable / disable CLA task(s) interrupt(s) (configures MIER)
CLA_[enable|disable]Tasks(base, taskFlags);
 taskNumber parameter indicates which task is being configured:
 CLA_TASK_x (x = 1 to 8)
 trigger parameter is the interrupt trigger source – see next slide
 base is the CLA base address: CLA1_BASE
 taskFlags parameter value is the bitwise OR of:
 CLA_TASKFLAG_x (x = 1 to 8) or CLA_TASKFLAG_ALL

9-6 TMS320F28004x Microcontroller Workshop - Control Law Accelerator

 Control Law Accelerator (CLA)

Task Interrupt Trigger Sources

CLA_setTriggerSource(taskNumber, trigger);

CLA_TRIGGER_SOFTWARE CLA_TRIGGER_ADCCEVT CLA_TRIGGER_TINT1 CLA_TRIGGER_SDFM1DRINT2

CLA_TRIGGER_ADCA1 CLA_TRIGGER_XINT1 CLA_TRIGGER_TINT2 CLA_TRIGGER_SDFM1DRINT3

CLA_TRIGGER_ADCA2 CLA_TRIGGER_XINT2 CLA_TRIGGER_ECAP1INT CLA_TRIGGER_SDFM1DRINT4

CLA_TRIGGER_ADCA3 CLA_TRIGGER_XINT3 CLA_TRIGGER_ECAP2INT CLA_TRIGGER_PMBUSAINT

CLA_TRIGGER_ADCA4 CLA_TRIGGER_XINT4 CLA_TRIGGER_ECAP3INT CLA_TRIGGER_SPITXAINT

CLA_TRIGGER_ADCAEVT CLA_TRIGGER_XINT5 CLA_TRIGGER_ECAP4INT CLA_TRIGGER_SPIRXAINT

CLA_TRIGGER_ADCB1 CLA_TRIGGER_EPWM1INT CLA_TRIGGER_ECAP5INT CLA_TRIGGER_SPITXBINT

CLA_TRIGGER_ADCB2 CLA_TRIGGER_EPWM2INT CLA_TRIGGER_ECAP6INT CLA_TRIGGER_SPIRXBINT

CLA_TRIGGER_ADCB3 CLA_TRIGGER_EPWM3INT CLA_TRIGGER_ECAP7INT CLA_TRIGGER_LINAINT1

CLA_TRIGGER_ADCB4 CLA_TRIGGER_EPWM4INT CLA_TRIGGER_EQEP1INT CLA_TRIGGER_LINAINT0

CLA_TRIGGER_ADCBEVT CLA_TRIGGER_EPWM5INT CLA_TRIGGER_EQEP2INT CLA_TRIGGER_CLA1PROMCRC

CLA_TRIGGER_ADCC1 CLA_TRIGGER_EPWM6INT CLA_TRIGGER_ECAP6INT2 CLA_TRIGGER_FSITXAINT1

CLA_TRIGGER_ADCC2 CLA_TRIGGER_EPWM7INT CLA_TRIGGER_ECAP7INT2 CLA_TRIGGER_FSITXAINT2

CLA_TRIGGER_ADCC3 CLA_TRIGGER_EPWM8INT CLA_TRIGGER_SDFM1INT CLA_TRIGGER_FSIRXAINT1

CLA_TRIGGER_ADCC4 CLA_TRIGGER_TINT0 CLA_TRIGGER_SDFM1DRINT1 CLA_TRIGGER_FSIRXAINT2

 Select ‘CLA_TRIGGER_SOFTWARE’ if task is unused or software triggered (default value)

Software Trigger
Software Triggering a Task
 Tasks can also be started by a software
trigger using the CPU
 Method #1: Write to Interrupt Force Register (MIFRC)
15 - 8 7 6 5 4 3 2 1 0

reserved INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1

CLA_forceTask(base, taskFlags);
 base is the CLA base address: CLA1_BASE
 taskFlags value is the bitwise OR of the tasks:
CLA_TASKFLAG_x (x = 1 to 8) or CLA_TASKFLAG_ALL

 Method #2: Use IACK instruction

CLA_[enable|disable]IACK(base);
 Then trigger the task with the assembly instruction:
asm(" IACK #<Task>");
 For example, to trigger TASK4:
asm(" IACK #0x0008");
 More efficient – function does not require EALLOW

TMS320F28004x Microcontroller Workshop - Control Law Accelerator 9-7

Control Law Accelerator (CLA)

Background Task
Background Task
 Option to run 8 tasks or 7 tasks and 1
background task
 Task 8 can be set to be the background task
 While Tasks 1-7 service peripheral triggers in the foreground
 Runs continuously until disabled or device/soft reset
 Can be triggered by a peripheral or software
 Tasks 1 - 7 can interrupt background task in priority
order (Task1 is highest, Task7 is lowest)
 Can make portions of background task
uninterruptible, if needed
 Background Task Uses:
 Run continuous functions such as communications
and clean-up routines

Background Task Registers

 MVECTBGRND register contains the background task vector
 Branch return address is saved to MVECTBGRNDACTIVE register
 Address gets popped to the MPC when execution returns

MVECTBGRNDACTIVE
MVECTBGRND
MPC MVECT1-8 CLA
Program Core
Memory CLA Program Bus

 Enable / disable background task

CLA_[enable|disable]BackgroundTask(base);
 Start the background task (provided there are no other pending tasks)
CLA_startBackgroundTask(base);
 Enable / disable background task hardware trigger
CLA_[enable|disable]HardwareTrigger(base);
 Trigger source for the background task selected by CLA1TASKSRCSELx
 base is the CLA base address: CLA1_BASE

9-8 TMS320F28004x Microcontroller Workshop - Control Law Accelerator

 Control Law Accelerator (CLA)

Background Task Interrupts

 By default background tasks are interruptible
 Highest priority pending task executes first
 When task completes, and there are no other pending interrupt,
execution returns to the background task
 Sections of background task can be made uninterruptible
 Using compiler intrinsics:
 __disable_interrupts(); // MSETC BGINTM
 __enable_interrupts(); // MCLRC BGINTM
//-------------------------------------------------------------------------
// Task 8 - Background Task
//-------------------------------------------------------------------------
__attribute__((interrupt("background"))) void Cla1Task8 ( void )
{
//
// Code below is interruptible
//
CODE GOES HERE... Specifies that this is a
// “background” task instead
// Make this portion un-interruptible of a regular interrupt
//
__disable_interrupts();
CODE GOES HERE...
__enable_interrupts();
//
// Code below is interruptible
//
CODE GOES HERE...
}

Memory Configuration
Memory Config Driverlib Functions
Program CLA Data
Memory CLA Program Bus Core CLA Data Bus Memory

LSxCLAPGM

 Set the LSx memory RAM configuration (CPU only or CPU & CLA)
MemCfg_setLSRAMMasterSel(ramSection, masterSel);
 Set the CLA memory RAM configuration type (LSx = Data or Program)
MemCfg_setCLAMemType(ramSections, claMemType);
 ramSection parameter value is:
 MEMCFG_SECT_LSx (x = 0 to 7)
 masterSel value is RAM section dedicated to the CPU or shared between the
CPU and the CLA:
 MEMCFG_LSRAMMASTER_CPU_ONLY
 MEMCFG_LSRAMMASTER_CPU_CLA1
 ramSections parameter value is an OR of:
 MEMCFG_SECT_LSx (x = 0 to 7)
 claMemType value is RAM section is configured as CLA data memory or CLA
program memory:
 MEMCFG_CLA_MEM_DATA or MEMCFG_CLA_MEM_PROGRAM

TMS320F28004x Microcontroller Workshop - Control Law Accelerator 9-9

Control Law Accelerator (CLA)

Task Vector
Task Vector Driverlib Functions
 Task interrupt vector registers (MVECT1 to MVECT8)
contain the start address for each task
MVECTBGRNDACTIVE
MVECTBGRND
MPC MVECT1-8 CLA
Program Core
Memory CLA Program Bus

 Map CLA task interrupt vector (MVECTx)

CLA_mapTaskVector(base, claIntVect, claTaskAddr);
 Map CLA background task interrupt vector (MVECTBGRND)
CLA_mapBackgroundTaskVector(base, claTaskAddr);
 base is the CLA base address: CLA1_BASE
 claIntVect parameter is the CLA interrupt vector value:
 CLA_MVECT_x (x = 1 to 8)
 claTaskAddr is the start address of the task code

CLA Initialization
CLA Initialization
Performed by the CPU during software initialization
1. Copy CLA task code from flash to CLA program RAM
2. Initialize CLA data RAMs, as needed
 Populate with data coefficients, constants, etc.

3. Configure the CLA registers

 Enable the CLA clock – SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLA1);
 Populate the CLA task interrupt vectors (MVECT1-8 registers)
 Select the desired task interrupt sources (CLA1TASKSRCSELx registers)
 If desired, enable IACK instruction to start tasks using software
 Map CLA program RAM and data RAMs to CLA space

4. Configure desired CLA task completion interrupts in the PIE

5. Enable CLA task triggers in the MIER register
6. Initialize the desired peripherals to trigger the CLA tasks
Data can passed between the CLA and CPU via message RAMs or allocated CLA Data RAM

9 - 10 TMS320F28004x Microcontroller Workshop - Control Law Accelerator

 Control Law Accelerator (CLA)

Enabling CLA Support in CCS

Enabling CLA Support in CCS
 Set the “Specify CLA support” project option to ‘cla2’
 When creating a new CCS project, choosing a device
variant that has the CLA will automatically select this
option, so normally no user action is required

CLA Task C Programming

CLA Task C Programming
Language Implementation
 Supports C only (no C++ or GCC extension support)
 Different data type sizes than C28x CPU and FPU
TYPE CPU and FPU CLA
char 16 bit 16 bit
short 16 bit 16 bit
int 16 bit 32 bit
long 32 bit 32 bit
long long 64 bit 32 bit
float 32 bit 32 bit
double 32 bit 32 bit
long double 64 bit 32 bit
pointers 32 bit 16 bit

 CLA architecture is designed for 32-bit data types

 16-bit computations incur overhead for sign-extension
 16-bit values mostly used to read/write 16-bit peripheral registers
 There is no SW or HW support for 64-bit integer or floating point

TMS320F28004x Microcontroller Workshop - Control Law Accelerator 9 - 11

Control Law Accelerator (CLA)

CLA Task C Language Restrictions (1 of 2)

 No initialization support for global and static
local variables
int16_t x; // valid
int16_t x=5; // not valid

 Initialized global variables should be declared in a

.c file instead of the .cla file
.c file: .cla file:
int16_t x=5; extern int16_t x;

 For initialized static variables, easiest solution is to

use an initialized global variable instead
 No recursive function calls
 No function pointers

CLA Task C Language Restrictions (2 of 2)

 No support for certain fundamental math
operations
 integer division: z = x/y;
 modulus (remainder): z = x%y;
 unsigned 32-bit integer compares
uint32_t i; if(i < 10) {…} // not valid
int32_t i; if(i < 10) {…} // valid
uint16_t i; if(i < 10) {…} // valid
int16_t i; if(i < 10) {…} // valid
float32_t x; if(x < 10) {…} // valid

 No standard C math library functions, but TI

provides some function examples (next slide)

9 - 12 TMS320F28004x Microcontroller Workshop - Control Law Accelerator

 Control Law Accelerator (CLA)

C2000Ware – CLA Software Support

C2000Ware™ - CLA Software Support
 TI provides some examples of floating-point math CLA functions

Resource Explorer

CLAmath

Examples

CLA Compiler Scratchpad Memory Area

CLA Compiler Scratchpad Memory Area
 For local and compiler generated temporary variables
 Static allocation, used instead of a stack
 Defined in the linker command file
Lab.cmd
MEMORY
{

SECTIONS
{

/*** CLA Compiler Required Sections ***/

.scratchpad : > RAMLS0, PAGE = 1

TMS320F28004x Microcontroller Workshop - Control Law Accelerator 9 - 13

Control Law Accelerator (CLA)

CLA Initialization Code Example

CLA Initialization Code Example
 Defines data types and
Lab.h special registers specific
#include “driverlib.h" // cla.h to the CLA
#include “f28004x_device.h"
 Defines register bit field
structures
extern interrupt void Cla1Task1();
extern interrupt void Cla1Task2();  CLA task prototypes are
prefixed with the
extern interrupt void Cla1Task8(); ‘interrupt’ keyword

 CLA task symbols are

visible to all C28x CPU
Cla.c and CLA code
#include "Lab.h"

// Initialize CLA task interrupt vectors

CLA_mapTaskVector(CLA1_BASE, CLA_MVECT_1, (uint16_t)&Cla1Task1);
CLA_mapTaskVector(CLA1_BASE, CLA_MVECT_2, (uint16_t)&Cla1Task2);

CLA_mapTaskVector(CLA1_BASE, CLA_MVECT_7, (uint16_t)&Cla1Task7);

CLA_mapTaskVector(CLA1_BASE, CLA_MVECT_8, (uint16_t)&Cla1Task8);

CLA Task C Code Example

CLA Task C Code Example
ClaTasks_C.cla

#include "F28004x_device.h"  .cla extension

#include "Lab.h" causes the c2000
;------------------------------------- compiler to invoke
interrupt void Cla1Task1 (void) the CLA compiler
{
 Bit Field peripheral
__mdebugstop1(); address definitions

xDelay[0] = (float32_t)AdcaResultRegs.ADCRESULT0;  All code within this

Y = coeffs[4] * xDelay[4]; file is placed in the
xDelay[4] = xDelay[3]; section “Cla1Prog”

xDelay[1] = xDelay[0];  C Peripheral

Y = Y + coeffs[0] * xDelay[0]; Register Header File
ClaFilteredOutput = (uint16_t)Y; references can be
} used in CLA C and
;------------------------------------- assembly code
interrupt void Cla1Task2 (void)
{  Closing braces are
replaced with
} MSTOP instructions
;------------------------------------- when compiled

9 - 14 TMS320F28004x Microcontroller Workshop - Control Law Accelerator

 Control Law Accelerator (CLA)

CLA Code Debugging

CLA Code Debugging
 The CLA and CPU are debugged from the same JTAG port
 You can halt, single-step, and run the CLA independent of the CPU
1. Insert a breakpoint in the CLA code
 Insert a MDEBUGSTOP1 instruction(s) in the code where desired then rebuild/reload
 In C code, can use asm(“ MDEBUGSTOP1”)
 When the debugger is not connected, the MDEBUGSTOP1 acts like an MNOP
2. Connect to the CLA target in CCS
 This enables CLA breakpoints
3. Run the CPU target
 CLA task will trigger (via peripheral interrupt or software)
 CLA executes instructions until MDEBUGSTOP1 is hit
4. Load the code symbols into the CLA context in CCS
 This allows source-level debug
 Needs to be done only once per debug session unless the .out file changes
5. Debug the CLA code
 Can single-step the code, or run to the next MDEBUGSTOP1 or to the end of the task
 If another task is pending, it will start at the end of the previous task
6. Disconnect the CLA target to disable CLA breakpoints, if desired

Note: when using the legacy MDEBUGSTOP instruction, a CLA single step executes one pipeline cycle,
whereas a CPU single step executes one instruction (and flushes the pipeline); see TRM for details

TMS320F28004x Microcontroller Workshop - Control Law Accelerator 9 - 15

Lab 9: CLA Floating-Point FIR Filter

Lab 9: CLA Floating-Point FIR Filter

 Objective
The objective of this lab exercise is to become familiar with operation and programming of the
CLA. In this lab exercise, the ePWM1A generated 2 kHz, 25% duty cycle symmetric PWM
waveform will be filtered using the CLA. The CLA will directly read the ADC result register and a
task will run a low-pass FIR filter on the sampled waveform. The filtered result will be stored in a
circular memory buffer. Note that the CLA is operating concurrently with the CPU. As an
operational test, the filtered and unfiltered waveforms will be displayed using the graphing feature
of Code Composer Studio.

Lab 9: CLA Floating-Point FIR Filter

ePWM1 ADC CLA

TB Counter RESULT0 Cla1Task1
ADCINA0
Compare Cla1Task2
Action Qualifier
jumper Cla1Task8
wire

ePWM2 triggering ADC on period

match using SOCA trigger every data
20 µs (50 kHz) memory
ePWM2

CPU copies
result to
buffer during
CLA ISR
...
Display
using CCS

Recall that a task is similar to an interrupt service routine. Once a task is triggered it runs to
completion. In this lab exercise two tasks will be used. Task 1 contains the low-pass filter. Task
8 contains a one-time initialization routine that is used to clear (set to zero) the filter delay chain.

 Procedure

Open the Project

1. A project named Lab9 has been created for this lab exercise. Open the project by
clicking on Project  Import CCS Projects. The “Import CCS Eclipse Projects”
window will open then click Browse… next to the “Select search-directory” box. Navigate
to: C:\F28004x\Labs\Lab9\project and click Select Folder. Then click
Finish to import the project. All build options have been configured the same as the
previous lab exercise. The files used in this lab exercise are:

9 - 16 TMS320F28004x Microcontroller Workshop - Control Law Accelerator

 Lab 9: CLA Floating-Point FIR Filter

Adc.c EPwm.c
Cla_9.c f28004x_globalvariabledefs.c
ClaTasks_C.cla f28004x_headers_nonbios.cmd
CodeStartBranch.asm Gpio.c
Dac.c Lab_9.cmd
DefaultIsr_9_10.c Main_9.c
device.c SineTable.c
Dma.c Watchdog.c
ECap.c

Project Build Options and Enabling CLA Support in CCS

2. In this lab exercise the Bit Field Header Files are used for reading the ADC result register
in the CLA task file (ClaTasks_C.cla). We need to setup the include search path to
include the bit field header files. Open the build options by right-clicking on Lab9 in the
Project Explorer window and select “Properties”. Under “C2000 Compiler” select “Include
Options”. In the include search path box that opens (“Add dir to #include search
path”) click the Add icon. Then in the “Add directory path” window type:

${PROJECT_ROOT}/../../f28004x_headers/include

Click OK to include the search path.

Note: from the bit field header files, f28004x_globalvariabledefs.c and

f28004x_headers_nonbios.cmd have already been added to the project.

3. Next, we will confirm that CLA support has been enabled. Under “C2000 Compiler”
select “Processor Options” and notice the “Specify CLA support” is set to cla2. This
is needed to compile and assemble CLA code. Click Apply and Close to save and
close the Properties window.

Inspect Lab_9.cmd
4. Open and inspect Lab_9.cmd. Notice that a section called “Cla1Prog” is being linked
to RAMLS4. This section links the CLA program tasks to the CPU memory space. Two
other sections called “Cla1Data1” and “Cla1Data2” are being linked to RAMLS1 and
RAMLS2, respectively, for the CLA data. These memory spaces will be mapped to the
CLA memory space during initialization. Also, notice the two message RAM sections
used to pass data between the CPU and CLA.
We are linking CLA code directly to the CLA program RAM because we are not yet using
the flash memory. CCS will load the code for us into RAM, and therefore the CPU will
not need to copy the CLA code into the CLA program RAM. In the flash programming lab
exercise later in this workshop, we will modify the linking so that the CLA code is loaded
into flash, and the CPU will do the copy.
5. The CLA C compiler uses a section called .scratchpad for storing local and compiler
generated temporary variables. This scratchpad memory area is allocated using the
linker command file. Notice .scratchpad is being linked to RAMLS0. Close the
Lab_9.cmd linker command file.

Setup CLA Initialization

During the CLA initialization, the CPU memory block RAMLS4 needs to be configured as CLA
program memory. This memory space contains the CLA Task routines. A one-time force of the
CLA Task 8 will be executed to clear the delay buffer. The CLA Task 1 has been configured to

TMS320F28004x Microcontroller Workshop - Control Law Accelerator 9 - 17

Lab 9: CLA Floating-Point FIR Filter

run an FIR filter. The CLA needs to be configured to start Task 1 on the ADCAINT1 interrupt
trigger. The next section will setup the PIE interrupt for the CLA.

6. Open ClaTasks_C.cla and notice Task 1 has been configured to run an FIR filter.
Within this code the ADC result integer (i.e. the filter input) is being first converted to
floating-point, and then at the end the floating-point filter output is being converted back
to integer. Also, notice Task 8 is being used to initialize the filter delay line. The .cla
extension is recognized by the compiler as a CLA C file, and the compiler will generate
CLA specific code.

7. Edit Cla_9.c to implement the CLA operation as described in the objective for this lab
exercise:
• Set Task 1 peripheral interrupt trigger source to ADCA1
• Set Task 8 peripheral interrupt trigger source to SOFTWARE
• Disable the Background Task
• Enable the use of the IACK instruction to trigger a task
• Enable CLA Task 8 interrupt for one-time initialization routine (clear delay buffer)
• Enable CLA Task 1 interrupt

Note: the CLA has been configured for RAMLS0, RAMLS1, RAMLS2, and RAMLS4 memory
blocks to be shared between the CPU and CLA. The RAMLS4 memory block is mapped
to CLA program memory space, and the RAMLS0, RAMLS1 and RAMLS2 memory blocks
are mapped to CLA data memory space. Also, the RAMLS0 memory block is used for the
CLA C compiler scratchpad. Notice that CLA Task 8 interrupt is disabled after the one-
time initialization routine (clear delay buffer) is completed.

8. Open Main_9.c and add a line of code in main() to call the InitCla() function.
There are no passed parameters or return values. You just type
InitCla();

at the desired spot in main().

9. In Main_9.c comment out the line of code in main() that calls the InitDma() function.
The DMA is no longer being used. The CLA will directly access the ADC RESULT0
register.

Setup PIE Interrupt for CLA

Recall that ePWM2 is triggering the ADC at a 50 kHz rate. In the Control Peripherals lab exercise
(i.e. ePWM lab), the ADC generated an interrupt to the CPU, and the CPU read the ADC result
register in the ADC ISR. Then in the DMA lab exercise, the ADC instead triggered the DMA, and
the DMA generated an interrupt to the CPU, where the CPU read the ADC result register in the
DMA ISR. For this lab exercise, the ADC is instead triggering the CLA, and the CLA will directly
read the ADC result register and run a task implementing an FIR filter. The CLA will generate an
interrupt to the CPU, which will store the filtered results to a circular buffer implemented in the
CLA ISR.
10. Remember that in Adc.c we commented out the code used to enable the ADCA1
interrupt in PIE group 1. This is no longer being used. The CLA interrupt will be used
instead.

11. Using the “PIE Interrupt Assignment Table” find the location for the CLA Task 1 interrupt
“INT_CLA1_1” and fill in the following information:

9 - 18 TMS320F28004x Microcontroller Workshop - Control Law Accelerator

 Lab 9: CLA Floating-Point FIR Filter

PIE group #: # within group:

This information will be used in the next step.
12. Modify the end of Cla_9.c to do the following:
• Add the Driverlib function to re-map the CLA1_1 interrupt signal to call the ISR
function. (Hint: #define name in driverlib/inc/hw_ints.h and label name
in DefaultIsr_9_10.c)
• Add the Driverlib function to enable the appropriate PIEIER and core IER
13. Open and inspect DefaultIsr_9_10.c. Notice that this file contains the CLA interrupt
service routine. Save all modified files.

Build and Load

14. Click the “Build” button and watch the tools run in the Console window. Check for
errors in the Problems window.
15. Click the “Debug” button (green bug). The CCS Debug perspective view should open,
the program will load automatically, and you should now be at the start of main(). If the
device has been power cycled since the last lab exercise, be sure to configure the boot
mode to EMU_BOOT_RAM using the Scripts menu.

Run the Code – Test the CLA Operation

Note: For the next step, check to be sure that the jumper wire connecting PWM1A (pin #80) to
ADCINA0 (pin #70) is in place on the LaunchPad.

16. Run the code (real-time mode). Open and watch the memory browser window update.
Verify that the ADC result buffer contains updated values.

17. Setup a dual-time graph of the filtered and unfiltered ADC results buffer. Click:
Tools  Graph  Dual Time and set the following values:

Acquisition Buffer Size 50

DSP Data Type 16-bit unsigned integer

Sampling Rate (Hz) 50000

Start Address A AdcBufFiltered

Start Address B AdcBuf

Display Data Size 50

Time Display Unit µs

18. The graphical display should show the filtered PWM waveform in the Dual Time A display
and the unfiltered waveform in the Dual Time B display. You should see that the results
match the previous lab exercise.
19. Halt the code.

TMS320F28004x Microcontroller Workshop - Control Law Accelerator 9 - 19

Lab 9: CLA Floating-Point FIR Filter

Terminate Debug Session and Close Project

20. Terminate the active debug session using the Terminate button. This will close the
debugger and return Code Composer Studio to the CCS Edit perspective view.
21. Next, close the project by right-clicking on Lab9 in the Project Explorer window and
select Close Project.

End of Exercise

9 - 20 TMS320F28004x Microcontroller Workshop - Control Law Accelerator

 Lab 9: CLA Floating-Point FIR Filter

Lab 9 Reference: Low-Pass FIR Filter

Bode Plot of Digital Low Pass Filter

Coefficients: [1/16, 4/16, 6/16, 4/16, 1/16]

Sample Rate: 50 kHz

TMS320F28004x Microcontroller Workshop - Control Law Accelerator 9 - 21

Lab 9: CLA Floating-Point FIR Filter

9 - 22 TMS320F28004x Microcontroller Workshop - Control Law Accelerator

 System Design
Introduction
This module discusses various aspects of system design. Details of the emulation and analysis
block along with JTAG will be explored. Flash memory programming and the Code Security
Module will be described.

Module Objectives
Module Objectives

 JTAG Emulation
 Analysis and Diagnostic Capabilities
 Flash Configuration and
Memory Performance
 Flash Programming
 Dual Code Security Module (DCSM)

TMS320F28004x Microcontroller Workshop - System Design 10 - 1

Emulation and Analysis Block

Chapter Topics
System Design .......................................................................................................................... 10-1
Emulation and Analysis Block ................................................................................................. 10-3
Analysis and Diagnostic Capabilities ...................................................................................... 10-5
Flash Configuration and Memory Performance ...................................................................... 10-7
Flash Programming ............................................................................................................... 10-11
Dual Code Security Module (DCSM) .................................................................................... 10-13
Lab 10: Programming the Flash ............................................................................................ 10-17

10 - 2 TMS320F28004x Microcontroller Workshop - System Design

 Emulation and Analysis Block

Emulation and Analysis Block

JTAG Emulation System
System Under Test
H SCAN IN
E
TMS320C2000
Debug A
Probe D SCAN OUT
E
R

Some Available Debug Probes

XDS100 CLASS -
These debug probes are ultra-low cost and
BlackHawk: USB100
open-design which can used to create your own
Spectrum Digital: XDS100
debug probe
XDS110 CLASS -
This debug probe replaces the XDS100 class
Texas Instruments: XDS110
while supporting a wider variety of standards
XDS200 CLASS -
BlackHawk: USB200 These debug probes offer a balance of low cost
Spectrum Digital: XDS200 with good performance compared to the
XDS100/XDS110 class debug probes
Note: XDS510 CLASS debug probes are not recommended (obsolete); and for C2000, XDS560 CLASS debug
probes are expensive and typically do not offer much advantage over the XDS200 CLASS debug probes

Emulation Connections to the Device

TMS320F28004x Microcontroller Workshop - System Design 10 - 3

Emulation and Analysis Block

Emulation Mode Driverlib Functions

Selects the behavior of the peripheral during emulation control
Driverlib Function Options
CLAPROMCRC_setEmulationMode() CLAPROMCRC_MODE_SOFT
CLAPROMCRC_MODE_FREE
CPUTimer_setEmulationMode() CPUTIMER_EMULATIONMODE_STOPAFTERNEXTDECREMENT
CPUTIMER_EMULATIONMODE_STOPATZERO
CPUTIMER_EMULATIONMODE_RUNFREE
DMA_setEmulationMode() DMA_EMULATION_STOP
DMA_EMULATION_FREE_RUN
ECAP_setEmulationMode() ECAP_EMULATION_STOP
ECAP_EMULATION_RUN_TO_ZERO
ECAP_EMULATION_FREE_RUN
EPWM_setEmulationMode() EPWM_EMULATION_STOP_AFTER_NEXT_TB
EPWM_EMULATION_STOP_AFTER_FULL_CYCLE
EPWM_EMULATION_FREE_RUN
EQEP_setEmulationMode() EQEP_EMULATIONMODE_STOPIMMEDIATELY
EQEP_EMULATIONMODE_STOPATROLLOVER
EQEP_EMULATIONMODE_RUNFREE
I2C_setEmulationMode() I2C_EMULATION_STOP_SCL_LOW
I2C_EMULATION_FREE_RUN
SPI_setEmulationMode() SPI_EMULATION_STOP_MIDWAY
SPI_EMULATION_STOP_AFTER_TRANSMIT
SPI_EMULATION_FREE_RUN
Note: see the F28004x Driverlib User’s Guide for detailed usage

10 - 4 TMS320F28004x Microcontroller Workshop - System Design

 Analysis and Diagnostic Capabilities

Analysis and Diagnostic Capabilities

Analysis and Diagnostic Capabilities
 C28x CPU has two hardware analysis units:
 Address and Data Comparison Units (ACU/DCU)
 ACU – counts events or monitors address buses
 DCU – monitors address and data buses

 ACU and DCU can be configured as analysis breakpoints or

watchpoints; in addition, ACU can be configured as a benchmark
counter or event counter
 Embedded real-time analysis and diagnostic
(ERAD) module:
 Enhances the debug and system analysis capabilities
 ERAD module is implemented external to the C28x CPU core
 ERAD module consists of Enhanced Bus Comparator Units (EBC) and
Benchmark System Event Counter Units (BSEC)
 EBC – used to generate hardware breakpoints, hardware watchpoints
and other output events
 BSEC – used to analyze and profile the system

C28x CPU Hardware Analysis Units

 The C28x CPU two hardware analysis units can
be configured to provide any one of the following
advanced debug features:
Analysis Configuration Debug Activity
2 Hardware Breakpoints ⇒ Halt on a specified instruction
(for debugging in flash)

2 Address Watchpoints ⇒ A memory location is getting

corrupted; halt the processor when
any value is written to this location

1 Address Watchpoint with Data ⇒ Halt program execution after a

specific value is written to a variable

1 Pair Chained Breakpoints ⇒ Halt on a specified instruction only

after some other specific routine has
executed

TMS320F28004x Microcontroller Workshop - System Design 10 - 5

Analysis and Diagnostic Capabilities

ERAD Module
ERAD expands device debug and system analysis capabilities
to 10 hardware breakpoints and 10 hardware watchpoints
 8 Enhanced Bus
Comparator Units
C28x CPU ERAD
 Similar to ACU/DCU
 Inputs: address bus, Address Bus
program counter, data bus Data Bus Event
Enhanced Bus Output
 Comparison mode Program Counter Comparator
Debug Units (EBC)
 (>, >=, <, <=) Triggers
ACU DCU
x8
 Output: debug triggers,
event output
 4 Benchmark System
Event Counter Units Benchmark
 Similar to count feature in System Events System Event
Counter Unit
ACU (BSEC)
x4
 Inputs: events from EBC,
system events
 Outputs: debug events
Counter
 ERAD can be used by the Events
application or debugger

10 - 6 TMS320F28004x Microcontroller Workshop - System Design

 Flash Configuration and Memory Performance

Flash Configuration and Memory Performance

Basic Flash Operation
 RWAIT bit-field in the FRDCNTL register specifies the number of
random accesses wait states
 OTP reads are hardwired for 10 wait states (RWAIT has no effect)
 Must specify the number of SYSCLK cycle wait-states;
Reset defaults are maximum value (15)
 Flash/OTP reads returned after (RWAIT + 1 SYSCLK cycles)
 Flash configuration code should not be run from the flash memory

 Set the number of wait states for a flash read access

Flash_setWaitstates(ctrlBase, waitstates);
 ctrlBase is base address of the flash control registers: FLASH0CTRL_BASE
 waitstates value is a number between 0 and 15

*** Refer to the F28004x data sheet for value details ***
For 100 MHz, RWAIT = 4

Speeding Up Execution in Flash / OTP

16
Aligned
128-bit
fetch 128 Instruction
128 fetch 16 or 32
C28x
dispatched
MUX

core
2-level deep decoder
fetch buffer unit

128-bit data
cache Data read either from
program or data memory
Flash or OTP

 Enable prefetch mechanism:

Flash_enablePrefetch(ctrlBase);
 Enable data cache:
Flash_enableCache(ctrlBase);
 ctrlBase is base address of the flash control registers: FLASH0CTRL_BASE

TMS320F28004x Microcontroller Workshop - System Design 10 - 7

Flash Configuration and Memory Performance

Code Execution Performance

 Assume 100 MHz SYSCLKOUT and single-cycle
execution for each instruction

Internal RAM: 100 MIPS

Fetch up to 32 bits every cycle  1 instruction/cycle

Flash: 100 MIPS

Assume RWAIT=4, prefetch buffer enabled
Fetch 128 bits every 4 cycles:
(128 bits) / (32-bits per instruction worst-case)  4 instructions/4 cycles
PC discontinuity will degrade this, while 16-bit instructions can help
Benchmarking in control applications has shown actual performance of about
90% efficiency, yielding approximately 90 MIPS

Data Access Performance

 Assume 100 MHz SYSCLKOUT
Memory 16-bit access 32-bit access Notes
(words/cycle) (words/cycle)

Internal RAM 1 1

Flash 0.73 0.57 Assumes RWAIT = 4,

flash data cache enabled,
‘sequential’ access (8 words/11 cycles) (4 words/7 cycles) all 128 bits in cache are used

Flash 0.25 0.25 Assumes RWAIT = 4

random access (1 word/4 cycles) (1 word/4 cycles)

 Internal RAM has best data performance – put time critical data here
 Flash performance often sufficient for constants and tables
 Note that the flash instruction fetch pipeline will also stall during a
flash data access
 For best flash performance, arrange data so that all 128 bits in a
cache line are utilized (e.g. sequential access)

10 - 8 TMS320F28004x Microcontroller Workshop - System Design

 Flash Configuration and Memory Performance

Flash / OTP Power Modes

 Power configuration settings save power by putting Flash/OTP to ‘Sleep’ or
‘Standby’ mode; flash will automatically enter ‘Active’ mode if a Flash/OTP
access is made
 At reset Flash/OTP is in sleep mode
 Operates in three power modes:
 Sleep (lowest power)
 Standby (shorter transition time to active)
 Active (highest power)
 After an access is made, Flash/OTP can automatically power down to
‘Standby’ or ‘Sleep’ (active grace period set in user programmable counters)

 Set fallback power mode for flash bank:

Flash_setBankPowerMode(ctrlBase, bank, powerMode);
 Set fallback power mode for charge pump:
Flash_setPumpPowerMode(ctrlBase, powerMode);
 ctrlBase is base address of the flash control registers: FLASH0CTRL_BASE
 bank parameter is: FLASH_BANK0 or FLASH_BANK1
 powerMode value for:
 Bank – FLASH_BANK_PWR_x (x = SLEEP, STANDBY, or ACTIVE)
 Pump – FLASH_PUMP_PWR_x (x = SLEEP or ACTIVE)

Error Correction Code (ECC) Protection

 Provides capability to screen out Flash/OTP memory faults (enabled at reset)
 Single error correction and double error detection (SECDED)
 For every 64-bits of Flash/OTP, 8 ECC check bits are calculated and
programmed into ECC memory
 ECC check bits are programmed along with Flash/OTP data
 During an instruction fetch or data read operation the 64-bit data/8-bit ECC are
processed by the SECDED to determine one of three conditions:
 No error occurred
 A correctable error (single bit data error) occurred
 A non-correctable error (double bit data error or address error) occurred
ECC (15:8) Single-bit data error
SECDED Address/double-bit data error
Data (127:64) Single-bit error position
Flash
Corrected data out
and 128-bit aligned
OTP ECC (7:0) Single-bit data error
SECDED Address/double-bit data error
Data (63:0) Single-bit error position
Corrected data out

 Enable ECC protection: Flash_enableECC(eccBase);

 ctrlBase is base address of the ECC registers: FLASH0ECC_BASE

TMS320F28004x Microcontroller Workshop - System Design 10 - 9

Flash Configuration and Memory Performance

Initializing Flash Module

Main.c device.c
// CPU Initialization void Device_init(void)
Device_init(); {
• #ifdef _FLASH
•
• // Copy time critical and flash setup code to RAM
device.h memcpy(...&Ramfuncs...);
#endif
#define
DEVICE_FLASH_WAITSTATES 4 // Call flash initialization setup
Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE,
DEVICE_FLASH_WAITSTATES);
}

flash.c
void Flash_initModule(uint32_t ctrlBase, uint32_t eccBase, uint16_t waitstates)
{
Flash_setBankPowerMode(ctrlBase, FLASH_BANK0, FLASH_BANK_PWR_ACTIVE);
Flash_setBankPowerMode(ctrlBase, FLASH_BANK1, FLASH_BANK_PWR_ACTIVE);
Flash_setPumpPowerMode(ctrlBase, FLASH_PUMP_PWR_ACTIVE);
Flash_disableCache(ctrlBase); //disable before changing wait states
Flash_disablePrefetch(ctrlBase); //disable before changing wait states
Flash_setWaitstates(ctrlBase, waitstates);
Flash_enableCache(ctrlBase); //enable to improve performance
Flash_enablePrefetch(ctrlBase); //enable to improve performance
Flash_enableECC(eccBase);
}

10 - 10 TMS320F28004x Microcontroller Workshop - System Design

 Flash Programming

Flash Programming
Flash Programming Basics
 The device CPU performs the flash programming
 The CPU executes flash utility code from RAM that reads the flash
data and writes it into the flash memory
 We need to get the flash utility code and the flash data into RAM

FLASH CPU

Flash
Utility Emulator JTAG
Code
RAM
RS232 SCI

SPI

Bootloader
ROM
Flash I2C
Data
CAN

GPIO
F28004x

Flash Programming Basics

0x0008 0000
Flash Bank 0
0x0008 FFFF 64K x 16
0x0009 0000
Flash Bank 1
0x0009 FFFF 64K x 16

 Sequence of steps for flash programming:

Algorithm Function
1. Erase - Set all bits to one
2. Program - Program selected bits with zero
3. Verify - Verify flash contents

 Minimum Erase size is a sector

 Minimum Program size is a bit!

TMS320F28004x Microcontroller Workshop - System Design 10 - 11

Flash Programming

Flash Programming Utilities

 JTAG Emulator Based
 CCS on-chip Flash programmer (Tools  On-Chip Flash)
 CCS UniFlash (TI universal Flash utility)
 BlackHawk Flash utilities (requires Blackhawk emulator)
 Elprotronic FlashPro2000
 Spectrum Digital SDFlash JTAG (requires SD emulator)
 SCI Serial Port Bootloader Based
 CodeSkin C2Prog
 Elprotronic FlashPro2000
 Production Test/Programming Equipment Based
 BP Microsystems programmer
 Data I/O programmer
 Build your own custom utility
 Can use any of the ROM bootloader methods
 Can embed flash programming into your application
 Flash API algorithms provided by TI

* TI web has links to all utilities (http://www.ti.com/c2000)

10 - 12 TMS320F28004x Microcontroller Workshop - System Design

 Dual Code Security Module (DCSM)

Dual Code Security Module (DCSM)

Dual Code Security Module (DCSM)
 DCSM offers protection for two zones – zone 1 & zone 2
 Each zone has its own dedicated secure OTP
 Contains security configurations for each zone

 The following on-chip memory can be secured:

 Flash – each sector individually
 LS0-7 RAM – each block individually

 Data reads and writes from secured memory are only

allowed for code running from secured memory
 All other data read/write accesses are blocked:
JTAG emulator/debugger, ROM bootloader, code running in
external memory or unsecured internal memory

Zone Selection
 Each securable on-chip memory resource can
be allocated to either zone 1 (Z1), zone 2 (Z2),
or as non-secure
 DcsmZ1Regs.Z1_GRABSECTR register:
 Allocates individual flash sectors to zone 1 or non-secure

 DcsmZ2Regs.Z2_GRABSECTR register:
 Allocates individual flash sectors to zone 2 or non-secure

 DcsmZ1Regs.Z1_GRABRAMR register:
 Allocates LS0-7 to zone 1 or non-secure
 DcsmZ2Regs.Z2_GRABRAMR register:
 Allocates LS0-7 to zone 2 or non-secure
Technical Reference Manual contains a table to resolve mapping conflicts

TMS320F28004x Microcontroller Workshop - System Design 10 - 13

Dual Code Security Module (DCSM)

CSM Passwords
Zx_CSMPSWD0
Zx_CSMPSWD1
Zx_CSMPSWD2
Zx_CSMPSWD3

 Each zone is secured by its own 128-bit (four 32-bit

words) user defined CSM password
 Passwords for each zone is stored in its dedicated
OTP location
 Location based on a zone-specific link pointer
 128-bit CSMKEY registers are used to secure and
unsecure the device
 Password locations for each zone can be locked and
secured by programming PSWDLOCK fields in the
OTP with any value other than “1111” (0xF)

Zone Select Bits in OTP

Zx-LINKPOINTER Address offset of
Zone-Select block

xxx11111111111111111111111111111 0x020
xxx11111111111111111111111111110 0x030 Zone Select Block
xxx1111111111111111111111111110x 0x040
xxx111111111111111111111111110xx 0x050 Addr. Offset 32-bit Content
xxx11111111111111111111111110xxx 0x060
xxx1111111111111111111111110xxxx 0x070 0x0 Zx-EXEONLYRAM
xxx111111111111111111111110xxxxx 0x080 0x2 Zx-EXEONLYSECT
xxx11111111111111111111110xxxxxx 0x090
xxx1111111111111111111110xxxxxxx 0x0A0 0x4 Zx-GRABRAM
xxx111111111111111111110xxxxxxxx 0x0B0
xxx11111111111111111110xxxxxxxxx 0x0C0 0x6 Zx-GRABSECT
xxx1111111111111111110xxxxxxxxxx 0x0D0
xxx111111111111111110xxxxxxxxxxx 0x0E0 0x8 Zx-CSMPSWD0
xxx11111111111111110xxxxxxxxxxxx 0x0F0 0xA Zx-CSMPSWD1
xxx1111111111111110xxxxxxxxxxxxx 0x100
xxx111111111111110xxxxxxxxxxxxxx 0x110 0xC Zx-CSMPSWD2
xxx11111111111110xxxxxxxxxxxxxxx 0x120
xxx1111111111110xxxxxxxxxxxxxxxx 0x130 0xE Zx-CSMPSWD3
xxx111111111110xxxxxxxxxxxxxxxxx 0x140
xxx11111111110xxxxxxxxxxxxxxxxxx 0x150
xxx1111111110xxxxxxxxxxxxxxxxxxx 0x160  Final link pointer value is
xxx111111110xxxxxxxxxxxxxxxxxxxx 0x170
xxx11111110xxxxxxxxxxxxxxxxxxxxx 0x180 resolved by comparing all three
xxx1111110xxxxxxxxxxxxxxxxxxxxxx 0x190 individual link pointer values
xxx111110xxxxxxxxxxxxxxxxxxxxxxx 0x1A0
xxx11110xxxxxxxxxxxxxxxxxxxxxxxx 0x1B0 (bit-wise voting logic)
xxx1110xxxxxxxxxxxxxxxxxxxxxxxxx 0x1C0  OTP value “1” programmed as
xxx110xxxxxxxxxxxxxxxxxxxxxxxxxx 0x1D0
xxx10xxxxxxxxxxxxxxxxxxxxxxxxxxx 0x1E0 “0” (no erase operation)
xxx0xxxxxxxxxxxxxxxxxxxxxxxxxxxx 0x1F0

10 - 14 TMS320F28004x Microcontroller Workshop - System Design

 Dual Code Security Module (DCSM)

Zone Select Block - Linker Pointer

Zone 1 OTP FLASH Zone 2 OTP FLASH
0x78000 Z1-LINKPOINTER1 Three link pointers 0x78200 Z2-LINKPOINTER1
0x78002 Reserved need to be 0x78202 Reserved
0x78004 Z1-LINKPOINTER2
programmed with 0x78204 Z2-LINKPOINTER2
the same value
0x78006 Reserved (not ECC 0x78206 Reserved
0x78008 Z1-LINKPOINTER3 protected) 0x78208 Z2-LINKPOINTER3
0x7800A Reserved 0x7820A Reserved
0x78010 Z1-PSWDLOCK 0x78210 Z2-PSWDLOCK
0x78012 Reserved 0x78212 Reserved
0x78014 Z1-CRCLOCK 0x78214 Z2-CRCLOCK
0x78016 Reserved Zone Select Block 0x78216 Reserved
0x78018 Reserved Addr. Offset 32-bit Content 0x78218 Reserved
0x7801A Reserved 0x0 Zx-EXEONLYRAM 0x7821A Reserved
0x7801E Z1-BOOTCTRL 0x2 Zx-EXEONLYSECT 0x7821E Z2-BOOTCTRL
0x78020 ZoneSelectBlock1 0x4 Zx-GRABRAM 0x78220 ZoneSelectBlock1
(16 x 16-bits) 0x6 Zx-GRABSECT (16 x 16-bits)
0x78030 ZoneSelectBlock2 0x8 Zx-CSMPSWD0 0x78230 ZoneSelectBlock2
(16 x 16-bits) (16 x 16-bits)
0xA Zx-CSMPSWD1
● ● ● ●
● ● 0xC Zx-CSMPSWD2 ● ●
0x781F0 ZoneSelectBlockn 0xE Zx-CSMPSWD3 0x783F0 ZoneSelectBlockn
(16 x 16-bits) (16 x 16-bits)

Secure and Unsecure the CSM

 The CSM is always secured after reset
 To unsecure the CSM:
 Perform a dummy read of each CSMPSWD(0,1,2,3)
register (passwords in the OTP)
 Write the correct password to each CSMKEY(0,1,2,3)
register
 The boot ROM code will automatically unlock the
device as part of the initialization sequence for
devices that do not have passwords programmed
 See Technical Reference Manual for details

TMS320F28004x Microcontroller Workshop - System Design 10 - 15

Dual Code Security Module (DCSM)

CSM Password Match Flow

Start
Write the CSM Password
of that Zone into
CSMKEY(0/1/2/3) registers
Zone secure
after reset
or runtime

Correct No
Read Linkpointer and password?
calculate the address
of ZoneSelectBlock
Yes

Dummy Read of CSM PWL Zone

of the Secure Zone which Unsecure
needed to be unsecure

10 - 16 TMS320F28004x Microcontroller Workshop - System Design

 Lab 10: Programming the Flash

Lab 10: Programming the Flash

 Objective
The objective of this lab exercise is to program and execute code from the on-chip flash memory.
The TMS320F280049C device has been designed for standalone operation in an embedded
system. Using the on-chip flash eliminates the need for external non-volatile memory or a host
processor from which to bootload. In this lab exercise, the steps required to properly configure
the software for execution from internal flash memory will be covered.

Lab 10: Programming the Flash

ePWM1 ADC CLA

TB Counter _Cla1Task1
ADCINA0 RESULT0
Compare _Cla1Task2
Action Qualifier
jumper _Cla1Task8
wire

ePWM2 triggering
ADC on period match data
using SOCA trigger every memory
20 µs (50 kHz) ePWM2

CPU copies
result to
buffer during
CLA ISR

...
Objective:
 Program system into flash memory
 Learn use of CCS flash programmer Display
using CCS
 DO NOT PROGRAM PASSWORDS

 Procedure

Open the Project

1. A project named Lab10 has been created for this lab exercise. Open the project by
clicking on Project  Import CCS Projects. The “Import CCS Eclipse Projects”
window will open then click Browse… next to the “Select search-directory” box. Navigate
to: C:\F28004x\Labs\Lab10\project and click Select Folder. Then click
Finish to import the project. All build options have been configured the same as the
previous lab exercise. The files used in this lab exercise are:

TMS320F28004x Microcontroller Workshop - System Design 10 - 17

Lab 10: Programming the Flash

Adc.c EPwm.c
Cla.c f28004x_globalvariabledefs.c
ClaTasks_C.cla f28004x_headers_nonbios.cmd
CodeStartBranch.asm Gpio.c
Dac.c Lab_10.cmd
DefaultIsr_9_10.c Main_10.c
device.c SineTable.c
Dma.c Watchdog.c
ECap.c

Project Build Options

2. We need to setup the predefined symbols for programming the flash. Open the build
options by right-clicking on Lab10 in the Project Explorer window and select “Properties”.
Under “C2000 Compiler” select “Predefined Symbols”. In the predefined name box that
opens (“Pre-define NAME”) click the Add icon. Then in the “Enter Value” window type
_FLASH. This name is used in the project to conditionally include code specific to
initializing the flash module. This conditional code is located in the device.c file. Click
OK to include the name. Then click Apply and Close to save and close the Properties
window.

Link Initialized Sections to Flash

Initialized sections, such as code and constants, must contain valid values at device power-up.
Stand-alone operation of an embedded system means that no debug probe (emulator) is
available to initialize the device RAM. Therefore, all initialized sections must be linked to the on-
chip flash memory.

Each initialized section actually has two addresses associated with it. First, it has a LOAD
address which is the address to which it gets loaded at load time (or at flash programming time).
Second, it has a RUN address which is the address from which the section is accessed at
runtime. The linker assigns both addresses to the section. Most initialized sections can have the
same LOAD and RUN address in the flash. However, some initialized sections need to be loaded
to flash, but then run from RAM. This is required, for example, if the contents of the section
needs to be modified at runtime by the code.

3. Open and inspect the linker command file Lab_10.cmd. Notice that the first flash sector
has been divided into two blocks named BEGIN_FLASH and FLASH_BANK0_SEC0.
The FLASH_BANK0_SEC0 flash sector origin and length has been modified to avoid
conflicts with the other flash sector spaces. The remaining flash sectors have been
combined into a single block named FLASH_BANK0_SEC1_15. Additionally, a second
bank is available named FLASH_BANK1_SEC0_15. See the reference slide at the end
of this lab exercise for further details showing the address origins and lengths of the
various flash sectors used.

4. Edit Lab_10.cmd to link the following compiler sections to on-chip flash memory block
FLASH_BANK0_SEC1_15:
Compiler Sections:

.text .cinit .const .econst .pinit .switch

Copying Interrupt Vectors from Flash to RAM

The interrupt vectors must be located in on-chip flash memory and at power-up needs to be
loaded to the PIE RAM as part of the device initialization procedure. The code that performs this

10 - 18 TMS320F28004x Microcontroller Workshop - System Design

 Lab 10: Programming the Flash

process is part of Driverlib. In main(), the call to Interrupt_initModule() enables vector fetching
from PIE block, and the call to Interrupt_initVectorTable() loads the vector table. In Driverlib, both
functions are part of interrupt.c.

Initializing the Flash Control Registers

The initialization code for the flash control registers cannot execute from the flash memory (since
it is changing the flash configuration!). Therefore, the initialization function for the flash control
registers must be copied from flash (load address) to RAM (run address) at runtime. The code
that performs this process is part of Driverlib. In main(), the call to Device_init() copies time
critical and flash setup code to RAM and then calls Flash_initModule() to initialize the flash. In
Driverlib, these functions are part of device.c and flash.c.

5. In the Driverlib, flash.c uses the C compiler CODE_SECTION pragma to place the
Flash_initModule() function into a linkable section named “.TI.ramfunc”.

6. The “.TI.ramfunc” section will be linked using the user linker command file Lab_10.cmd.
In Lab_10.cmd the “.TI.ramfunc” will load to flash (load address) but will run from
RAMLS5 (run address). Also notice that the linker has been asked to generate symbols
for the load start, load size, and run start addresses.

While not a requirement from a MCU hardware or development tools perspective (since
the C28x MCU has a unified memory architecture), historical convention is to link code to
program memory space and data to data memory space. Therefore, notice that for the
RAMLS5 memory we are linking “.TI.ramfunc” to, we are specifiying “PAGE = 0” (which is
program memory).

Dual Code Security Module and Passwords

The DCSM module provides protection against unwanted copying (i.e. pirating!) of your code
from flash, OTP, and LS0-7 RAM blocks. The DCSM uses a 128-bit password made up of 4
individual 32-bit words. They are located in the OTP. During this lab exercise, device default
passwords will be used – therefore only dummy reads of the password locations are needed to
unsecure the DCSM. DO NOT PROGRAM ANY REAL PASSWORDS INTO THE DEVICE.
After development, real passwords are typically placed in the password locations to protect your
code. We will not be using real passwords in the workshop. Again, DO NOT CHANGE THE
DEVICE PASSWORD VALUES.

Executing from Flash after Reset

The F280049C device contains a ROM bootloader that will transfer code execution to the flash
after reset. When the boot mode selection is set for “Jump to Flash” mode, the bootloader will
branch to the instruction located at address 0x080000 in the flash. An instruction that branches
to the beginning of your program needs to be placed at this address. Note that BEGIN_FLASH
begins at address 0x080000. There are exactly two words available to hold this branch
instruction, and not coincidentally, a long branch instruction “LB” in assembly code occupies
exactly two words. Generally, the branch instruction will branch to the start of the C-environment
initialization routine located in the C-compiler runtime support library. The entry symbol for this
routine is _c_int00. Recall that C code cannot be executed until this setup routine is run.
Therefore, assembly code must be used for the branch. We are using the assembly code file
named CodeStartBranch.asm.

7. Open and inspect CodeStartBranch.asm. This file creates an initialized section

named “codestart” that contains a long branch to the C-environment setup routine. This
section needs to be linked to a block of memory named BEGIN_FLASH.

TMS320F28004x Microcontroller Workshop - System Design 10 - 19

Lab 10: Programming the Flash

8. In the earlier lab exercises, the section “codestart” was directed to the memory named
BEGIN_M0. Edit Lab_10.cmd so that the section “codestart” will be directed to
BEGIN_FLASH. Save your work.

On power up the reset vector will be fetched and the ROM bootloader will begin execution. If the
debug probe (emulator) is connected, the device will be in emulation boot mode and will use the
EMU-BOOT registers values in the PIE RAM to determine the boot mode. This mode was
utilized in the previous lab exercises. In this lab exercise, we will be disconnecting the debug
probe and running in stand-alone boot mode (but do not disconnect the emulator yet!). The
bootloader will read the Z1-OTP-BOOT registers values from their locations in the OTP. The
behavior when these values have not been programmed (i.e., KEY not 0x5A) or have been set to
invalid values is boot to flash boot mode.

Initializing the CLA

Previously, the named section “Cla1Prog” containing the CLA program tasks was linked directly
to the CPU memory block RAMLS4 for both load and run purposes. At runtime, all the code did
was map the RAMLS4 block to the CLA program memory space during CLA initialization. For an
embedded application, the CLA program tasks are linked to load to flash and run from RAM. At
runtime, the CLA program tasks must be copied from flash to RAMLS4. The C-compiler runtime
support library contains a memory copy function called memcpy() which will be used to perform
the copy. After the copy is performed, the RAMLS4 block will then be mapped to CLA program
memory space as was done in the earlier lab.

9. In Lab_10.cmd notice that the named section “Cla1Prog” will now load to flash (load
address) but will run from RAMLS4 (run address). The linker will also be used to
generate symbols for the load start, load size, and run start addresses.

10. Open Cla.c and notice that the memory copy function memcpy() is being used to copy
the CLA program code from flash to RAMLS4 using the symbols generated by the linker.
Just after the copy the Driverlib MemCfg_setCLAMemType() function is used to configure
the RAMLS4 block as CLA program memory space. Close the opened files.

Build – Lab.out
11. Click the “Build” button to generate the Lab.out file to be used with the CCS Flash
Programmer. Check for errors in the Problems window.

Programming the On-Chip Flash Memory

In CCS the on-chip flash programmer is integrated into the debugger. When the program is
loaded CCS will automatically determine which sections reside in flash memory based on the
linker command file. CCS will then program these sections into the on-chip flash memory.
Additionally, in order to effectively debug with CCS, the symbolic debug information (e.g., symbol
and label addresses, source file links, etc.) will automatically load so that CCS knows where
everything is in your code. Clicking the “Debug” button in the CCS Edit perspective will
automatically launch the debugger, connect to the target, and program the flash memory in a
single step.

12. Program the flash memory by clicking the “Debug” button (green bug). The CCS Debug
perspective view will open and the flash memory will be programmed. (If needed, when
the “Progress Information” box opens select “Details >>” in order to watch the
programming operation and status). After successfully programming the flash memory
the “Progress Information” box will close. Then the program will load automatically, and
you should now be at the start of main().

10 - 20 TMS320F28004x Microcontroller Workshop - System Design

 Lab 10: Programming the Flash

Running the Code – Using CCS

13. Reset the CPU using the “CPU Reset” button or click:
Run  Reset  CPU Reset

The program counter should now be at address 0x3FC7A5 in the “Disassembly” window,
which is the start of the bootloader in the Boot ROM. If needed, click on the “View
Disassembly…” button in the window that opens, or click View  Disassembly.

14. Under Scripts on the menu bar click:

EMU Boot Mode Select  EMU_BOOT_FLASH

This has the debugger load values into EMU-BOOT registers so that the bootloader will
jump to "Flash" at address 0x080000.

15. Next click:

Run  Go Main

The code should stop at the beginning of your main() routine. If you got to that point
succesfully, it confirms that the flash has been programmed properly, that the bootloader
is properly configured for jump to flash mode, and that the codestart section has been
linked to the proper address.

16. You can now run the CPU, and you should observe the LED5 on the LaunchPad blinking.

17. Halt the CPU.

18. Try resetting the CPU, select the EMU_BOOT_FLASH boot mode, and then hitting run
(without doing the Go Main procedure). The LED should be blinking again.

19. Halt the CPU.

Terminate Debug Session and Close Project

20. Terminate the active debug session using the Terminate button. This will close the
debugger and return Code Composer Studio to the CCS Edit perspective view.

21. Next, close the project by right-clicking on Lab10 in the Project Explorer window and
select Close Project.

Running the Code – Stand-alone Operation (No Emulator)

Recall that if the device is in stand-alone boot mode, the state of GPIO24 and GPIO32 pins are
used to determine the boot mode. On the LaunchPad switch SW2 controls the boot options for
the F280049C device. Check that switch SW2 positions 1 and 2 are set to the default “1” (printed
on the board; both switches are towards the MCU). This will configure the device (in stand-alone
boot mode) to boot mode flash. Since the Z1-OTP-BOOT registers have not been programmed,
the default will be boot from flash. Details of the switch positions can be found in the LaunchPad
User’s Guide.

22. Close Code Composer Studio.

23. Disconnect the USB cable from the LaunchPad (i.e. remove power from the LaunchPad).

TMS320F28004x Microcontroller Workshop - System Design 10 - 21

Lab 10: Programming the Flash

24. Re-connect the USB cable to the LaunchPad (i.e. power the LaunchPad). The LED
should be blinking, showing that the code is now running from flash memory.

End of Exercise

10 - 22 TMS320F28004x Microcontroller Workshop - System Design

 Lab 10: Programming the Flash

Lab 10 Reference: Programming the Flash

Flash Memory Section Blocks

origin =
0x080000 BEGIN_FLASH
length = 0x2
page = 0
0x080002 FLASH_BANK0_SEC0
length = 0x000FFE
page = 0
0x081000 FLASH_BANK0_SEC1_15
length = 0x00F000
page = 0
0x090000 FLASH_BANK1_SEC0_15
length = 0x010000
page = 0

Lab_10.cmd
SECTIONS
{
codestart :> BEGIN_FLASH, PAGE = 0

Startup Sequence from Flash Memory

0x080000 LB _c_int00 “rts2800_fpu32.lib”

_c_int00
4

FLASH (128Kw)
5
“user” code sections
3
main ( )
{
……
……
……
0x3F8000 Boot ROM (32Kw) }
Boot Code
InitBoot
{SCAN GPIO}
2
BROM vector (64w)
0x3FFFC0 * reset vector
1

RESET * reset vector = 0x3FC7A5

TMS320F28004x Microcontroller Workshop - System Design 10 - 23

Lab 10: Programming the Flash

10 - 24 TMS320F28004x Microcontroller Workshop - System Design

 Communications
Introduction
The TMS320F28004x contains features that allow for several methods of communication and
data exchange between the MCU and other devices. Many of the most commonly used
communications techniques are presented in this module.

The intent of this module is not to give exhaustive design details of the communication
peripherals, but rather to provide an overview of the features and capabilities. Once these
features and capabilities are understood, additional information can be obtained from various
resources such as the Technical Reference Manual, as needed. This module will cover the basic
operation of the communication peripherals, as well as some basic terms and how they work.

Module Objectives
Module Objectives

 Serial Peripheral Interface (SPI)

 Serial Communication Interface (SCI)
 Local Interconnect Network (LIN)
 Inter-Integrated Circuit (I2C)
 Controller Area Network (CAN)
 Power Management Bus (PMBus)
 Fast Serial Interface (FSI)

The F28004x MCU includes numerous communications peripherals that extend the connectivity
of the device. These communications peripherals include Serial Peripheral Interface (SPI), Serial
Communication Interface (SCI), Local Interconnect Network (LIN), Inter-Integrated Circuit (I2C)
Controller Area Network (CAN), Power Management Bus (PMBus), and Fast Serial Interface
(FSI).

TMS320F28004x Microcontroller Workshop - Communications 11 - 1

Communications Techniques

Chapter Topics
Communications ....................................................................................................................... 11-1
Communications Techniques .................................................................................................. 11-3
Serial Peripheral Interface (SPI) ............................................................................................. 11-4
SPI Summary ...................................................................................................................... 11-6
Serial Communications Interface (SCI) ................................................................................... 11-7
Multiprocessor Wake-Up Modes ......................................................................................... 11-9
SCI Summary .................................................................................................................... 11-11
Local Interconnect Network (LIN) ......................................................................................... 11-12
LIN Message Frame and Data Timing .............................................................................. 11-13
LIN Summary .................................................................................................................... 11-14
Inter-Integrated Circuit (I2C) ................................................................................................. 11-15
I2C Operating Modes and Data Formats .......................................................................... 11-16
I2C Summary .................................................................................................................... 11-17
Controller Area Network (CAN) ............................................................................................. 11-18
CAN Bus and Node ........................................................................................................... 11-19
Principles of Operation ...................................................................................................... 11-20
Message Format and Block Diagram ................................................................................ 11-21
CAN Summary .................................................................................................................. 11-22
Power Management Bus (PMBus) ........................................................................................ 11-23
Conceptual Block Diagram and Connections ................................................................... 11-23
PMBus Summary .............................................................................................................. 11-24
Fast Serial Interface (FSI) ..................................................................................................... 11-25
CPU Interface and Connection ......................................................................................... 11-26
FSI Summary .................................................................................................................... 11-27
Lab 11: C2000Ware SCI Echoback Example ....................................................................... 11-28

11 - 2 TMS320F28004x Microcontroller Workshop - Communications

 Communications Techniques

Communications Techniques
Several methods of implementing a TMS320C28x communications system are possible. The
method selected for a particular design should reflect the method that meets the required data
rate at the lowest cost. Various categories of interface are available and are summarized in the
module objective slide. Each will be described in this module.

Serial ports provide a simple, hardware-efficient means of high-level communication between

devices. Like the GPIO pins, they may be used in stand-alone or multiprocessing systems.

In a multiprocessing system, they are an excellent choice when both devices have an available
serial port and the data rate requirement is relatively low. Serial interface is even more desirable
when the devices are physically distant from each other because the inherently low number of
wires provides a simpler interconnection.

Serial ports require separate lines to implement, and they do not interfere in any way with the
data and address lines of the processor. The only overhead they require is to read/write new
words from/to the ports as each word is received/transmitted. This process can be performed as
a short interrupt service routine under hardware control, requiring only a few cycles to maintain.

The C2000 device family has both synchronous and asynchronous serial ports. The features and
operation will be described in this module.

TMS320F28004x Microcontroller Workshop - Communications 11 - 3

Serial Peripheral Interface (SPI)

Serial Peripheral Interface (SPI)

The SPI is a high-speed synchronous serial port that shifts a programmable length serial bit
stream into and out of the device at a programmable bit-transfer rate. It is typically used for
communications between processors and external peripherals, and it has a 16-level deep receive
and transmit FIFO for reducing servicing overhead. During data transfers, one SPI device must
be configured as the transfer MASTER, and all other devices configured as SLAVES. The
master drives the transfer clock signal for all SLAVES on the bus. SPI communications can be
implemented in any of three different modes:

• MASTER sends data, SLAVES send dummy data

• MASTER sends data, one SLAVE sends data

• MASTER sends dummy data, one SLAVE sends data

In its simplest form, the SPI can be thought of as a programmable shift register. Data is shifted in
and out of the SPI through the SPIDAT register. Data to be transmitted is written directly to the
SPIDAT register, and received data is latched into the SPIBUF register for reading by the CPU.
This allows for double-buffered receive operation, in that the CPU need not read the current
received data from SPIBUF before a new receive operation can be started. However, the CPU
must read SPIBUF before the new operation is complete of a receiver overrun error will occur. In
addition, double-buffered transmit is not supported: the current transmission must be complete
before the next data character is written to SPIDAT or the current transmission will be corrupted.

The Master can initiate a data transfer at any time because it controls the SPICLK signal. The
software, however, determines how the Master detects when the Slave is ready to broadcast.

SPI Data Flow

 Simultaneous transmits and receive

 SPI Master provides the clock signal

SPI Device #1 - Master SPI Device #2 - Slave

shift shift

SPI Shift Register SPI Shift Register

clock

11 - 4 TMS320F28004x Microcontroller Workshop - Communications

 Serial Peripheral Interface (SPI)

SPI Block Diagram

C28x - SPI Master Mode Shown
SPISIMO
RX FIFO_15

RX FIFO_0
SPIRXBUF.15-0

MSB LSB
SPIDAT.15-0 SPISOMI

SPITXBUF.15-0
TX FIFO_0

TX FIFO_15

LSPCLK baud clock clock SPICLK

rate polarity phase

SPI Transmit / Receive Sequence

1. Slave writes data to be sent to its shift register (SPIDAT)

2. Master writes data to be sent to its shift register (SPIDAT or SPITXBUF)

3. Completing Step 2 automatically starts SPICLK signal of the Master

4. MSB of the Master’s shift register (SPIDAT) is shifted out, and LSB of the Slave’s shift
register (SPIDAT) is loaded

5. Step 4 is repeated until specified number of bits are transmitted

6. SPIDAT register is copied to SPIRXBUF register

7. SPI INT Flag bit is set to 1

8. An interrupt is asserted if SPI INT ENA bit is set to 1

9. If data is in SPITXBUF (either Slave or Master), it is loaded into SPIDAT and transmission
starts again as soon as the Master’s SPIDAT is loaded

Since data is shifted out of the SPIDAT register MSB first, transmission characters of less than 16
bits must be left-justified by the CPU software prior to be written to SPIDAT.

Received data is shifted into SPIDAT from the left, MSB first. However, the entire sixteen bits of
SPIDAT is copied into SPIBUF after the character transmission is complete such that received
characters of less than 16 bits will be right-justified in SPIBUF. The non-utilized higher
significance bits must be masked-off by the CPU software when it interprets the character. For
example, a 9 bit character transmission would require masking-off the 7 MSB’s.

TMS320F28004x Microcontroller Workshop - Communications 11 - 5

Serial Peripheral Interface (SPI)

SPI Data Character Justification

 Programmable data
length of 1 to 16 bits SPIDAT - Processor #1
 Transmitted data of less 11001001XXXXXXXX
than 16 bits must be left
justified
MSB transmitted first
 Received data of less
SPIDAT - Processor #2
than 16 bits are right
justified XXXXXXXX11001001

 User software must

mask-off unused MSB’s

SPI Summary
SPI Summary

 Synchronous serial communications

 Two wire transmit or receive (half duplex)
 Three wire transmit and receive (full duplex)

 Software configurable as master or slave

 C28x provides clock signal in master mode

 Data length programmable from 1-16 bits

 125 different programmable baud rates

11 - 6 TMS320F28004x Microcontroller Workshop - Communications

 Serial Communications Interface (SCI)

Serial Communications Interface (SCI)

The SCI is a two-wire asynchronous serial port (also known as a UART) that supports
communications between the processor and other asynchronous peripherals that use the
standard non-return-to-zero (NRZ) format. A receiver and transmitter 16-level deep FIFO is used
to reduce servicing overhead. The SCI transmit and receive registers are both double-buffered to
prevent data collisions and allow for efficient CPU usage. In addition, the C28x SCI is a full
duplex interface which provides for simultaneous data transmit and receive. Parity checking and
data formatting is also designed to be done by the port hardware, further reducing software
overhead.

SCI Pin Connections

(Full Duplex Shown)
TX FIFO_15 TX FIFO_15

TX FIFO_0 TX FIFO_0
Transmitter-data Transmitter-data
buffer register buffer register

8 8

Transmitter SCITXD SCITXD Transmitter

shift register shift register

Receiver SCIRXD SCIRXD Receiver

shift register shift register
8 8
Receiver-data Receiver-data
buffer register buffer register
RX FIFO_0 RX FIFO_0

RX FIFO_15 RX FIFO_15

SCI Device #1 SCI Device #2

TMS320F28004x Microcontroller Workshop - Communications 11 - 7

Serial Communications Interface (SCI)

SCI Data Format

NRZ (non-return to zero) format

Addr/
Start LSB 2 3 4 5 6 7 MSB Parity Stop 1 Stop 2
Data

This bit present only in Address-bit mode

Communications Control Register (SCICCR)

7 6 5 4 3 2 1 0
Stop Even/Odd Parity Loopback Addr/Idle SCI SCI SCI
Bits Parity Enable Enable Mode Char2 Char1 Char0

0 = 1 Stop bit 0 = Disabled 0 = Idle-line mode # of data bits = (binary + 1)

1 = 2 Stop bits 1 = Enabled 1 = Addr-bit mode e.g. 110b gives 7 data bits

0 = Odd 0 = Disabled
1 = Even 1 = Enabled

The basic unit of data is called a character and is 1 to 8 bits in length. Each character of data is
formatted with a start bit, 1 or 2 stop bits, an optional parity bit, and an optional address/data bit.
A character of data along with its formatting bits is called a frame. Frames are organized into
groups called blocks. If more than two serial ports exist on the SCI bus, a block of data will
usually begin with an address frame which specifies the destination port of the data as
determined by the user’s protocol.

The start bit is a low bit at the beginning of each frame which marks the beginning of a frame.
The SCI uses a NRZ (Non-Return-to-Zero) format which means that in an inactive state the
SCIRX and SCITX lines will be held high. Peripherals are expected to pull the SCIRX and SCITX
lines to a high level when they are not receiving or transmitting on their respective lines.

When configuring the SCICCR, the SCI port should first be held in an inactive state. This is
done using the SW RESET bit of the SCI Control Register 1 (SCICTL1.5). Writing a 0 to this bit
initializes and holds the SCI state machines and operating flags at their reset condition. The
SCICCR can then be configured. Afterwards, re-enable the SCI port by writing a 1 to the SW
RESET bit. At system reset, the SW RESET bit equals 0.

11 - 8 TMS320F28004x Microcontroller Workshop - Communications

 Serial Communications Interface (SCI)

SCI Data Timing

 Start bit valid if 4 consecutive SCICLK periods of
zero bits after falling edge
 Majority vote taken on 4th, 5th, and 6th SCICLK cycles

Majority
Vote

SCICLK
(Internal)
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2

SCIRXD

Start Bit LSB of Data

Falling Edge Detected

Note: 8 SCICLK periods per data bit

Multiprocessor Wake-Up Modes

Multiprocessor Wake-Up Modes

 Allows numerous processors to be hooked

up to the bus, but transmission occurs
between only two of them
 Idle-line or Address-bit modes
 Sequence of Operation
1. Potential receivers set SLEEP = 1, which disables RXINT except
when an address frame is received
2. All transmissions begin with an address frame
3. Incoming address frame temporarily wakes up all SCIs on bus
4. CPUs compare incoming SCI address to their SCI address
5. Process following data frames only if address matches

TMS320F28004x Microcontroller Workshop - Communications 11 - 9

Serial Communications Interface (SCI)

Idle-Line Wake-Up Mode

 Idle
time separates blocks of frames
 Receiver wakes up when SCIRXD high for 10 or
more bit periods
 Two transmit address methods
 Deliberatesoftware delay of 10 or more bits
 Set TXWAKE bit to automatically leave exactly 11
idle bits
Idle periods
of less than Block of Frames
10 bits

SCIRXD/ Last Data SP ST Addr SP ST Data SP ST Last Data SP ST Addr SP

SCITXD

Idle Address frame 1st data frame Idle

Period follows 10 bit Period
10 bits 10 bits
or greater or greater idle or greater

Address-Bit Wake-Up Mode

 Allframes contain an extra address bit
 Receiver wakes up when address bit detected
 Automatic setting of Addr/Data bit in frame by
setting TXWAKE = 1 prior to writing address
to SCITXBUF
Block of Frames

SCIRXD/ Last Data 0 SP ST Addr 1 SP ST Data 0 SP ST Last Data 0 SP ST Addr 1 SP

SCITXD

First frame within 1st data frame

no additional
Idle Period block is Address. idle bits needed
length of no ADDR/DATA beyond stop bits
significance bit set to 1

The SCI interrupt logic generates interrupt flags when it receives or transmits a complete
character as determined by the SCI character length. This provides a convenient and efficient
way of timing and controlling the operation of the SCI transmitter and receiver. The interrupt flag
for the transmitter is TXRDY (SCICTL2.7), and for the receiver RXRDY (SCIRXST.6). TXRDY is

11 - 10 TMS320F28004x Microcontroller Workshop - Communications

 Serial Communications Interface (SCI)

set when a character is transferred to TXSHF and SCITXBUF is ready to receive the next
character. In addition, when both the SCIBUF and TXSHF registers are empty, the TX EMPTY
flag (SCICTL2.6) is set. When a new character has been received and shifted into SCIRXBUF,
the RXRDY flag is set. In addition, the BRKDT flag is set if a break condition occurs. A break
condition is where the SCIRXD line remains continuously low for at least ten bits, beginning after
a missing stop bit. Each of the above flags can be polled by the CPU to control SCI operations,
or interrupts associated with the flags can be enabled by setting the RX/BK INT ENA
(SCICTL2.1) and/or the TX INT ENA (SCICTL2.0) bits active high.

Additional flag and interrupt capability exists for other receiver errors. The RX ERROR flag is the
logical OR of the break detect (BRKDT), framing error (FE), receiver overrun (OE), and parity
error (PE) bits. RX ERROR high indicates that at least one of these four errors has occurred
during transmission. This will also send an interrupt request to the CPU if the RX ERR INT ENA
(SCICTL1.6) bit is set.

SCI Summary
SCI Summary
 Asynchronous communications format
 65,000+ different programmable baud rates
 Two wake-up multiprocessor modes
 Idle-line wake-up & Address-bit wake-up
 Programmable data word format
1 to 8 bit data word length
 1 or 2 stop bits
 even/odd/no parity

 Error Detection Flags

 Parity error; Framing error; Overrun error;
Break detection
 Transmit FIFO and receive FIFO
 Individual interrupts for transmit and receive

TMS320F28004x Microcontroller Workshop - Communications 11 - 11

Local Interconnect Network (LIN)

Local Interconnect Network (LIN)

Local Interconnect Network (LIN)
A broadcast serial network
 One master, up to sixteen addressable slaves
 Serial link layer similar to UART (e.g., start, data,
stop bits)
 Single wire (plus ground)
 12V bus (originally desiged for automotive apps)
 No bus arbitration or collision detection
 Master initiates all communication
 A single slave responds
 Configurable Baud Rate up to 20 Kbits/s
 C2000 LIN module
 Compliant with the LIN spec 2.1
 Can be used as an SCI (UART), if desired

The LIN standard is based on the SCI (UART) serial data link format. The communication
concept is single-master/multiple-slave with a message identification for multi-cast transmission
between any network nodes.

LIN Module Block Diagram

8
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0 Checksum
Calculator
Synchronizer

Mask
LINRX SCIRXSHF
Filter Parity
Calculator
LINTX SCITXSHF
Bit
Monitor
TD0
TD1
TD2
TD3
TD4
TD5
TD6
TD7

11 - 12 TMS320F28004x Microcontroller Workshop - Communications

 Local Interconnect Network (LIN)

LIN Message Frame and Data Timing

LIN Message Frame
Message Frame
Master Sends Slave Responds
1 to 8 Data Fields

Sync Sync ID Data Data Data Data Data Check

Sum
Break Field Field Field Field Field Field Field Field

In-Frame Space Interbyte Spaces

 Sync Break – beginning of a message

 Sync Field – bit rate synchronizing occurs
 ID Field
 Identifier: 6-bit ID, 2-bit parity
 Message (optional): 2, 4, or 8 bytes
 Data Field – 1-bit start, 8-bit data, 1-bit stop bit
 Checksum Field – 1-bit start, 8-bit checksum,
1-bit stop
 In-Frame & Inter-byte Spaces – can be 0

LIN Data Timing

To make a determination of the bit value, 16

samples of each bit are taken with majority
vote on samples 8, 9, and 10

Majority Majority Majority

Vote Vote Vote

LM_CLK
(Internal)

LINRX

TMS320F28004x Microcontroller Workshop - Communications 11 - 13

Local Interconnect Network (LIN)

LIN Bus Connections

12 V

1 KΩ
LIN bus (master node only)

12 V
Vdd (e.g., 3.3 V)
LIN Transceiver
~5 KΩ

Vdd
TX RX
LIN Controller
(F28004x)

LIN Summary
LIN Summary

 Functionally compatible with standalone

SCI of C28x devices
 Identification masks for filtering
 Automatic master header generation
 231 programmable transmission rates with
7 fractional bits
 Automatic wakeup support
 Error detection (bit, bus, no response,
checksum, synchronization, parity)
 Multi-buffered receive/transmit units

11 - 14 TMS320F28004x Microcontroller Workshop - Communications

 Inter-Integrated Circuit (I2C)

Inter-Integrated Circuit (I2C)

Inter-Integrated Circuit (I2C)
 NXP Semiconductors I2C-bus specification compliant, version 2.1
 Data transfer rate from 10 kbps up to 400 kbps
 Each device can be considered as a Master or Slave
 Master initiates data transfer and generates clock signal
 Device addressed by Master is considered a Slave
 Multi-Master mode supported
 Standard Mode – send exactly n data values (specified in register)
 Repeat Mode – keep sending data values (use software to initiate a
stop or new start condition)
VDD ..
Pull-up 28x I2C
Resistors I2C Controller

Serial Data (SDA)

Serial Clock (SCL)
.. . . . . . . . .
I2C 28x
EPROM I2C

The I2C provides an interface between devices that are compliant I2C-bus specification version
2.1 and connect using an I2C-bus. External components attached to the 2-wire serial bus can
transmit or receive 1 to 8-bit data to or from the device through the I2C module.

I2C Block Diagram

I2CXSR I2CDXR

TX FIFO
SDA
RX FIFO

I2CRSR I2CDRR

Clock
SCL
Circuits

TMS320F28004x Microcontroller Workshop - Communications 11 - 15

Inter-Integrated Circuit (I2C)

I2C Operating Modes and Data Formats

I2C Operating Modes

Operating Mode Description

Slave-receiver mode Module is a slave and receives data from a master

(all slaves begin in this mode)

Slave-transmitter mode Module is a slave and transmits data to a master

(can only be entered from slave-receiver mode)

Master-receiver mode Module is a master and receives data from a slave

(can only be entered from master-transmit mode)

Master-transmitter mode Module is a master and transmits to a slave

(all masters begin in this mode)

I2C Serial Data Formats

7-Bit Addressing Format

1 7 1 1 n 1 n 1 1
S Slave Address R/W ACK Data ACK Data ACK P

10-Bit Addressing Format

1 7 1 1 8 1 n 1 1
S 11110AA R/W ACK AAAAAAAA ACK Data ACK P

Free Data Format

1 n 1 n 1 n 1 1
S Data ACK Data ACK Data ACK P

R/W = 0 – master writes data to addressed slave

R/W = 1 – master reads data from the slave
n = 1 to 8 bits
S = Start (high-to-low transition on SDA while SCL is high)
P = Stop (low-to-high transition on SDA while SCL is high)

11 - 16 TMS320F28004x Microcontroller Workshop - Communications

 Inter-Integrated Circuit (I2C)

I2C Arbitration
 Arbitration procedure invoked if two or more master-
transmitters simultaneously start transmission
 Procedure uses data presented on serial data bus (SDA) by
competing transmitters
 First master-transmitter which drives SDA high is overruled
by another master-transmitter that drives SDA low
 Procedure gives priority to the data stream with the lowest
binary value

SCL
Device #1 lost arbitration
and switches to slave-
Data from 1 0 receiver mode
device #1
Data from Device #2
1 0 0 1 0 1 drives SDA
device #2

SDA 1 0 0 1 0 1

I2C Summary
I2C Summary

 Compliance with Philips I2C-bus specification

(version 2.1)
 7-bit and 10-bit addressing modes
 Configurable 1 to 8 bit data words
 Data transfer rate from 10 kbps up to 400 kbps
 Transmit FIFO and receive FIFO

TMS320F28004x Microcontroller Workshop - Communications 11 - 17

Controller Area Network (CAN)

Controller Area Network (CAN)

Controller Area Network (CAN)
A Multi-Master Serial Bus System
 CAN 2.0B Standard
 High speed (up to 1 Mbps)
 Add a node without disturbing the bus (number of nodes not
limited by protocol)
 Less wires (lower cost, less maintenance, and more reliable)
 Redundant error checking (high reliability)
 No node addressing (message identifiers)
 Broadcast based signaling

A
B
C

D E

The CAN module is a serial communications protocol that efficiently supports distributed real-time
control with a high level of security. It supports bit-rates up to 1 Mbit/s and is compliant with the
CAN 2.0B protocol specification.

CAN does not use physical addresses to address stations. Each message is sent with an
identifier that is recognized by the different nodes. The identifier has two functions – it is used for
message filtering and for message priority. The identifier determines if a transmitted message
will be received by CAN modules and determines the priority of the message when two or more
nodes want to transmit at the same time.

11 - 18 TMS320F28004x Microcontroller Workshop - Communications

 Controller Area Network (CAN)

CAN Bus and Node

CAN Bus
 Two wire differential bus (usually twisted pair)
 Max. bus length depend on transmission rate
 40 meters @ 1 Mbps

CAN CAN CAN

NODE A NODE B NODE C

CAN_H

120Ω 120Ω
CAN_L

The MCU communicates to the CAN Bus using a transceiver. The CAN bus is a twisted pair wire
and the transmission rate depends on the bus length. If the bus is less than 40 meters the
transmission rate is capable up to 1 Mbit/second.

CAN Node
Wired-AND Bus Connection

CAN_H

120W 120W
CAN_L

CAN Transceiver
(e.g. TI SN65HVD23x)

TX RX
CAN Controller
(TMS320F28004x)

TMS320F28004x Microcontroller Workshop - Communications 11 - 19

Controller Area Network (CAN)

Principles of Operation
Principles of Operation
 Data messages transmitted are identifier based, not
address based
 Content of message is labeled by an identifier that is
unique throughout the network
 (e.g. rpm, temperature, position, pressure, etc.)
 All nodes on network receive the message and each
performs an acceptance test on the identifier
 If message is relevant, it is processed (received);
otherwise it is ignored
 Unique identifier also determines the priority of the
message
 (lower the numerical value of the identifier, the higher the
priority)
 When two or more nodes attempt to transmit at the
same time, a non-destructive arbitration technique
guarantees messages are sent in order of priority
and no messages are lost

Non-Destructive Bitwise Arbitration

 Bus arbitration resolved via arbitration with
wired-AND bus connections
 Dominate state (logic 0, bus is high)
 Recessive state (logic 1, bus is low)

Start
Bit
Node A Node A wins
arbitration
Node B
Node C

CAN Bus

Node B loses Node C loses

arbitration arbitration

11 - 20 TMS320F28004x Microcontroller Workshop - Communications

 Controller Area Network (CAN)

Message Format and Block Diagram

CAN Message Format
 Data is transmitted and received using Message Frames
 8 byte data payload per message
 Standard and Extended identifier formats

 Standard Frame: 11-bit Identifier (CAN v2.0A)

Arbitration Control
Field Field Data Field

S 11-bit R I E
O Identifier T D r0 DLC 0…8 Bytes Data CRC ACK O
F R E F

 Extended Frame: 29-bit Identifier (CAN v2.0B)

Control
Arbitration Field Field Data Field

S S I R E
11-bit 18-bit
O T r1 r0 DLC 0…8 Bytes Data
Identifier R D Identifier CRC ACK O
F R E R F

The MCU CAN module is a full CAN Controller. It contains a message handler for transmission
and reception management, and frame storage. The specification is CAN 2.0B Active – that is,
the module can send and accept standard (11-bit identifier) and extended frames (29-bit
identifier).

CAN Block Diagram

To ePIE DMA CPU Bus (8, 16 or 32-bit)

CAN

Module Interface
Test
Message Modes
Only
RAM Register and Message
Message Object Access (IFx)
32 RAM
Message Interface
Objects Message Handler
(mailboxes)

CAN Core

CAN_TX CAN_RX

SN65HVD23x
3.3 V CAN Transceiver

CAN Bus

TMS320F28004x Microcontroller Workshop - Communications 11 - 21

Controller Area Network (CAN)

The CAN controller module contains 32 mailboxes for objects of 0 to 8-byte data lengths:
• configurable transmit/receive mailboxes
• configurable with standard or extended indentifier

The CAN module mailboxes are divided into several parts:

• MID – contains the identifier of the mailbox
• MCF (Message Control Field) – contains the length of the message (to transmit or
receive) and the RTR bit (Remote Transmission Request – used to send remote
frames)
• MDL and MDH – contains the data

The CAN module contains registers which are divided into five groups:

• Control & Status Registers

• Local Acceptance Masks

• Message Object Time Stamps

• Message Object Timeout

• Mailboxes

CAN Summary
CAN Summary
 Fully compliant with CAN standard v2.0B
 Supports data rates up to 1 Mbps
 Thirty-two message objects
 Configurable as receive or transmit
 Configurable with standard or extended identifier
 Programmable receive mask
 Uses 32-bit time stamp on messages
 Programmable interrupt scheme (two levels)
 Programmable alarm time-out

 Programmable wake-up on bus activity

 Two interrupt lines
 Self-test mode

11 - 22 TMS320F28004x Microcontroller Workshop - Communications

 Power Management Bus (PMBus)

Power Management Bus (PMBus)

Power Management Bus (PMBus)
 Provides an interface between the MCU and devices
compliant with the SMI Forum PMBus Specification:
 Part I version 1.0 and Part II version 1.1
 Enables a standard 2-wire communications protocol between
power supply components
 Based on SMBus and supports I2C mode
 uses a similar physical layer to I2C
 Support for master and slave modes
 Support for three speeds:
 Standard Mode: Up to 100 kHz
 Fast Mode: 400 kHz
 Fast Mode+: 1000 kHz
 Applicable to module operating in I2C mode with input clock at 20 MHz

 Four-byte transmit and receive buffers

 Packet error checking (PEC)

Conceptual Block Diagram and Connections

Conceptual Block Diagram
SYSCLK

ALERT DMA
DIV PMBCTRL Registers
CTL
GPIO Bit Clock
CPU
MUX SDA PMBTXBUF
Shift
Register
PMBRXBUF
SCL PMBUSA_INT
PIE
PMBus Module

 SCL is the bus clock

 Normally controlled by the master; can be held low by a slave to
delay a transaction (to allow more time for processing)
 SDA is the bidirectional data line
 CONTROL is a slave input that can trigger an interrupt
 Can be used to tell a slave device to shut down
 ALERT is a slave output/master input
 Allows a slave to request attention from the master

TMS320F28004x Microcontroller Workshop - Communications 11 - 23

Power Management Bus (PMBus)

The PMBus module provides an interface for communicating between the microcontroller and
other devices that are compliant with the System Management Interface (SMI) specification.
PMBus is an open-standard digital power management protocol that enables communication
between components of a power system.

PMBus Connections
F28004x Alert DEVICE
Control #1
PMBus Data
Write Physical
Module Clock Protect Address

Alert DEVICE
Control #2
Data
Write Physical
Clock Protect Address

Alert DEVICE
Control #N
Data
Write Physical
Clock Protect Address

PMBus Summary
PMBus Summary
 Provides a standard and flexible means for
digital power management
 SDA and SCL timings derived from SYSCLK
 To comply with the PMBus timing specifications
the bit clock must be set to 10 MHz or less

 Four-byte Transmit Data Buffer

 Four-byte Receive Data Buffer
 Clock high and low time-outs
 CONTROL and ALERT signals

11 - 24 TMS320F28004x Microcontroller Workshop - Communications

 Fast Serial Interface (FSI)

Fast Serial Interface (FSI)

Fast Serial Interface (FSI)
 Ensure reliable high-speed serial communication
across an isolation barrier
 Provides galvanic isolation where different circuits do not
have common power and ground connections
 Consists of independent transmitter (FSITX) and
receiver (FSIRX) cores
 Each cores is configured and operated independently
 Point-to-point (single master/single slave)
 Fast transfer: 50 MHz
 Dual data rate (100 Mbps @ 50 MHz clock)
 Single or dual data lines
 Programmable data length
 Hardware- or software-calculated CRC
 Frame error detection
 Two interrupts per FSI core

The FSI module is a highly reliable high-speed serial communication peripheral capable of
operating at dual data rate providing 100 Mbps transfer using a 50 MHz clock. The FSI consists
of independent transmitter and receiver cores that are configured and operated independently.
FSI is a point-to-point communication protocol operating in a single-master/single-slave
configuration. With this high-speed data rate and low channel count, the FSI can be used to
increase the amount of information transmitted and reduce the costs to communicate over an
isolation barrier.

TMS320F28004x Microcontroller Workshop - Communications 11 - 25

Fast Serial Interface (FSI)

CPU Interface and Connection

Transmitter / Receiver CPU Interface
FSI Transmitter FSI Receiver

Core Signals Core Signals

Transmitter / Receiver Core Signals

Transmitter Core Signal Receiver Core Signal
 TXCLK – Transmit clock  RXCLK – Receive clock
 TXD0 – Primary data output  Connected to the TXCLK of the
line for transmission transmitting FSI module
 For multi-lane transmission:  RXD0 – Primary data input line
 Contains all the even for reception
numbered bits of the data  Connected to the TXD0 of the
and CRC bytes transmitting FSI module
 Other frame fields will be  RXD1 – Additional data input
transmitted in full line for reception
 TXD1 – Additional data output  Connected to the TXD1 of the
line for transmission transmitting FSI module if multi-
 Configured for multi-lane lane transmission is used
transmission:
 Contain all the odd numbered
bits of the data and CRC
bytes
 Applies only to the data
words and the CRC bytes

11 - 26 TMS320F28004x Microcontroller Workshop - Communications

 Fast Serial Interface (FSI)

Point to Point Connection

Note: while there is no true concept of a master or a slave node in the FSI protocol,
this example uses this nomenclature as a simple way to describe the data flow

FSI Summary
FSI Summary
 Highly reliable high-speed serial peripheral
for communicating over an isolation barrier
 High-speed data rate and low channel count
 Increases the amount of information transmitted
and reduce the costs
 Separate transmit and receive modules
 Point-to-point communication protocol
 FSI transmitter core communicates directly to a
single FSI receiver core
 Skew compensation for signal delay due to
isolation
 Line break detection

TMS320F28004x Microcontroller Workshop - Communications 11 - 27

Lab 11: C2000Ware SCI Echoback Example

Lab 11: C2000Ware SCI Echoback Example

 Objective
The objective of this lab exercise is to learn how to import and run a project from C2000Ware in
its default location. In the previous lab exercises, a local copy of the required C2000Ware files
was included with the lab files. This provided portability and made the workshop files self-
contained and independent of other support files or resources. It is assumed that Code
Composer Studio (CCS) is already installed; however, the installation of C2000Ware will be
required and included in the procedure directions.

For this lab exercise, the F28004x Driver Library (Driverlib) SCI echoback example will be used.
The SCI echoback example receives and returns data through the SCI-A port. The CCS terminal
feature will be used to view the data from the SCI and to send characters to the SCI. Each
character that is received by the SCI port is sent back to the host. The program will print out a
greeting and then ask you to enter a character which it will echo back to the terminal. Also, a
watch variable ‘loop count’ is included to count the number of characters sent.

The SCI-A port on the F280049C LaunchPad will communicate to the host PC using the USB
connection. The XDS110 debug probe enumerates as both a debugger and a virtual COM port.
By default, SCI-A is mapped to the virtual COM port of the XDS110 debug probe using GPIO28
and GPIO29. (Alternately, SCI-A can be connected to a host PC using an external connection via
a transceiver and cable).

 Procedure

Download and Install C2000Ware

1. Download C2000Ware from http://www.ti.com/tool/c2000ware. (Also, C2000Ware can be
downloaded using the CCS Resource Explorer).

2. Install C2000Ware using the default location (i.e. C:\ti\c2000\).

Import the Project

3. Import the project by clicking on Project  Import CCS Projects. The “Import
CCS Eclipse Projects” window will open then click Browse… next to the “Select search-
directory” box. Navigate to:

C:\ti\c2000\C2000Ware_<version>\driverlib\f28004x\examples\sci

and click Select Folder.

4. In the “Discovered projects” window that opens select sci_ex1_echoback and then
click Finish to import the project.

Modify the Target Configuration File

The F28004x Driverlib example projects include a target configuration file within each project.
This target configuration has been setup to use the XDS100v2 standard JTAG mode. Recall that
the F280049C LaunchPad XDS110 USB Debug Probe is only wired to support 2-pin cJTAG
mode. Therefore, before using the LaunchPad with these examples, the target configuration file
needs to be reconfigured.

11 - 28 TMS320F28004x Microcontroller Workshop - Communications

 Lab 11: C2000Ware SCI Echoback Example

5. The sci_ex1_echoback project should now appear in the Project Explorer window.
Expand the project and open the ‘targetConfigs’ folder. Rename the file name from
TMS320F280049M.ccxml to TMS320F280049C.ccxml (i.e. change from “M” to “C”).
Next, double-left click on the TMS320F280049C.ccxml file.

6. In the window that opens, select the emulator using the “Connection” pull-down list and
choose “Texas Instruments XDS110 USB Debug Probe”. In the “Board or Device” box
type TMS320F280049C to filter the options. In the box below, check the box to select
“TMS320F280049C”.

7. Under Advanced Setup click “Target Configuration” and highlight “Texas Instruments
XDS110 USB Debug Probe_0”. Under Connection Properties set the JTAG/SWD/cJTAG
Mode to “cJTAG (1149.7) 2-pin advanced modes”.

Click Save to save the configuration, then close the “TMS320F280049C.ccxml” setup
window by clicking the X on the tab.

Inspect sci_ex1_echoback.c
8. Open and inspect sci_ex1_echoback.c. Notice that code lines 139 through 148 use
the Driverlib functions to configure SCI-A.

Next, code lines 161 through 169 displays the greeting on the terminal and waits for a
character to be entered. Code lines 174 and 179 through 181 reads a character and
writes it back to the terminal. Finally, code line 186 increments the loop counter.

TMS320F28004x Microcontroller Workshop - Communications 11 - 29

Lab 11: C2000Ware SCI Echoback Example

Build and Load

9. Click the “Build” button and watch the tools run in the Console window. Check for
errors in the Problems window.

10. Click the “Debug” button (green bug). The CCS Debug perspective view should open,
the program will load automatically, and you should now be at the start of main(). If the
device has been power cycled since the last lab exercise, be sure to configure the boot
mode to EMU_BOOT_RAM using the Scripts menu.

Configure a CCS Terminal

11. To view the terminal information on your PC, we first need to determine the COM port
associated with the F280049C LaunchPad. To do this in Windows 10, right click on ‘This
PC’ (or ‘My Computer’ in earlier versions of Windows) and select on Properties. In the
dialog box that appears, click on Device Manager (or the Hardware tab and open Device
Manager). Look for an entry under Ports (COM & LPT) titled “User UART (COMX)” or
“USB Serial Port (COMX)”, where X is a number. Remember this number for the next
step where we will open and configure a serial terminal.

12. Open a CCS terminal by clicking the Terminal button or clicking:

View  Terminal

13. A Launch Terminal window will open. Configure the terminal with the following settings:
• Choose terminal: Serial Terminal
• Serial Port: (from above COM port number X)
• Baud rate: 9600
• Data size: 8
• Parity: None
• Stop bits: 1
• Encoding: Default (ISO-8859-1)

Click OK to launch the terminal window.

Run the Code

14. In sci_ex1_echoback.c towards the top of the code highlight the global variable
‘loopCounter’ with the mouse, right click and select “Add Watch Expression…” and
then select OK. The global variable loopCounter should now be in the Expressions
window with a value of “0”. This global variable will be used to count the number of
characters sent.

15. Enable the Expressions window for continuous refresh.

16. Run the code (using the Resume button on the toolbar). The program will print out a
greeting and then ask you to enter a character which it will echo back to the terminal.
Hello World!
You will enter a character, and the DSP will echo it back!
Enter a character:

11 - 30 TMS320F28004x Microcontroller Workshop - Communications

 Lab 11: C2000Ware SCI Echoback Example

17. Enter a character and the character will echo back to the terminal. Also, the loopCounter
will increment with each character sent.

18. Halt the code (using the Suspend button on the toolbar).

Terminate Debug Session and Close Project

19. Terminate the active debug session using the Terminate button. This will close the
debugger and return Code Composer Studio to the CCS Edit perspective view.

20. Next, close the project by right-clicking on sci_ex1_echoback in the Project Explorer
window and select Close Project.

End of Exercise

TMS320F28004x Microcontroller Workshop - Communications 11 - 31

Lab 11: C2000Ware SCI Echoback Example

11 - 32 TMS320F28004x Microcontroller Workshop - Communications

 Support Resources
Introduction
This module contains various references to support the development process.

Module Objectives
Module Objectives

 C2000 MCU Device Workshops Website

 Documentation Resources
 C2000Ware™
 TI Development Tools
 Additional Resources
 Product Information Center
 On-line support

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TI Support Resources

Chapter Topics
Support Resources ................................................................................................................... 12-1
TI Support Resources ............................................................................................................. 12-3
C2000 MCU Device Workshops Website ........................................................................... 12-3
Documentation Resources .................................................................................................. 12-4
C2000Ware™ ..................................................................................................................... 12-4
C2000 Experimenter’s Kit ................................................................................................... 12-5
F28335 Peripheral Explorer Kit ........................................................................................... 12-6
C2000 LaunchPad Evaluation Kit ....................................................................................... 12-7
C2000 controlCARD Application Kits .................................................................................. 12-8
XDS100/110/200 Class JTAG Debug Probes .................................................................... 12-9
Product Information Resources ........................................................................................ 12-10

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 TI Support Resources

TI Support Resources
C2000 MCU Device Workshops Website
C2000 MCU Device Workshops Website

https://training.ti.com/c2000-mcu-device-workshops
At the TI Training Portal you will find all of the materials for the C2000 Microcontroller Workshops,
which include support for the following device families:

• TMS320F28004x
• TMS320F2837xD
• TMS320F2806x
• TMS320F2803x
• TMS320F2802x
• TMS320F2833x
• TMS320F280x
• TMS320F281x
• TMS320F240x
• F28M35x

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TI Support Resources

Documentation Resources
Documentation Resources
 Data Sheet
 Contains device electrical characteristics and
timing specifications
 Key document for hardware engineers
 Silicon Errata
 Contains deviations from original specifications
 Includes silicon revision history
 Technical Reference Manual (TRM)
 Contains architectural descriptions and
register/bit definitions
 Key document for firmware engineers
 Workshop Materials
 Hands-on device training materials
 For hardware and software engineers
Documentation resources can be found at
www.ti.com/c2000

C2000Ware™
C2000Ware™

Resource Explorer

Directory Structure

C2000Ware for C2000 microcontrollers is a cohesive set of software infrastructure, tools, and
documentation that is designed to minimize system development time. It includes device-specific

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 TI Support Resources

drivers and support software, as well as system application examples. C2000Ware provides the
needed resources for development and evaluation. It can be downloaded from the TI website.

C2000 Experimenter’s Kit

C2000 Experimenter Kit
 Experimenter Kits include
 controlCARD
 USB docking station
 C2000 applications software with
example code and full hardware
details available in C2000Ware
 Part Number:
 Code Composer Studio (download)
 TMDSDOCK280049C
 TMDSDOCK28379D  Docking station features
 TMDSDOCK28069  Access to controlCARD signals
 TMDSDOCK28035  Breadboard areas
 TMDSDOCK28027  On-board USB JTAG debug probe
 TMDSDOCK28335  JTAG debug probe not required
 TMDSDOCK2808  controlCARDs are also
 TMDSDOCKH52C1
available separately
JTAG debug probe required for:
 Available through TI authorized
 TMDSDOCK28343
distributors and the TI store
 TMDSDOCK28346-168

The C2000 Experimenter Kits is a tool for device exploration and initial prototyping. These kits
are complete, open source, evaluation and development tools where the user can modify both the
hardware and software to best fit their needs.

The various Experimenter’s Kits shown on this slide include a specific controlCARD and Docking
Station. The docking station provides access to all of the controlCARD signals with two
prototyping breadboard areas and header pins, allowing for development of custom solutions.
Most have on-board USB JTAG emulation capabilities and no external debug probe or power
supply is required. However, where noted, the kits based on a DIMM-168 controlCARD include a
5-volt power supply and require an external JTAG debug probe.

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TI Support Resources

F28335 Peripheral Explorer Kit

F28335 Peripheral Explorer Kit
 Experimenter Kit includes
 F28335 controlCARD
 Peripheral Explorer baseboard
 C2000 applications software with
example code and full hardware details
available in C2000Ware
 Code Composer Studio (download)
 Peripheral Explorer features
 ADC input variable resistors
 GPIO hex encoder & push buttons
 eCAP infrared sensor
 GPIO LEDs, I2C & CAN connection
 Analog I/O (AIC+McBSP)
 On-board USB JTAG debug probe
 JTAG debug probe not required
 Available through TI authorized
TMDSPREX28335
distributors and the TI store

The C2000 Peripheral Explorer Kit is a learning tool for new C2000 developers and university
students. The kit includes a peripheral explorer board and a controlCARD with the
TMS320F28335 microcontroller. The board includes many hardware-based peripheral
components for interacting with the various peripherals common to C2000 microcontrollers, such
as the ADC, PWMs, eCAP, I2C, CAN, SPI and McBSP. A teaching ROM is provided containing
presentation slides, a learning textbook, and laboratory exercises with solutions.

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 TI Support Resources

C2000 LaunchPad Evaluation Kit

C2000 LaunchPad Evaluation Kit
 Low-cost evaluation kit
 F28027 and F28379D standard
versions
 F28027F version with InstaSPIN-FOC
 F28069M version with InstaSPIN-
MOTION
 Various BoosterPacks available
 On-board JTAG debug probe
 JTAG debug probe not required
 Access to LaunchPad signals
 C2000 applications software
 Part Number: with example code and full
 LAUNCHXL-F28027 hardware details in available in
 LAUNCHXL-F28027F C2000Ware
 LAUNCHXL-F28069M  Code Composer Studio (download)
 LAUNCHXL-F28379D  Available through TI authorized
 LAUNCHXL-F280049C
distributors and the TI store

The C2000 LaunchPads are low-cost, powerful evaluation platforms which are used to develop
real-time control systems based on C2000 microcontrollers. Various LaunchPads are available
and developers can find a LaunchPad with the required performance and feature mix for any
application. The C2000 BoosterPacks expand the power of the LaunchPads with application-
specific plug-in boards, allowing developers to design full solutions using a LaunchPad and
BoosterPack combination.

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TI Support Resources

C2000 controlCARD Application Kits

C2000 controlCARD Application Kits
 Developer’s Kit for – Motor Control,
Digital Power, etc. applications
 Kits includes
 controlCARD and application specific
baseboard
 Code Composer Studio (download)
 Software download includes
 Complete schematics, BOM, gerber
files, and source code for board and
all software
 Quickstart demonstration GUI for
quick and easy access to all board
features
 Fully documented software specific to
each kit and application
 See www.ti.com/c2000 for other kits
and more details
 Available through TI authorized
distributors and the TI store

The C2000 Application Kits demonstrate the full capabilities of the C2000 microcontroller in a
specific application. The kits are complete evaluation and development tools where the user can
modify both the hardware and software to best fit their needs. Each kit uses a device specific
controlCARD and a specific application board. All kits are completely open source with full
documentation and are supplied with complete schematics, bill of materials, board design details,
and software. Visit the TI website for a complete list of available Application Kits.

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 TI Support Resources

XDS100/110/200 Class JTAG Debug Probes

XDS100 / XDS110 / XDS200 Class JTAG
Debug Probes

 Blackhawk  Spectrum Digital

 USB100v2  XDS100v2

 Texas
Instruments
 XDS110

 Blackhawk  Spectrum Digital

 USB200  XDS200

www.blackhawk-dsp.com www.ti.com www.spectrumdigital.com

The JTAG debug probes are used during development to program and communicate with the
C20000 microcontroller. While almost all C2000 development tool include emulation capabilities,
after you have developed your own target board an external debug probe will be needed. Debug
probes are available with different features and at different price points. Shown here are popular
debug probes from various manufacturers.

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TI Support Resources

Product Information Resources

For More Information . . .
 USA – Product Information Center (PIC)
 Phone: +1-703-344-7012
 TI E2E Community
 http://e2e.ti.com
 Embedded Processor Wiki
 http://processors.wiki.ti.com
 TI Training
 http://training.ti.com
 TI store
 http://store.ti.com
 TI website
 http://www.ti.com

For more information and support, contact the product information center, visit the TI E2E
community, embedded processor Wiki, TI training web page, TI eStore, and the TI website.

12 - 10 TMS320F28004x Microcontroller Workshop - Support Resources

 Appendix A – F280049C Experimenter Kit
Overview
This appendix provides a quick reference and mapping of the header pins used on the F280049C
LaunchPad and F280049C Experimenter Kit. This allows either development board to be used
with the workshop.

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F280049C Experimenter Kit

Chapter Topics
Appendix A – F280049C Experimenter Kit .............................................................................. A-1
F280049C Experimenter Kit ......................................................................................................A-3
Initial Hardware Setup ...........................................................................................................A-3
Docking Station and LaunchPad Pin Mapping......................................................................A-3
controlCARD and LaunchPad LED Mapping ........................................................................A-3
Docking Station and LaunchPad Pin Locations ....................................................................A-4
Stand-Alone Operation (No Emulator) ..................................................................................A-4

A-2 TMS320F28004x Microcontroller Workshop – Appendix A

 F280049C Experimenter Kit

F280049C Experimenter Kit

Initial Hardware Setup
• F280049C Experimenter Kit:

Insert the F280049C controlCARD into the Docking Station connector slot. Using the two (2)
supplied USB cables – plug the USB Standard Type A connectors into the computer USB ports
and plug the USB Mini-B connectors as follows:

• J1:A on the controlCARD (left side) – isolated XDS100v2 JTAG emulation

• J17 on the Docking Station – board power

On the Docking Station move switch S1 to the “USB-ON” position. This will power the Docking
Station and controlCARD using the power supplied by the computer USB port. Additionally, the
other computer USB port will power the on-board isolated JTAG emulator and provide the JTAG
communication link between the device and Code Composer Studio.

Docking Station and LaunchPad Pin Mapping

Function Docking Station LaunchPad

ADCINA0 ANA header, Pin # 09 Pin # 70

GND GND Pin # 20 (GND)

GPIO59 (‘1’) Pin # 101 Pin # 11

GPIO25 (‘T’) Pin # 77 Pin # 31

DACOUTB ANA header, Pin # 11 Pin # 30

PWM1A Pin # 49 Pin # 80

ECAP1 (via Input X-bar) Pin # 75 (GPIO24) Pin # 55 (GPIO24)

controlCARD and LaunchPad LED Mapping

Function controlCARD LaunchPad

LED – Power LED D1 (green) LED1 (red)

LED – GPIO31 / GPIO23 LED D2 (red) LED4 (red)

LED – GPIO34 LED D3 (red) LED5 (green)

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F280049C Experimenter Kit

Docking Station and LaunchPad Pin Locations

Stand-Alone Operation (No Emulator)

When the device is in stand-alone boot mode, the state of GPIO24 and GPIO32 pins are used to
determine the boot mode. On the controlCARD boot mode selection switch S1 controls the boot
options for the F280049C device. This switch is installed with 180 degree rotation. Check that
switch S1 positions 2 and 1 are set to the default “1 – up” position (both switches up). This will
configure the device (in stand-alone boot mode) to boot from flash. Details of the switch positions
can be found in the controlCARD User’s Guide.

A-4 TMS320F28004x Microcontroller Workshop – Appendix A