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49 views35 pagesChapter 2 - Propositional Logic & Hardware
Chapter 2- Propositional Logic & Hardware
Uploaded by
kedarprjCopyright
© © All Rights Reserved
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21
Introduction
Studying logic is important because it provides us a
way to support our claims to truth. It is tempting to
say that logic arguments establish the truth of their
conclusions. As a field of study, we can define logic
in many ways. We may say that logic is all about
arguments. It is a formal method of reasoning. In the
context of logic, an argument is not a quarrel or
dispute, but an example of reasoning where a state-
ment offers support, justification, ground, reason or
evidence for another statement. ;
As earlier said that logic is a formal method for
reasoning. Logic can be symbolically represented in
many ways. One such way of doing so is
propositional logic. This chapter is dedicated to the
study of propositional logic, digital logic and hardware.
= us begin with the discussion of propositional
logic.
Propositional Logic
The propositional logic represents logic through
"propositions and logical connectives. We may define
Proposition as an elementary atomic sentence that
may take either true value or false value but may not
take any other value.
introduction
Propositional Logic
Basic Logic Gates
More about Logic Gates
Applications of Logic Gates
Scanned with CamScanner 64
22.
les * ith
ing examP” ition as it may either be true op
the following ress @ Pe ropes ition as it is true] Fay
‘Tt is alse sition as it is false]
ition as it does not result in
Consider
on,
australia have Tt is not a Pre the similar reas Fly
dia is @ condiment vie a proposition fOr OM aby
what did you eat ? t a |
a this Topositio,
ome statements. After this J ripesition iy
led sentences OF bols used in ry ~
tions are also cal t terms and syn sentence that may »,
peta Jet us now talk abou! be true ot false jy a
i ond logic. take no other valie
pro
i ition as a part. We wi, |
any other proposi Part. Wey
ition i that does not contain. pai
ae Po in na ae as symbols for simple statements or propositions,
case letters, Py r+ : ™ |
pula ition is one with two or more simple propositions as Parts or what weng
See ee x cmreueTl ofacompound is any whole proposition that is part fa lage
omy
es j components may themselves be compounds.
For example, following are compound propositions :
Terms and Symbols
It is raining and wind is blowing.
Take it or leave it. .
If you work hard then you will be rewarded.
An operator (or connective) joins simple propositions into compounds, and joins compoust
iple prop iP i
into larger compounds. We will use the symbols, +, , =>, and <> to designate the sertst!|
connectives, They are called sentential connectives because they join sentences (or what we |
cating statements or propositions). The symbol, ~, is the only operator that is not a connect
a ae statements only, and does not join statements into compounds. |
ie symbols for statements and for ‘i 5 i ae
Parentheses serve as punctuation, *® COMPHise Our notation or symbolic lang
Different types of connectives (
. (or oy ) used in iti ven below
1. Disjunctive (Also called OR), Repro Eee sl
of the two arguments is true or baie ated by symbols + or v. Disjunction 7 EY
' . “Ber me
either p is true, or is true, or ne P*4q (or py q) means p OR @.Its
2 Conjunctive (Also
perators)
called AND), p,
“undif]
means both arguments are true o ‘epresented by symbols . or & or © Conjun
both pand 4 are true, ‘& P-4 (or p&q) meang 5 AND 4, Its
3. Conditional (Algo,
|
called If. Th, |
= Then : |
Implication means if one oy, E™Plicati “|
‘on), =o?
P>qer pq) BUMEnt is true py Presented by symbols OF”
‘ fans If p €n other argument is true ¢.$ ?
4 Bi-conditional (Also cay eahing is if 5, os
Represented by Symbols « and 9, P is true, then q is
o
ny
- Y If or Equivalence).
Scanned with CamScanner PROPOSITIONAL LOGIC & HARDWARE ' no... 65
Equivalence (or bi-conditional) means either both arguments are true or both are
false, e.g. p <> q (or p= 4) means if and only if p is true then q is true. Its meaning is
p and q are either both true or both false. ;
5. Negation (Also called NOT). Not a connective actually, just an operator. Represented
by~or'or (bar). It is an operator that affects a single statement only and does not
join two or more statements e.g., ~ p (or p’ or p) means NOT p. Its meaning is p is false.
‘We can summarize the above discussion as follows : ~
Simple statements
p “pis true” assertion
~—p “pis false” negation
Compounds and connectives :
p+q “either pis true, or q is true, or both” disjunction
Pq “both p and q are true” : conjunction
p>q “if pis true, then q is true” implication
peq “pand qareeither both true or both false” equivalence
Implication statements (p=> 4) are sometimes called conditionals, equivalence statements (p <> 4)
are sometimes called biconditionals.
Well-formed Formulae
‘As mentioned earlier, propositions are also called sentences or statements. Another term
formulae or well-formed formulae also refer to the same. That is, we may also call well
{formed-formula (wff) to refer to a proposition.
Truth values and Wit
Every simple or compound proposition may take an either true value or false value. These true
(also denoted by 1) or false (also denoted by 0) are also called truth values. We may define
truth value as truth or falsity of a proposition.
The truth value of a statement is its truth or falsity. All meaningful
statements have truth values, whether they are simple or
compound, asserted or negated. That is, p is either true or false,
~pis either true or false, p+q is either true or false, and so on.
A compound statement is truth-functional if its truth value as a whole can be figured out
solely on the basis of the truth values of its parts or components. A connective is
truth-functional if it makes only compounds that are truth-functional. For example, if we
knew the truth values of pand of q, then we could figure out the truth value of the compound,
p+4, Therefore the compound, p+4q, is a truth-functional compound and disjunction is a
‘truth-functional connective.
All four of the connectives we are studying (disjunction,
conjunction, implication, and equivalence) are truth-functional.
Negation is a truth-functional operator. With these four
connectives and negation we can express all the truth-functional
telations among statements. A truth table helps us express it.
Sree RGeRETE)
of falsity of a)
Proposition, =
So
Scanned with CamScanner (i) Negation (NOT) .
(i) Disjunction (OR)>
(ii) Conjunction (AND)
to make truth tables for
Let us now learn
it is also called unary connecti.|
ition, thus, ta
willbe denoted by ~ por p’ or Plt pi)
pis 0 (false). The truth table fort
orks on single proposition,
roposition, then its negation
and if p is 1 (true) then ~
The NOT operator w
sometimes. If p denotes a p?
0 (false), then ~p is 1 (true)
operation is shown as follows +
Table 2.1 Truth table for Negation (NOT)
P
0
1 0
Also note that
NOT (NOT p) results into p itself ice, |
B=p
or @y=P
or ~ (~p) = PB
sie
‘The OR connective works with more than one proposition. The compound p +4 has two (
component propositions (p and 9), each of which can be true or false. So there are four @)
possible combinations. The disjunction of p with q (denoted as p+q,0r py q) will be te
whenever p is true or q is true or both are true. Consider the truth table given below :
Table 2.2 Truth table for Disjunction (OR)
b [iter
0 0. 0
0 1 1
1 0 Toiiuel
1 1 1
The AND connective also works with more than iti "
n 1 The com}
p-4(or p&q) will be rue whenever both p and q are tus. ee a
Table 2.3 Truth table for Conjunction (AND)
7 pa a
0
0 1 °
2 ° 0 , R |
. e 1 1 |
i
Scanned with CamScanner eEeUuVQaK"""""_—_—""_——:
seeeesencusens 67)
{x Implication (Wf. Then / Conditional)
In the conditional p => 4, the first proposition (the if-clause) p here, is called the antecedent
and the second proposition (then clause) q here, is called the consequent. In more complex
conditionals, the antecedent and the consequent could themselves be compound propositions, The
conditional p=> q will be false when pis true and q is false, For all other input combinations, it
will be true, ——~ ieee ae oa
Table 2.4 Truth table for If. Then
The conditional p=> q may be expressed as follows :
p>q=p'+q
(v) Equivalence (If and only If./ Bi-conditional) =
Abi-conditional results into false when one of its component propositions is true and the other
is false. That is, p <> q will be 0 (false) when p is 0 and qis 1 Or pis 1 and q is 0. For all other
inputs, p< qis 1.
Table 2.5 Truth table for If and only if
0
0
1
1
Hono
Hoon
The bi-conditional p <> q may also be expressed as :
Po q=pq+p'
Some Related Terms
| The propositions that have some combination of 1’s and 0's in their truth table
column, are called contingencies.
| The propositions having nothing but 1’s in their truth table column, aré called
| tautologies.
The propositions having nothing but 0's in their truth table column, are called
contradictions.
contradiction.
atements
WATE
| Two statements are consistent if and only if their conjunction is not @
Scanned with CamScanner 68 is determined by interchanging
jonal_ proposition results into a New, conditions
werse of a conditi conditional. It
on gma util
[comer i | i bacariih and consequent of given
ee 1) tga Comverse of = 9181 Pe
i | | | That is, if 3
Wil i p: tis raining. » on
| i @ + Sky 15 fot clear. ‘ry is not clear.
then, pod = if tt is raining then 5
se will be new conditional
qa p = Ifsky isnot c
as given below :
Lear then it is raining.
‘The inverse of a conditional proposition is another conditional having negate
antecedent and consequent. That is, the inverse of p=> q is p'> 7&8
p: It ds raining.
q: Sky is not clear.
then, p= q = If itis raining then sky is not clear.
pi > q' = If it is not raining then sky is clear.
| The contrapositive of a conditional is formed by creating another conditional thi|
takes its antecedent as negated consequent of earlier conditional and consequent
| negated antecedent of earlier conditional. That is, contrapositive of p=> q is ~q=-)
or G=>porg'=>p'
2.2.3 Some Equivalence Propositional Laws
‘Two sentences are equivalent if they have the same truth value under i i
eve te ty
both the sentences possess the same truth set. ae
In the following lines, we are giving some equi i
ef nes, equivalence laws used in iti ic. W
ar giving them without proofs, since their proofs ae beyond the sare ori aaee |
Table 2.6 Some Equivalence Laws
1 of p=p .
\0.p=0 ey
tebe Properties of 1
Lp=p
Commutative law
P.=4.p
8)
(P¥q)+r=p+(qg+r) Associative law
3. ~ 1 (P.g).r=p.(
pps - 4-1)
epson ‘Absorption law fF]
BP +(p+ =p at Pee =oa)+(p.0 Distributive law
(A) p= 5 ay P +(9-7)
a P-P Involution 77 i pe panpes + 9)-(p+r)
Idempot
7. 77, De Morgan's law
Complementarity law
Conditional etiminati
Scanned with CamScanner gOPOSITIONAL LOGIC & HARDWARE .
A
Tete teeeeseteeeeees 69
Let us now have a look at some examples.
Example 2.1. Construct a truth table for the expression (A.(A +
B)). What single term i i
eetaen 0? igle term is the expression
Solution.
A B ALB “(i @ea)
0 0 0 0
0 1 1 0
1 0 1 1
1 1 1 1
Looking at the table, we find that columns (A.(A + B)) and A are identical, That is, they
possess the same truth set. Hlence the given expression (A..(A + B)) is equivalent to A.
Example 2.2. Using truth table, prove that p=> q is equivalent to ~ q=> ~ p.
Solution.
; i eg Sep
1
Inco
Mone
1
0
1
From the above truth table it is obvious that columns p=> q and ~q=> ~ p are identical ie,
possessing same truth set (1, 1, 0, 1). Hence it is proved that
p> q=~q>~4q.
This rule is also called transposition.
Erample 2.3. Prove that p=> q=3 +4.
Solution,
pai
0
0
1
1
=
1
1
0
1
norols
fromthe above truth table, we find that columns p=> q and p + q are possessing same truth set
(1.1, 0,1), Hence proved that
pq = prq
Eample 2.4, Prove that p <> q=4 < p.
Solution,
Ck
“rf
ies S-ll
Scanned with CamScanner 10 = senvccccccns ‘
ot
'
From the above truth table, we find that both propositions p< qand q.& p, possess tea
truth set (1, 0, 0, 1). Hence proved that ~
peq=qeP
Example 2.5. Prove that p<=>.q = (P=>49)-(7= P)-
Solution. 3
qe
Pp
0 0
0 a
1 0
1 iT
nor
Heo
Since the columns p ¢> q and (p=> q).(q=> p) are identical, it is proved that
pq = (pP=>49)-(4= P)
Example 2.6. Consider some simple propositions given below :
A: It is raining. B: Wind is blowing. C: 1am not driving.
From these, create the following compound proportions :
(@AvVB (i) ~B_ (iif) ~B.C_ io) A.~C_(@) A+ BLC.
Solution,
(@AvB : Itis raining OR wind is blowing.
(i) ~B “: Wind is NOT blowing.
(ii) ~A.C It is NOT raining AND I am not driving.
(io) A.~C : Iti raining AND I am driving.
() A+B.C
It is raining OR wind is blowing AND I am not driving.
Example 2.7. Prove that X+1is a tautology.
Solution.
Since the column X +1 has all trues (V's) in its column,
= it is a tautology.
imple 2.8, Prove that X +X" is a tautology and X .X" is a contradiction.
Solution.
X+X'has all V's in its truth set, hence it is
is a tautology,
X.X'has all 0's in its truth set, hence it is a
is a contradiction.
Scanned with CamScanner ror i
4 Drawing Conclusions — Syllogism
2.24 While studying logic, many a times conclusions are drawn from:
ven two or more logic statements. This process, rather logical The’ Togical | process "ofl
‘ocess of drawing conclusions from given logic statements, is} drawing conclusions from
F ed syllogism. The given statements or propositions are called} give n
ones, called
premises. :
‘To draw conclusions, we may use any. of the two methods
available for it :
® Truth Table Method
® Algebraic Method
1, Truth Table Method
In this method, a truth table (TT) is drawn for all the given premises and the conclusion to be
drawn. Then a conditional is prepared having the antecedent as conjunction of all given premises
and consequent as the conclusion to be drawn. If this conditional results into a tautology (all
true’s ie, 1’s) then the given conclusion is established. For this consider thé example given
below : a
‘ , xo
Example 2.9. From premises p and p=> q, infer q.
Solution. Given premises are :
p=4
Conclusion to be drawn C: q
As per the TT method, we have to prepare a truth table for given premises p, p= q, the
conjunction of these given premises i.c., p.(p=> q) and the conclusion to be drawn i.e, q-
Also there should be a column for
PL.P2=> Cie, [p.(p>g@l>q
Our truth ‘table will look like :
q :
0 0 1
1 0 1
0 0 a
: i 1 1
rom ay
[ a truth table, it is clear that the conditional having antecedent as the conjunction
establishes [p+ ag] and consequent as the conclusion (q), is a tautology..Hence it is
i that from given premises p and P= q conclusion drawn is q.
P-
P>q
>
Scanned with CamScanner Example 2.10. From p> qandq=% Tue
Solution. Given premises are: ;
(Py p>4q
(PA): q2r -
Goncsion (Ct be drawn: p> 798 pe TT 0
re a truth table having column for
a "te p29, P2tie, Pt.P2ie, (p> 9-4
qe” ie
C(ie, p= 1) and Pl.P2=> q= n= (P
Cie, (p> 9-(
[poger] >a | ger 8 7
Oe0ee 0) 1 1 1
oo 1 1 Z 1
Ou 1 0 E
o 1 1 1 A
70: 0 0 1
1001 0 1 Lay
11 0 1 0 ing
fei 1 1 i= 1
From the table, we derive that i
P1.P2=> Cis a tautology ie., having all 1's in its truth set. Hence concluded that
rq
q=r _
p>r
(i) Algebraic Method
a ou method, to draw a conclusion from given premises, conditional elimination is carried
a oe is inplecs ct aconditional p=> qits equivalent p + q(~p + q)is substituted and thenit
een ee eel having antecedent as the conjunction-of-all premises and
Serge non, is a tautology or not. To understand this, consider
Example 2.11. From pand p= q, infer a,
Solution. Given premises are
P=>4q
Conclusion (C) to be drawn : 4,
Let us compute P1.P2=5¢
ie, (P.(p=> ql
Carrying out conditional elimination ie, substituti
=[P-(B+ql=>q , NEP awit
P+p.d>q ,
+P.)>q
we get
a
Scanned with CamScanner PROPOSITIONAL LOGIC & HARDWARE teneeeeecccemenssecsseecussesens = [3
Carrying out conditional elimination once again, we get Rl
9q)*4
p4= +7, Rule 10, table 2.6)
9 +4=1, Rule 6, table 2.6)
(1: p+1= 9, Rule 2, table 2.6)
Hence the result is established.
Example 2.12. From p=> q and q=> r, infer p=> r.
Solution. Given premises are: p=>q, q=>r
and conclusion to be drawn is p=> r.
Thus we have to establish that
[p> 9).4> > (p>)
Carrying out conditional elimination, we get
(P+9.G+ => (p+
Carrying out conditional elimination once again, we get
=(P+Q (Gr) +(P+r)
=(P +)+(9 +N+(P4N) (De Morgan’s Law)
=(P-F)+(G.7) +(P +0) (De Morgan's Law)
. =p.qtq.r+ptr
=pep.ge req? [Commutative law table 2.6]
=(B+p).(P+D+(r+q)(r+7) [Distributive law p+qr=(p+4)(p+n)]
=1.(p +9) +(r+q)-1. [- p+ par+F=]]
=p+atr+q=prr+g+q
=persl fe 7+q=1]
=p+1 fe nets]
=1 [e p+1=1]
Hence the result is established.
The inference rules established in above examples are also known as Modus ponens and Chain
rule, That is, Modus Ponens is
P
p=4
7.
Chain rule is p=>q
q=r
p>r
Scanned with CamScanner 7 oe e eee eee
Pome yan : oe that may either be rue or fatse 0 7 watue,
ry atomic zeae
ir Of ‘ition a:
‘A simple proposition is one that does not contain any other pl pos es
. e propositions a5 Parts:
A connective joi ns ‘compounds into larger compounds.
join in 7
ive joins simple propositions into compounds and joins °
oe disjunctive, conjunctive, conditional, bi-conditional and negation.
isi q ,
A proposition is an elemental
‘A compound proposition is one with (#0 OF
Different types of connectives are
The negation is a unary connective.
Well-formed formula (wff) refers t0 sentences or propositions Or statements.
‘Truth value is defined as truth or falsity of @ proposition.
‘A truth table is a complete list of possible truth values of a proposition.
‘The logical process of drawing conclusion from propositions is called syllogism.
The propositions used to draw conclusion are called premises. :
‘Two inference rules are Modus Ponens and Chain rule.
‘Modus ponens is p
p>a
ae
+ Chain rule is p=>4q
q>r
pSr
ny
System of logic was constructed lon,
ig long ago by Ari
cme oc pc i eo ee
some Wt organization of man’s reasoning. For centuries after the subjett contrat
y logic problems using conventional cee en
gebra but only George Boole
TY paper ‘An ee with his own mathemat!
‘BOOLEAN ALGEBRA’.
Boole’s work remained confit
work ined to
paper titled “A Symbolic Analysis oe
ers only until
19.
Boolean Algebra to solve relay loge protieg te 38 when Claude E. Shannon wrot,
. Bic ing Circuii 6
eer algebra effectively deals vi gene AS logic ce In this paper he apo
: e binary valuge noms are binary decision’
ues,
After Shannon applied boolean algebra j Thus it is also called “switeti®
boolean algebra could be applied to con “Phone switch
In the ters, the ™mputer tching circui wt
computers, these boolean operat electronics as wenn” menees realized
§ ions are well. :
Perfo
"med by logic gates,
Scanned with CamScanner What is a Logic Gate ?
Gates are digital (two-state) circuits because the input and output signals are either low
voltage (denotes 0) or high voltage (denotes 1). Gates are often called logic circuits because they
can be analyzed with boolean algebra.
‘There are three basic logic gates and four others :
Z 1. Inverter (NOT gate)
2. OR gate
3. AND gate
7
2.3.1 Inverter (NOT Gate)
‘An inverter is also called a NOT gate because the output is not the
same as the input. The output is sometimes called the complement
(opposite) of the input.
‘A gate is simply an
electronic, circuit which
‘operates on one or more
signals to. produce an
input signal a
put signal ;
output state is always the
opposite of the input state.
Following tables summarize the operation.
ma 7 Truth Table for NOT gate Table 2.8 Alternative truth table for NOT gate
; ae
‘ x eae RXR
Low High vA 2
High 4 Low Y a
o ely
A low input i., 0 produces high output ie, 1, and
vice versa. The symbol for inverter is given in
adjacent Fig. 2.1. po Figure 2.1 NOT gate symbol
2.3.2. OR Gate 4
Ifall inputs are 0 then output is also 0. If one or more inputs are 1,
RR o
the output is 1./ more input signals. but
. r ‘only one output ‘signal. If:
‘An OR gate can have as many inputs as desired. No matter how | Snyof the iat signal |
many inputs are there, the action of OR gate is the same: one or fy (high), the output signal |
more 1 (high) inputs produce output as 1. Following tables show { js. :
OR action :
Table 2.9 Tut Table for two input OR gate Table 2.10 Truth Table for three input OR gate
- a
0
1
1
FeX+Y a
1 \
J) ee
7 =X4¥+
1
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teis given below * JS
“n
on
, .
=p 2
- o (0) Four input OR gate,
(6) Three input OR gate
‘The symbol for OR 83!
n
vow»
7
SANTOR
a
two or more than
input signals and prog”
one output signal, wy,"
all the inputs are 1 j,
high then ‘the outpu i)
otherwi @ Output is 0,
Figure 2.2 (a) Two input OR gate
2.3.3 AND gate
If any of the inputs is
inputs must be 1.
‘An AND gate can have as
tables illustrate AND action.
0, the output is 0. To obtain output as 1, all
many inputs as desired. Following
Table 2.11 Two input AND gate Table 2.12 Three input AND gate
ne Gey enaee | WSFaa
o of 0 0 0 0 0
o 1]o 0 0 1 0
' 4 0 1 0 0
0 1 1 0
1 0 0 0 :
1 0 1 0 Here,
The symbol for AND is S : | t ee
1
Aa— A—
BS oar =)-—
cool F
Figure 2.3 (a) 2-input AND gate
2.4 More About Logic Gates
We have covered three basi
asic logi
gates also which are derived frog aes S
red fro rok
more popular than NOT, OR faa ae a Ee oe See ae se
'& AND, OR and NOT). These gots
; gales’
introduces NOR AND
» WAND, XOR, xNOAND and are wi
2.4.1 NOR Gate OR gates, MSIY used in industry. This so
com>
mn
(6) 3-input AND gate (0) &i
‘input AND gate
FFeither of the two input j
: put is 1 (hi,
NOR gate is nothing but inverts a the output wit a
The NOR gate can have as a 0 dow). aon gies
how many inputs are there, the, MPUts as ee nt i
ail0 Gav} urea Te, the action of No} desired. Ny, more input signals 'y
Follow luce output ag 1 NOR gate ig pn® Matter | Only one ouput ser,
Anitngmh tan same ie, all the inputs are 0 (7
“14) illustra low), then the
te NOR signal is 1 (high) _
ction,
Scanned with CamScanner pROPOSITIONAL LOGIC & HARDWARE
Table 2.13 2-input NOR gate
w-
=>
Y
Zz
@
Figure 2.4 (a) Logical meaning of NOR gate (b) 2 input NOR gate’ (c) 3 input NOR gate (d) 4 input NOR gate
2.4.2’ NAND Gate /
NAND gate is inverted AND gate. Thus, for all 1 (high) inputs, it
produces 0 (low) output, otherwise for any other input
combination, it produces a 1 (high) output. NAND gate can also
have as many inputs as desired.
NAND action is illustrated in following Truth Tables (2.15 and 2.16).
Table 2.15 2-input NAND gate’s table Table 2.16 3-input NAND gate’s table
all of the we
(igh), then. the output’
Produced is 0 (low) |
zl Svar SES
4.0 ©
won of
orn »
om
|
Wp ws © © 08>
BH eeHHnoo
Rononrone
Cone ee eh
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‘The logical meaning of NAND gate can be shor
x E
yr
ID gates are given below :
The Py of 2, 3, 4 input NAN!
Figure 2.5 (a) 2-input NAND gate (8) 3-input NAND gate (€) 4-input NAND gate.
2.4.3 XOR Gate (Exclusive OR Gate)
In boolean algebra ® sign stands for
XOR operation. Thus A XOR B can be
written as A ® B.
Following Truth Tables (2.17 and 2.18)
illustrate XOR operation.
Table 2.17 2-intput XOR gate.
Odd
&
Figure 2.6 (a) 2-input OR gate
o
g
§
How HH © © ofof:
nn oon ole
v
The symbols of XOR gates are given below :
f.-3)
. (©) 3input x0R gate (oe ”
XOR addition can be summarized as foll -input XOR gate.
lows:
990-0; 081-1; 1g
4 1; 1150
Scanned with CamScanner Ad XNOR Gate (Exclusive NOR gate) Eee eal
ae ot oa ‘OR gate followed by a NOT gate (inventor
Following Tables 2.19 and 2.20). | Thus'XNOR produces 1 (high) output when the f z |
{Illustrate XNOR action. O combination has: even number of, ars
m sae |
0 Table 2.19 2 input XNOR gate Table 2.20 3-input XNOR gate
No. of 1's | No. of Songs
even/odd \( ~ Kir vitae eetaraline Maize |r.
Even 0 0 1 Even | 0 0 0 1
Odd 0 i. 0 Odd | 0 0 1 0
odd 1 0 0 Odd | 0 1 0 0
Even 1 1 1 Even | 0 1 1 1
=
Odd | 1 0 0 0
Even | 1 0 1 1
Even | 1 1 0 1
Following wie the XNOR gate symbols of ene O88. | achugeas tee oe te | AO
A
> SD-— =>
Figure 2.7 (a) 2-input XNOR gate (b) 3-input XNOR gate (c) input XNOR gate.
‘The bubble (smalll circle), on the outputs of NAND, NOR, XNOR gates represents complementation.
Now that you are familiar with logic gates, you can use them in designing logic circuits.
Example 2.13, tee a circuit to realize the following : F(a, b, = AB+AC +B AC
oy
Solution. The given boplean expression can also be written as flows wiv
‘
F(a,b,Q=A.B+A.C+B.A.C ;
ot F(@,b,=(A AND B) OR (A AND (NOT ©) OR ( (NOTE) AND (NOT 5) ANDO)
Now these logical epataions can easily be implemented in form of logic gates. Thus circuit
diagram for above expression will be as follows.
c
: AND AB & <
° “TN Ee
A 4G F :
c [>o BS. y Apa vaitelii
ste pnw ¥ B22 .
boa 7
c a
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. I ce
NOR Gate/{Exclusive NOR gate) The XNOR Gate is logicail
244 x to XOR Le., XOR gate followed | ye
Following Tables (219 and 2.20). | Thus XNOR produces 1 (high
illustrate XNOR action.
A
alent to an invented
@NOT gate (inventor),
output when the input,
bination has even number of 1's, |
Table 2.19 2 input XNOR gate Table 2.20 3-input XNOR gate
Me goad || Mes wie BS PAN Bae
Even 0 0 Even | 0 0 0 + 1
Odd 0 1 Odd | 70-20. 1° | 9
Odd 1 0 Odd 0 1 0 0
Even i 1 Even. 0 1 a 1
Odd 1 0 0 0
Even 1 0 A 1
Even 1 s 0 1
Following are the XNOR gate symbols : ear | aaiGes Gey mrasictal,
Figure 2.7 (a) 2-input XNOR gate (6) 3-input XNOR gate (c) 4-input XNOR gate.
The bubble (small circle), on the outputs of NAND, NOR, XNOR gates represents complementation.
Now that you are familiar with logic gates, you can use them in designing logic circuits.
Example 2.13, Design a circuit to realize the following : F(a, b, = AB+AC +B AC
Solution. The given boolean expression can also be written as follows :
F(a,b,=A.B+A.C +B.A.C
or F(a,b, ) =(A AND B) OR (A AND (NOT C)) OR ( (NOT B) AND (NOT B) AND C)
Now these logical operators can easily be implemented in form of logic gates. Thus circuit
diagram for above expression will be as follows.
, "e C13
[-~) ~ —e—*
A c F
v2 ano 4°. } on)»
AB+AC+ BAC
K-
ae
= Scanned with CamScanner BO. eeeeeee
ction
I circuit for the fur
the diagram of digital
Example 2.14, Draw #
tah (&+2)- (v+2)
“a6 be written as
. Above expression can 2
om Fk, ¥,2)= 0 OR ¥) AND ((NOT ) OR (
‘Thus circuit diagram will be
NOT Z) ) AND (Y OR Z)
+ Y):(X+Z).(¥+Z)
245 NAND to NAND and a to NOR Design
We can design circ circuits using ig AND, OR, NOT gates as we have done so far, but NAND ani
NOR gates are more popular as these are less expensive and easier to design. And also ote
switching functions (AND, OR) can easily by implemented using NAND/NOR gates, Ths
NAND, NOR gates are also referred to as Universal Gates,
NAND-to-NAND Logic
AND and OR operations from NAND gates are shown yee
x
Pe,
Figure 2.8 AND operation using NAND-NAND fs
AND operation using NAND is
Proof. X NAND Y
|
(XNAND ¥) NAND (X NAND 1) (De Morgan's Second Tha |
= (+ Y)NAND(X +7) |
) (De Morgan's Second Theo™
(De Morgan's First Theor
ae)
exert
—_—
Scanned with CamScanner xe WY DS 7 ey
& Yr
TF F [nwo p— vy ‘ =.
my
—
Figure 2.9 OR operat Wrusign NAND to NAND logic.
ion using NAND is / / a
OR operation using Sere Snemr
(REY=& ?
S (De Morgan's Second Theorem)
a (X+X=X)
similarly, YNANDY =Y / er cal
(De Morgan's Second Theorem)
G (X=X,Y=y/)
al
NOT operation using NAND gates is
Proof, XNANDX=X.X=X / (+ X.X=X)
NAND-to-NAND logic is best suited for boolean expression in Sum-of-Products form.
in a for
[esi Ait ty ig A SU
1 Re es ee seat
Ll ieee A iat tg Mh
iietagietct a Ne
‘xample, xz +2ZX can be drawn as follows :
/
x
4 ’ a
“ee Zz é
_ z
x
NAND-TO-NAND logic Network (only for two-levelcir
a= y aD ae
Floure 2.44
(2) AND-to-OR implementation. (b) NAND-to-NAND implementation.
Scanned with CamScanner ital circuit for the JUN
dis
Example 2.15. Draw the ae Cont 3 xo AND gates only.
F(X,Y,
Ke written as
ion. F(X, ¥,Z)=YZ+XZ can
Solution. F( MAND) NAND CAND?)
Thus logic circuit diagram is
Yt : [wep
\ 7 -
Example 2.16. Draw the diagram Ee circuit for
F (a,b, = AB+BC+CD using NAND-to-NAND logic.
Solution. F (a,b, c)= AB+BC+CD
=(4.NAND B) NAND (B NANDC) NAND(C NAND D)
Thus logic circuit is
EE /
A
8
B
NAND
c
E —
D [ee pe)
Example 2.17. Draw the circuit diagram for
fs “-ABC+CB using NAND-to-NAND logic onl
I ly.
gi
(A) NAND (NOT B) NAND (©) NAND (WoT C) NAND B) “¥
\
Solution,
Thus logic circuit is
wa
A— Z®&
AD [nop © K @
F
Pes
a
NOR-o-NOR Logic
A
Sei 8 De [no aed
Fig
jure 2. i
12 OR operation using NOR to NOR Io"
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{NOR A) NOR @NOR)|
>
Figure 2.13. AND operation using NOR to NOR logic.
ioropesa _ A 7) >- a
[NOT AZ ANOR A)
Figure 2.14 NOT operation using NOR Logic
NOR-to-NOR logic is best suited for boolean expression in Product-of-Sums form.
Design rule for, N'
networl K {only, for, 2-level
ni
Se mi lp id fag I Su HN Ae i
i rhea ak an ‘ci mane i
aa
it
For example, (X + Y)(Y +Z) (Z +X) can be implemented as follows :
, a
¥ Y
y _ _ 3
z |e) KHWIYHZEX) Zz OC YY DIZ +X)
Zz
>
(a) (b)
Figure 2.15 (a) OR-to-AND implementation (b) NOR-to-NOR circuit.
Example 2.18, Represent (X + ¥)(Y +Z)(Z+ X) in NOR-to-NOR form.
Solution. (X + ¥)(Y +2) (Z+X) = (K NOR Y) NOR (¥ NOR Z) NOR (Z NOR X)
a Xt
y
Y+Z
Or HUY D+)
\
N <
Z+x
NOR)
x ON
Scanned with CamScanner B+C) ee OBI Neb
Example 2.19. Represent
Solution, aa
Cr)
B+ usi ly.
Example 2.20. Show A(B +C) using NOR gates om ly.
Solution. sae
&+@+o)
>t
A (B+)
. A(B+C)
2.5 Applications of Logic Gates
The design and maintenance of digital computers are greatly facilitated by the use of baz
algebra and logic circuits. Logic networks are designed making use of logic gates.
Logic gates have several applications to the computers. These are used in following wi
applications :
1. ADDERS
- Half Adder
~ Full Adder
2. Encoders
3. Decoders
and many more, However, we are
, We are going to cover A
os oe * Adders only, as per the syllabus.
We are familiar with ALU (Arithmetic 1: ;
operations. But ALUs do nor geile Logie Uni) wii Performs all arithmetic alt
t Process deci
adders in ALU also work on binary Tae ‘numbers ; they process binary numbes
Before we get into details, all
Youneed to know is rules for Bir inet
o:00 for Binary addition, which are give
I+l4ten
See, the result ishaving two bits, ghee
BES YoU the Sim - soci
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poeNe
Half Adder
It isa logic circuit that adds two bits. It produces the outputs : SUM and CARRY. The ‘boolean
equations for SUM and CARRY are : "
| SUM is X XOR Y; and CARRY is X AND Y. |
‘Therefore, SUM produces 1, when X and Y are different and CARRY is 1 when X and Y both
are 1’s. Truth Table for Half Adder is given in (Table 2.21).
Table 2.21 Truth Table for half adder
Xe RY: “Carry Sum
0 0 0 0 ap
0 1 0 1
1 0 0 1
1 i 1 0
Logic circuit for Half adder has been given in Fig. 2.16.
x Y
‘CARRY
Figure 2.16 2-input Half adder.
Applications of Half adder are limited as only two bits can be added. Instead we need a circuit
that can add three bits at a time.
Full Adder
nee logic circuit that can add three bits. It produces two outputs : SUM and CARRY. The
Solean equations for SUM and CARRY are : (Refer to Truth table 2.21)
—— srernone
Z+XYZ) a Lae ;
CARRY =XY4+YZ4+2ZX (Simplified from expression XYZ +XYZ+XYZ + XYZ)
“| SUM equals X XOR Y XOR Z.. Bec |
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produces 1 when input is containing odd number of 15 and CARRY,
’s in i it.
when there are two or more 1’s in input
‘rath Table for Full Adder is given below (Table 2.22).
- Table 2.22 Truth Table for full adder
‘Therefore, SUM
0
a XYZ
1 XYZ
0
1 XYZ
0
0
1 xyz
Logic circuit for Full Adder has been given in Fig. 2.17.
x yz
an Vor) suM
[ Jano) 2 ) on) CARRY aaa
Figure 2.17 3-input Full Adder,
+ The NOT gate or inverter is a
opposite of the input state,
: meee (igh). "PM anals bu only one output signal If any ofthe input signals is 1 (high
fame otherwise capa asa and produce an output signal When a the inputs are 1 iit
: sara ‘wo or more Input signals but only one ouput signal, If.all the inputs are 0 (i.e., low), hen
{gate has two or more input signals but on} : eu
‘output produced is 0 (low), Y One output signal, if all Of the inputs are 1 (high), then
‘gate with only one input si
7 One input signal and one output signal; the output state is alwoys ™
fs me output. I
iber ‘Produce
anneal ts —, for only those input combinations that’ tat
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inverted XOR gate. It produces 1 (high) output when the input combination has even number of 1's.
Design rules for NAND-to-NAND logic Network : (i) derive simplified sum-of-products expression. (ii) draw a
Preuit diagram using AND, OR gates. il) just replace AND and OR gates with NAND gates.
4p Design rule for NOR-o-NOR logic Network () derive simplified P-O-S expression (i) draw a circuit using OR,
{AND gates. (il) replace OR and AND gates with NOR gates.
‘+ Zogienersork have several applications some of them are: Adders half adder, ull adder), Encoders, Decoders et.
‘Half adder is logic circuit that adds two bit.
Fall adder is logic circuit that adds three bits.
¢ ANORGate is
Aree eas
oO
struct a truth table for the expression @. What single term
aa dh
aan Renee zy
0 1 0
1 0 1
Comparing the columns a and i, we find that 7 =a. Hence the expression @ is equivalent to a.
2. Prove that x + yz =(x + y)(x+y) S
Solution.
poy |e el ey [ar | ery are
=a 0 0 0 0 0
0 o 41 0 o 0 1 o
O- ¢ a 0 0 1 0 0
o 1 4 1 1 1 1 1
1 i) 0 0 1 1 1 1
1 0 x o 1 1 1 1
1 a 0 0 1 1 1 1
a 1 1 1 1 1
Comparing the columns, we find that x + yz =(x + y)(x +z). Hence proved.
3. Verify using truth table that (x+y =x .y. /
Solution, As it isa 2-variable expression, truth table will be as follows :
aay xy Gey x ¥ xy
0 0 0 1 1 1 1
o 1 1 0 1 0 0
4. 0 1 0 0 1 0
A 1 1 0 0 0 0
Comparis
‘Paring the columns (x + y) and x’y, both of the columns are identical, hence verified.
4F is
Sart Premises p=> qand 4=> p, conclude] + pq
olution. Given premises are :
Pl: pag
RQ: gop
Bs
Scanned with CamScanner (P1. P2)>C
q it
mn TN .
Since (P1. P2)=> C results into tautology. Hence concluded.
From premises p= q and q=> p, conclude @ + pq algebraically.
Solution. Given premises are : awe
Plip= dand P2:q= p
Conclusion (C) to be drawn : 9+ pq. /
We have to find out (Pl. P2)=> C + 7
=[(P> 9).4> Pym (G+ Pa)
Carrying out conditional elimination, we get
=P+9-4+ Pl => (7+ Pa)
aaa a
Carrying out conditional elimination once again, we get
Pa). CG+ I+ (a+ pa)
Peay tp)ea+ mn SS [De Morgar’s al
-9)+(F.B)+a+ pq / [De Morgan's lal
i peteripir
for (p< 4) +(p=>
Solution. Carrying out bi-conditional elimination, eit
ge
, PS 4=(p.a)4(5.5
Carrying conditional elimination, we get P.D+(B.G) a. »)
Pianta 7: C&
Thus, the equivalent expression i
PA+ PG +p 4g, Ue,
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axons
raw logic circuit diagram for the following expression: Yxab+bc+eal +
solution.
aad the simplified logic diagram using only NAND gates to implement :
EyZ+Fpz+Fyztx7yz
+
. EVE+EVr+E a By ene
FyEsT prt Tyztx ta)ttyz+yz
Solution. YEAR yrtRyztxyz=xXy% 2) yzty
14k yztxgz/
a,
=¥y+kyztxyz
aye
+2Table 2.6)
%
Draw the logic Of NAND gate using NOR gates only. Sf
- a—f ) —
R will gi
will give A NOR B —_—
Scanned with CamScanner 90
410. (a) Represent NOT OR gatels)-
‘using only Nt
(6) Giver the following circuit = LS
FALSE and the other is TRUE ?
-
are FALSE (ii) one #8
NAND gates.
if () both inputs
What is the output
a Half Adder using only
(Q) Draw the circuit of
Solution.
( X=NOTX=XNORX
a
J
(False (i) True
(0 Inhalf adder Sum
S
>I
1
\
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eceding wffs.
13. Given wf are: p=> qand ~ 4, show that ~ pis a logical consequence of two preceding off
Solution. We have to determine [(p=> 9)-
q Sims pig 4|
1 1
rat
p> 9)s~qgl>~p
P: 1
cornet
1
1
1
Honey
Heo ofs
Honols
ooo
0
1
0
U(p= 9)-~4]= ~pisa tautology. Hence,
pq
~4
~p
Solve the previous question algebraically, 4 =
Solution. We have to determine [(p=> 4). ~q]=> ~ ao
Carrying out conditional elimination, we get. 7 4% V i
(~p+49).~ql=>~p a
+4.) ~p
efor G ae
Carrying sate conditional elimination once again, we get g
“Cpr at~p
Pt—~qt~p (+ ~(~p.~q)=~~ p+ —~q De Morgan's Lav]
+qt~p So. Ta a
=pt~ptq 7, Sf
al+q CC i. p+~pel]
=1 [eo 1+=l]
Hence established. f
15._ Construct the inverse, converse and contrapositive of conditionals given below :
S— @ Ifitis january, then it is cola, (i) Ify +547, then y <0
Solution. . ot: r
(@ Let p= q=Ifit is January, then it is cold, /
ie, 7 Pilt is January A x» Cc
qiltis cold, _/ ~ Fe
Converse will be q=> p, ie,
If it is cold then it is January,
Inverse will be ~ p=> ~ 4, ie, a
Ifit is not January then it is not cold,
Contra-positive will be ~9=> ~p, ie,
If it is not cold then it is not January,
Scanned with CamScanner ppOsiTIONAL ee
i
pistes Daley #547 then y <0 ie,
aryt5#7
JS 7 by <0
Converse will be B= 4, it,
Ify ~B i,
Ify+5=7 then y <0
Contrapositive will be ~B=> ~8 iy //
Ify ¢ Othen y+5=7.
ano gate Ao ice hse yu 4a a “tl Stly|Wwhe al inputs are ii HA
erie ining simple ali into compounds. | LAAT AEA
Gate A loge teu with| one oF tore input signals but only ene o output signal, AWE
ao gate opal means 2h AND ete folled by an in inverter. Al igs mst be io) og lom ct |
nn ate on yr means an OR gate followed by an invert -Allinpts must be 0 (ow) toget (hah i
wor gate & A sete with one input ‘ang ne cutout signal output being Le of the input i |
an gte loge cet whose outeut i 1 (high ery wien one or mor
Preston Hletnentary nomic sentence that may, yether ie re bor fale,
Sylogim Logical process of drawing conclusion fr from Even premises
Toth table table of combinations showing all in
Tats ue Trt a folly ofa propos
i
input: ond ‘output | | Poss ities for a boolean expression. |
HI) AW) i
' evan numberof of 1's to get 2
AA Al i si a Le | |
525, He Wt it only when inputs have even|number (of: tts,
Pe Aaah Fe aT A
PT
TYPE A : VERY SHORT ANSWER QUESTIONS
1. What , =Ae% oo ee
2 Unstis proposition 2
t
ae you mean by contingency, tautology and contradiction ? /
'Sa logic gate ? Name the three basic logic gates.
4 vi of
S Wie oe implement logical addition, logical multiplication and capes ion 2
& Mat e Precedence order of evaluation of logical operators. (
the other name of NOT gate ? ‘
i
OI asoan nd tea tacos See
O=2 i) A+1=2 (iii) A.O=? (iv) A.1=?
SO
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a r true:
wressions are
i i following &P! =(XY)Z
8, According to ar oe and X02)
X+#(0+Z)=
=, XZ?
9. Wich lw states that XOV + 2)=2Y © rene
10. What is the following property : a
11, What is the following property
+X.Z
an eye +¥ are known as? 4
¥ and Rule XY =X + Oe the correct forms of the incorrect ones :
se Whe a ths following iar incorrect? Waite the ie
Which of the followin a
Manat as0ea Gata eA (1) (ABy = 4'B
(¢) A+ AB=A Oe () A+AB=A4B ee
(@Ati=1 +A pat 4 (
14. What is a connective ? ; :
15. Name she process for the compounds given below : 2
@Optq (p.q (ipaq (iv)~p peg Q
16. What are contingencies ?
17, Form the saith inyerse and contrapositive of condition p=> 4.
18. What is syllogism ? |
19/ Why are NAND and NOR gates called Universal gates ?
20. Which gates are called Universal gates and why ?
ap) Ose circuit diagram using NAND or NOR gates only to implement the Boolean fun
F (a,b) =ab' + ab
22, How does half adder differ from full adder ?
25, What is inverted AND gate called ? What is inverted OR gate called 2
24. When does an XOR gate produce a high output ? When does an XNOR gate produce a high outp!
25. Write some applications of logic networks, Vy, =
TYPE B SHORT ANSWER Questi INS
ven the following simple propostions; ONS
P= It is raining
49=It is not a sunny day.
Construct the compound sentences for the fol
z lowing expressions :
OF ra Wi) pg ye Tae
Ore CDF Goi) g %. pee
2 fla) If x represents “I like coffee ras
© (P+ 9)= (p.9)
then write in symbolic form :
\ (ii) Like coffee br ;
like coff ; it cof
- coffee or tea; () Neither I ike coffee mor fea?
onot like Coffee but like tea,
~*”y stand for 2 '
() Vike coffee and tea ; = se te
(iii) It is false that I don’t
(©) Either I like coffee of
f® For what statement does
"If sstands for the statement “
Twill rt a
What does ~s+t stand for 7"! BONO schoot”, and t for
4: Fatablish the following using truth
Ho tables : a\ny
0-5-9) (a> b~ igh t
Aid) (~04 )A(~b+ a) aes p a
ett
the statement, “T will watch a movi”
03 d).65 eb sy
DP. Gay= pt gar fi
Scanned with CamScanner ppOSITIONAL LOGIC & HARDWARE 95
oR
+ will be the result of following compounds if given inputs are
(sm @x20y=1; (x=Ly=1; (ii) x=1y=0
@ysx Oyve @~xvy (@xa~y OCUssyy =)
Sie the converse, inverse and contrapositive for conditional (i) x=> y, (ii) p=> q where
xiltis raining, _-y: am enjoying it.
p:2+3#6, q=a>0 [Hint. Refer to solved problem 14]
Cin gut which ofthe following are tautologies and which of them are contradictions ?
‘a pape = Vw 40) (p> 9)-P Neos!
FOG ip. decrPnD 6 MP3 Ne ~99 (~PA~D)
So opr. Op gaq= Le
a Given that: © p:2+3=5
qi2x3=6 a &
Now construct the truth table for following compounds : A 0
5 then 2x3 =6 (i if2 +345, then 2 x3=6 0
then 2x3 #6 (iv) £2 +345, then 2x3 #6 o
: o \
jo My
ve :
Qa that (asain that eye Le
a+b a>b reory
=> b boc yz
a z
¢
38. Draw the conclusions from the following premises :
Pl: John is a father.
P2: If John is a father then John has a child,
[Hint. Modus ponens)
4 Determine whether each of the following sentences is
(©) satisiable (6) contradictory (© valid
SH(P&q)y ~(p&q) Si(Py > (P&q)
oan Sy:(pv q)&(py ~a)v p
P3qs=p ‘i =
3 fi i Sgipy q&~ py ~q&p
ind the meaning of the statement 3
(~Py q)& rosy (~r&
fore : v rea)
a fe of the interpretations given below :
a ep 18 te, ris false, sis true,
* Gis false, ris true, sis true.
do you und 4
i Srstand by ‘truth value’ and ‘proposition’ ? How are these related ?
do you und ar 3
functions, “stand by ‘logical function’ ? What is its alternative name ? Give examples for logical
* Whatis,
‘Meant
>y tautology and contradiction ? Prove that 1+ Y is a tautology and 0.Y is a contradiction.
Scanned with CamScanner sis significaree? "
is a truth table ? What is its ae each X, ¥ in. {0 is ff A
2. Hee truth table that ae Xf eh KY ith wy
ae that (X+ YT = :
truth table Beal ea |
| ae ie ple fr te Boolean EXPresio® ee 5 @ MENPHR) OM=Nery ys
2. Give th able for the following em ns: Of tray
| a, Draw the tru tin ae a
Ah, Using truth table, prove oom " they differ from the distributive Jaws of ordinary rae |
distributive laws. ane
ace - sdempotence lave withthe help of 8 an
aire the complementarity aw with the help of @
1. Prove be hl
2a. Gine the truth table proof for distributive la
29, Prove the following = ie
(9 A(B+ C+ D)=
(ii (x+y +2). y+ Daytz ‘ ‘ a
jc cirguit di lowing a>" = Me a
£ Draw logic cirguit diagrams for the in is ; N
a Oyster (i) (At mero ei (iii) AB+ BC (io) y+ 32
“af. Design a dreuit (input) which gives a high input, when there is even number of low input
qls-B. Design a circuit (3 input) which given a high input only when there is even number ‘of low orhighinng
4 Design a logic circuit to realize the Boolean function f(x,y)=x-y+x.y P
. Draw the logic circuit for this boolean equation : !
y=ABCD+ ABCD+ ABCD+ ABCD VY
(io) B+ BC+ BCD=A(AD+C) a
35./Draw the AND-OR circuit for y= ABC D+ ABC D + ABCD .
36. Convert the above circuit into NAND-to-NAND logic circuit, ¢°¥7~
37. Why are NAND and NOR gates more popular ?
38, bow the logical cacy for the following using NAND, gates only :
(ryt xpe+ (i) ABC+ ABC + ABC SW
39. Draw the logical circuits ox lowing using NOR gates only ; 2
OK. E+) E+ GO (&+Y4Z.04F 42 \
(@) State De Morgan's Laws. Verify them using truth
SO) Prove (A+ B).(A'+C)=(A+Bs0).(A i Penge
x the truth table for a Fulladdern. OTA ERATE
