2023/9/11

Semiconductor Devices Physics and Technology

S. M. SZE
M. K. LEE

PART III. SEMICONDUCTOR TECHNOLOGY

Chatper 13 Lithography and Etching

13.1 Optical Lithography

13.2 Next-generation Lithographic Methods
13.3 Wet Chemical Etching
13.4 Dry Etching
Summary

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Chatper 13 Lithography and Etching

Lithography is the geometric pattern transferring processes on a mask to a thin
layer of radiation sensitive material (called resist or photoresist) covering the surface
of a semiconductor wafer or target substrate.1 The resist patterns defined by the
lithographic process are not permanent elements of the final device but only replicas
of circuit features. To produce circuit features, these resist patterns must be
transferred once more into the underlying layers comprising the device. The pattern
transfer is accomplished by following selective etching or deposition (lift-off)
process.2
Specified topics： Considerations :
• The importance of a clean room for lithography. • Clean rooms: ultraclean
• The most widely used lithographic method — environment.
optical lithography and its resolution • The exposure tools,
enhancement techniques. • The masks,
• Advantages and limitations of other • The resists, and
lithographic methods. • Resolution-enhancement
• Mechanisms for wet chemical etching of techniques
semiconductors, insulators, and metal films. • Etching or even deposition
• Dry etching (also called plasma-assisted mechanisms
etching) for high-fidelity pattern transfer.
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13.1 OPTICAL LITHOGRAPHY

When dust particles adhere to the Particle Problems:
surface of a photomask, it may 1. [1] may result in the formation of a
cause significant Yield Loss. pinhole in the underlying layer.
2. [2] is located near a pattern edge
and may cause a constriction of
current flow in a metal runner.
3. [3] can lead to a short circuit
between the two conducting regions
and render the circuit useless.

A dust particle incorporated into the gate

oxide can result in enhanced conductivity
and cause device failure due to low
breakdown voltage.

Fig. 1 Various ways in which

dust particles can interfere
with photomask patterns.3

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13.1.1 The Clean Room

Example:
A class 100 clean room (English system)：
a dust count of 100 particles/ft3 with particle
diameters of 0.5 μm and larger.

A class M 3.5 clean room (metric system) ：

a dust count of 103.5 or about 3500
particles/m3 with particle diameters of 0.5
μm and larger.
100 particles/ft3 = 3500 particles/m3
class 100 English system = class M 3.5 metric system.

For the lithography area, a class 10 clean room

or one with a lower dust count is required.

Fig. 2 Particle-size distribution curve for

English (- - -) and metric (—) classes of
clean rooms.4
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13.1.1 EXAMPLE 1
EXAMPLE 1
If we expose a 300-mm wafer for 1 minute to an air stream under a laminar-flow
condition at 30 m/min, how many dust particles will land on the wafer in a class-10
clean room?

SOLUTION For a class 10 clean room, there are 350 particles (0.5 μm and larger)
per cubic meter. The air volume that goes over the wafer in 1 minute is

• The number of dust particles (0.5 μm and larger) contained in the air volume:
350 × 2.12 = 742 particles.
• If there are 800 IC chips on the wafer, the worst Production Yield (%) =8%
• Only the particles that land and adhere to a circuit location critical enough will
cause a failure.
• The calculation indicates the importance of the clean room.

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13.1.2 Exposure Equipment

(a) Contact printing：
• may have the mask and wafer
in direct contact
• provides a resolution of ~1 μm
• suffers a major drawback
caused by dust particles and
mask damages

(b) Proximity printing：

• There is a small gap (10–50 μm)
• The resolution is degraded to
the 2–5 μm range
• Less dust particle and mask
Fig. 3 Schematic of Exposure Equipment damage problems
(a) contact printing, (b) proximity printing.
The performance parameters:
1. Resolution：the minimum feature dimension
2. Registration：pattern accuracy
3. Throughput： the number of exposures per hour
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13.1.2 Image-partitioning Techniques

Fig. 4 Image-partitioning techniques for The small image field can also be
projection printing: stepped over the surface of the wafer
(a) annual-field wafer scan, by two-dimensional translations of the
(b) 1:1 step-and-repeat, wafer only, while the mask remains
(c) M:1 reduction step-and repeat, and stationary.
(d) M:1 reduction step-and-scan.6,7
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13.1.2 A Simple Image System

(1) In shadow printing, the minimum

linewidth [or critical dimension (CD)] that
can be estimated as：
CD  g

(2) The resolution of a projection system

lm is determined by diffraction limit：

lm  k1
5

NA
CD: the minimum linewidth (3) The numerical aperture, NA is given by
NA = n sin  n sin(tan D / 2 f )  n ( D / 2 f )
1
λ : the exposure wavelength
g : the gap between the mask and wafer
lm : the projection system resolution (4) Depth of focus，DOF：
k1 : the process-dependent factor
 lm / 2  lm / 2 
NA : the numerical aperture DOF    k2
n : the index of refraction of the lens tan  sin  ( NA) 2
θ : the half-angle of the cone of light converging
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13.1.3 Masks
1. Use a computer-aided design
(CAD) system in which
designers can completely
describe the circuit patterns.

2. The digital CAD data drives a

pattern generator, which is an
electron-beam lithographic
system (Section 13.2.1).

3. The mask consists of a fused

silica substrate covered with a
chrominum layer.

4. The circuit pattern is first

transferred to the electron-
Fig. 6 An integrated-circuit photomask.1. sensitized layer (electron resist),
which is transferred once more
into the underlying chrominum
layer for the finished mask.
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13.1.3 Mask Defect Density

The yield is defined as the ratio of
good chips per wafer to the total
number of chips per wafer. As a
first-order approximation, the yield
Y for a given masking level can be
expressed as：

Y  e  DA (5)

where D is the average number of

“fatal” defects per unit area and A
is the area of an IC chip. If D
remains the same for all mask
levels (e.g., N = 10 levels), then
the final yield becomes：

Y  e  NDA (6)

Fig. 6 An integrated-circuit photomask.1.

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12.1.3 Yield of Lithographic Process

Example :

D = 0.25 defect/cm2,

the yield is 10% for a chip

size of 90 mm2,

It drops to 1% for a chip

size of 180 mm2.

Fig. 7 Yield for a 10-mask lithographic process with

various defect densities per level.
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13.1.4 Photoresist

Typical Process Steps :

1) dehydration and priming;
2) resist coating;
3) soft (or hard) baking;
4) exposure;
5) development;
6) rinse
7) drying
8) inspection.

1
  ET  E1 : the lithography energy dose
  ln  ET : the threshold energy
  E1  γ : the contrast ratio

Fig. 8 Exposure-response curve and cross section of the resist image

after development.1 (a) Positive photoresist; (b) negative photoresist.
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13.1.4 EXAMPLE 2
Find the parameter γ for the positive and negative photoresists
shown in Fig. 8.。

For the positive resist, ET = 90 mJ/cm2 and E1 = 45 mJ/cm2:

1 1
  E1    90 
  ln   ln   1.4
  ET    45 

For the negtive resist, ET = 7 mJ/cm2 and E1 = 12 mJ/cm2:

1 1
  E1    12 
  ln   ln   1.9
  ET    7 

The chemical amplified resist (CAR) has been developed for the
deep UV process with excellent solubility contrast between the
exposed and unexposed regions.

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13.1.5 Pattern Transfer

Fig. 9 Details of the optical lithographic
(a) Application
of resist pattern transfer process.8
1) Dehydration and priming：To ensure
satisfactory adhesion of the resist. The
most common adhesion promoter for
(b) Resist silicon ICs is hexa-methylenedi-siloxane
exposure (HMDS).
2) Resist coating; Spin coating: e.g. speed
(2000–10000) rpm for about 25~35
seconds 0.5 to 4.0 μm (a)
3) Soft or hard baking: e.g. at 95°–120°C
for 40–120 seconds (a)
4) Exposure: e.g. UV lamp 365 nm,
(c) Development
220~350 mW/cm2 for 1.5~6.0sec) (b)
5) Development: AZ 300 MIF (35-45sec ~2
μm photoresist thickness at RT) (c)
6) Rinse
(d) Etching
7) Drying (spin dry, blow dry, post-bake)
8) Inspection.
(d) Etching of SiO2 + (e) Removal of resist

(e) Removal of 15
resist

13.1.5 Pattern Transfer

Wet Photoresist Stripping

• The photoresist strippers ：
H2SO4, H2SO4-Cr2O3 (acid-
oxidant combination) attacking
the resist but not the oxide or
the Si.
• Organic-solvent strippers
• Alkaline strippers.
• Acetone for postbaking < 120 oC

Dry Photoresist Stripping

• Oxygen plasma post-bake >140
oC

Fig. 10 Liftoff process for pattern transfer. • The barrel plasma reactor
(a) Resist exposure through the mask. • UV/ozone stripping
(b) Resist development and post back
(c) Film deposition. (d) Liftoff (resist stripping).
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13.1.6 Resolution Enhancement Techniques

(1) Phase Shift

Technology

(2) Optical d = λ/ 2(n-1)

Proximity
Correction

(3) Immersion
Lithography

Fig. 11 The principle of phase-shift technology.

(a) Conventional technology; (b) phase-shift technology.9
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13.1.6 Resolution Enhancement Techniques

(1) Phase Shift

Technology

(2) Optical
Proximity
Correction

(3) Immersion
Lithography

(a) (b)
Fig. 12 Optical proximity effects.
a) Round corners by standard mask.
b) Accurate line shape by OPC mask.
.

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13.1.6 Resolution Enhancement Techniques

(1) Phase Shift

Technology

(2) Optical
Proximity
Correction

(3) Immersion https://en.wikipedia.org/wiki/Immersion_lithography

Lithography
Immersion lithography is a photolithography resolution
enhancement technique for manufacturing integrated circuits (ICs)
that replaces the usual air gap between the final lens and the
wafer surface with a liquid medium that has a refractive
index greater than one. The resolution is increased by a factor
equal to the refractive index of the liquid. Current immersion
lithography tools use highly purified water for this liquid, achieving
feature sizes below 45 nanometers

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13.2.1 Electron-Beam Lithography

• Electron-beam lithography is primarily
used to produce photomasks.
• The resist is directly exposed by a
focused electron beam without a
mask.
• The scan field (typically 1 cm)
on and of
(MHz ) The advantages：
• greater depth of focus
• without using a mask
• automated precisely operation (nm)

The disadvantages
• low throughput 30min/wafer
• high cost

Fig. 13 Schematic of an electron-beam machine.10.

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13.2.1 Electron-Beam Lithography

One can save time by

using a vector-scan
system.
raster scan vector scan
The vector scan
method using
variable-shaped beam
has higher throughout
than the conventional
Gaussian spot beam.

Fig. 14 (a) Raster-scan writing scheme; (b) vector-scan writing schemes;

(c) shapes of electron beam: round, variable, cell projection.12
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13.2.1 Electron-Beam Lithography

Positive electron resists
Common positive electron resists
include poly-methyl methacrylate
(PMMA) and poly-butene-1 sulfone
(PBS). Positive electron resists can
achieve resolutions of 100nm or
better.
(a) Chemical bonds are broken to form
shorter molecular fragments
Negative electron resist
The cross linking creates a complex
three-dimensional structure with a
molecular weight higher than that of
the nonirradiated polymer. Poly-
glycidyl methacrylate-co-ethyl
acrylate (COP)

(b) Radiation-induced polymer linking

Fig. 15 Schematic of (a) positive and (b) negative resists used in

electron-beam lithography.13
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13.2.1 Electron-Beam Lithography

The Proximity Effect

Fig. 16
(a) Simulated trajectories of 100 electrons in PMMA for a 20-keV electron beam
incident at the origin of a 0.4 μm PMMA film on a thick silicon substrate.14 .14
(b) The normalized dose distribution for forward scattering and backscattering at the
resist-substrate interface.
• The electron-beam irradiation at one location will affect the irradiation in
neighboring locations. This phenomenon is called the proximity effect. The
proximity effect places a limit on the minimum spacings between pattern features.
• To correct for the proximity effect, patterns are divided into smaller segments
(need re-correct the exposure dose => further decreases the throughput )
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13.2.2 Extreme-Ultraviolet Lithography

EUV lithography can print 50-nm

features with PMMA resist using
13.5-nm radiation (50~13nm or
even better)

High-NA EUV => 3nm

Soft X-ray : (1~2 nm)

Fig. 17 Schematic representation of an extreme-

ultraviolet (EUV) lithography system.15.
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13.2.3 Ion-Beam Lithography

Two types of ion-beam Advantages：
lithography systems: The backscattering is
completely absent for
1. A scanning focused- the silicon substrate,
beam system and there is only a
2. A mask-beam system. small amount of
backscattering for the
gold substrate.

Dis-advantages：
A random (or stochastic)
space-charge effect,
may cause broadening
of the ion beam.

Resolution: ~2nm

25
Nagarjuna Ravi Kiran, Manvendra Chauhan, Satinder K. Sharma, Subrata Ghosh*, and Kenneth E. Gonsalves* , Resists for
Helium Ion Beam Lithography: Recent Advances, ACS Appl. Electron. Mater. 2020, 2, 12, 3805–3817, November 24, 2020
https://doi.org/10.1021/acsaelm.0c00627

13.2.4 Comparison of Various

Lithographic Methods
Each method has its own limitations. It is not necessary to use the same
lithographic method for all levels. A mix-and-match approach can take advantage
of the unique features of each lithographic process to improve resolution and to
maximize throughput.
Table : Comparison of various Lithography techniques.
126 nm Electron
Parameter EUV X-Ray Ion Beam
optical Beam
Effective Wavelength 126 nm 13.5 nm 0.1 nm 12 pm 0.1 pm

Exposing Particles Photons Photons Photons Electrons Ions (Photons)

Type of Optics Reflective Reflective Reflective Electromagnetic Electromagnetic

None or
Mask Type Reflective Reflective Transmission None
Transmission
Resolution Limit 100 nm 3~45 nm 1~30 nm 10~22 nm 2 nm

Typical D.O.F. 500 nm 1100 nm Large Large (Scattering) Large (Scattering)

Refined from : Jack Kilby and Robert Noyce, Introduction to Silicon Wafer Processing

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13.3 WET CHEMICAL ETCHING

ETCHING
 (1) CHEMICAL ETCHING; (2) PHYSICAL ETCHING
 (1) WET ETCHING; (2) DRY ETCHING

Etch Parameter Terminology

(a) WIW: within the wafer ; (b) WTW: wafer to wafer

• Etch Rate = Dd / Dt

• Etch Uniformity (Someone prefers to call it Non-uniformity)

Standard Deviation Non-uniformity
Etch rate uniformity % = the spread of the etch rates using standard deviations
Max-Min Uniformity
Etch rate uniformity % = (maximum etch rate - minimum etch rate) X100%
2 x average values
Refine eq. (8)
• Selectivity = Etch Rate of Material 1 / Etch Rate of Material 2

• Aspect Ratio = Etch Depth : Etch Opening Diameter or Width

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13.3 WET CHEMICAL ETCHING

Etching System Performance：

https://corial.plasmatherm.com/en/blog/etch-performance-9-factors-to-
consider

1. Etch Rate： the measurable quantity of how fast material is

removed from the surface of a wafer
2. Uniformity： measure of consistency across a wafer
3. Flexibility： variety of capabilities of an etch system.
4. Profile： profile or slope of the feature
5. Selectivity： ratio between two etch rates
6. Substrate Temperature： temperature affects the results.
7. Morphology： the microscale roughness of a surface.
8. Damage： system generates particles, subtle effects, and …
9. Repeatability： run-to-run measurements.

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13.3 WET CHEMICAL ETCHING

EXAMPLE 3
Calculate the Al average etch rate and etch rate Max-Min uniformity on a 300
mm diameter silicon wafer, assuming the etch rates at the center, left, right,
top, and bottom of the wafer are 750, 812, 765, 743, and 798 nm/min,
respectively.

Al average etch rate = (750 + 812 + 765 + 743 + 798) ÷ 5 = 773.6 nm/min.

Max-Min uniformity = (812 – 743) ÷ (2 X 773.6) × 100% = 4.5 %.

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13.3.1 Silicon Etching

Etchant：a mixture of nitric acid (HNO3)
and hydrofluoric acid (HF) in water or
acetic acid (CH3COOH)

Si + 4HNO3 → SiO2 + 2H2O + 4NO2 (9)

SiO2+ 6HF → H2SiF6 +2H2O (10)

Orientation-dependent etching
 Anisotropic etching
Si {100} and {110} crystal planes can
be rapidly etched than the stable {111},
they have different activation energies

Wb = W0 – 2l . cot 54.7°

Fig. 18 Orientation-dependent etching. (a) Through window patterns on <100>-

oriented silicon; (b) through window patterns on <110>-oriented silicon.18
. 30

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13.3.~ Etchants for Insulators and Conductors

Etching Polysilicon : It is similar to etching single-crystal silicon. However, the etch rate is considerably
larger because of grain boundaries. The etch solution is usually modified to ensure that it does not attack the
underlying gate oxide. Dopant concentrations and temperature may affect the etch rate of polysilicon.

Etching Gallium Arsenide : The surface activities of the (111)-Ga and (111)-As faces are very different. Most
etches give a polished As-surface, but a crystallographic defected Ga-surface (and slow Ga etch rate).
The most commonly used etchants are the H2SO4-H2O2-H2O and H3PO4-H2O2-H2O systems.
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13.4 DRY ETCHING

Fig. 19 : Pattern Transfer.20
(a) Resist pattern formation.
Comparison of wet and dry etching
(b) wet chemical etching
(c) dry etching for pattern transfer.20
(a) Resist pattern
The degree of anisotropy
l Rt R
Af  1   1 l  1 l
hf Rv t Rv
Af : the degree of anisotropy
hf : the thickness of the layer material
(b) Undercutting l : the lateral distance etched
underneath the resist mask
t : the etch time
Rl : lateral etch rates
Rυ : vertical etch rates

For isotropic etching, Rl = Rυ and Af = 0.

(c) High-fidelity transfer
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13.4.1 Plasma Fundamentals

(-) (+) Sheath and Etching
1. Central plasma chamber is neutrally
Capacitively Plasma is a fully or
partially ionized gas is charged.
coupled to an
initiated by free electrons. 2. Electrons accumulate more during
RF generator
positive cycles, enhancing positive current.
The free electrons 3. Electron flow charges cathode but
RF oscillate and gain kinetic capacitor blocks current.
AC energy from the RF 4. Cathode bias becomes more negative,
electric field and thermal
preventing electron inflow.
excitation. They collide
with gas molecules. 5. Bias depends on applied voltage's
13.56 MHz
attributes.
non-interference
with radio- 6. Cathode bias leads to compensating
transmitted positive plasma potential.
signals with 7. Voltage gradients create vital sheaths with
optimized strong electric fields.
impedance for 8. Sheaths are thin, affect ion directionality.
energy transfer. 9. Anisotropic etching relies on directed ion
VDC bombardment.
DC bias 10.Cathode's strong field enables robust
(self-bias voltage) The ionization rate is on etching, anode's weaker field leads to
the order of 10-4 to 10-6. milder etching.
Fig. 20 Schematic system and approximate time-averaged potential distribution of a capacitively coupled RF plasma system.
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13.4.2 Surface Chemistry

Mechanisms

1. Etching plasma lacks thermal equilibrium, leading to high electron

temperatures (20,000~100,000 K), higher than ions (up to 2,000 K) and
neutrals (< 1,000 K).
2. Energetic electrons create reactive radicals and ions, enhancing unique
chemical reactions.
3. Reactive radicals and ions boosting surface processes and plasma chemistry.
4. Key surface processes include reactive ion etching (RIE), physical etching
(sputtering), chemical etching, and polymer deposition.

Diverse process demands: precise profiles, material selectivity, uniformity over

large substrates, and integration with adjacent processes.

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13.4.2 Surface Chemistry

Key Surface Process Issues:
(1) Physical Sputtering : Physical sputtering involves the energetic ion or neutral
bombardments of target without selectivity.

(2) Reactive Ion Etching : RIE involves ions and reactive radicals hitting the
surface together. The radicals cause anisotropic etching. RIE is like sputtering
but more selective due to its partial chemical nature from radicals.

(3) Chemical Etching : Chemical etching is usually isotropic depends on etchants.

In CMOS device fabrication, isotropic chemical etching isn't ideal for submicron
features. Thus, processes are adjusted to reduce chemical etching.
Si (solid) + 4F → SiF4 (gas). An example of chemical plasma Si etching

(4) Polymer Deposition : Polymer may buildup to sidewall form linked plasmas
radicals from fluorine-containing gases.

(5) Substrate Temperature : Substrate temperature is crucial; higher temperature

speeds up chemical etching. Temperature change manages anisotropic/isotropic
etching balance, affecting profile and selectivity.
35

13.4.2 Surface Chemistry

Positive Profile

Fig. 21 The sequential formation, from left to right, of an etching feature

profile in the presence of re-deposition. The etching of horizontal surfaces
and re-deposition onto vertical surfaces are assumed to occur sequentially.
Etching >> Deposition >> Etching >> Deposition >> …Scallop Sidewall

More Deposition
Deposition >> Positive Profile

More Etching
>> Negative Profile

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Two Groups of Dry Etchers

There are basically two groups of dry etchers based on how the plasma is produced:
(1) the capacitively coupled etchers; (2) the inductively coupled etchers.

Fig. 22 Plasma etcher with larger

area for the grounded electrode
and coupled capacitor.
The glow region Fig. 25 Inductively coupled
plasma etcher.
The sheaths (dark region)
A reactor for dry etching typically contains a vacuum chamber, pump system, power
supply generators, pressure sensors, gas flow control units, and end-point detector.
37

13.4.3 Capacitively Coupled Plasmas Etchers

Etchant gases Typical gas pressures A wafer can be placed on

are injected (~ 50 to 500 mTorr). the grounded (powered
cathode) electrode

Fig. 22 Plasma etcher with larger area Fig. 23 Schematic of a triode reactive ion
for the grounded electrode and etch reactor with two different radio-
coupled capacitor. frequency power sources.
• Each reactor uses a particular combination of
pressure, electrode configuration and type, and
source frequency to control the two primary etch
mechanisms—chemical and physical modes.
• Energies of bombarding ions are about ten times
higher in the reactive ion etch mode bombardment
due to higher self-bias VDC. The scattering of gas
prevents their use for fabrication of extremely small
features.
Fig. 24 Schematic of a typical barrel reactor.
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13.4.3 Capacitively Coupled Plasmas Etchers

• The glow region of the plasma is a good electrical conductor.
• The dark spaces in plasma are areas of limited conductivity and can be
modeled as capacitances.
• C = A/d, A is the electrode area; d is the sheath thickness of the dark space.
VC/VA = CA/CC = (AA/dA)/( AC/dC) (14)
 VC (CC) and VA (CA) are the voltage drops (capacitances) over the
sheath thicknesses of the dark space on the cathode and anode
 AC, AA are the areas of the cathode and anode.

• The current between two electrodes is dominated by space-charge-limited

current in a capacitively coupled plasma system.
• The space-charge-limited current (Section 2.7, eq.(91)) of positive ions must
be equal on both anode and cathode, i.e.
VC3/2 / dC2 = VA3/2 / dA2 (15)
Therefore,
VC /VA = (AA /AC)4 (16)
 Increasing the area of the grounded electrode raises the sheath voltage
at the powered electrode. Higher voltage enhances the etching rate but
lowers selectivity due to intense sputtering.
 Selectivity can be improved with the appropriate choice of etch chemistry.
39

13.4.4 Inductively Coupled Plasma Etchers

Similar to an ICP etcher :
• Resonant wave-plasma
interaction at low pressure
(<10mTorr).
• High degrees of gas
dissociation (ionization)
• Carefully designed the
magnetic field profile
• High-density uniform
plasma (HDP)

Fig. 26 Schematic of an electron cyclotron resonance reactor. 21

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13.4.4 Inductively Coupled Plasma Etchers

Charged species or ultraviolet radiation
in plasma may cause electrical
damage to circuits.

Ions can be accelerated and neutralized

before they bombard the substrate,
resulting in energetic neutral-species
bombardment on the substrate.

Fig. 27 Neutral beam plasma etcher.. These etchers are also useful for high-
rate removal of blanket films that do not
have any patterned features.
The major limitation is from their broad
angular distribution of neutral etchants.
41

13.4.4 Inductively Coupled Plasma Etchers

Multilayer metal interconnect Semiconductor wafers are
(TiW/AlCu/TiW) etching process processed in clean rooms to
with clustered tools. minimize exposure to ambient
particulate contamination.

The clustered plasma

processing tools can also
increase throughput and yield.

Fig. 28 Cluster reactive ion etch tool for multilayer metal (TiW/AlCu/TiW)
interconnect etching.2
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13.4.5 Plasma Diagnostics and End-Point

Using observed spectral peaks from optical emission spectroscopy (OES) ,
it is usually possible to determine the presence of neutral and ionic species
by correlating these emissions with previously determined spectral series.

Silicide etch / polysilicon etch

Fig. 29 The relative reflectance of the etching surface of a composite

silicide/poly-Si layer. The end point of the etch is indicated by cessation of
the reflective oscillation.
43

13.4.5 Plasma Diagnostics and End-Point

Figure 29 shows a typical signal from a silicide/polycrystalline Si gate etch.

The period of the oscillation is related to the change in film thickness by

2d =  / n , d =  / (2n) , D d = D  / (2n) (17)

where Δd is the change in film thickness for one period of reflected light, λ
is the wavelength of the laser light, and n is the refractive index of the
etching layer.

Moreno, Maria. (2016). Characterization and optimization of high density plasma

etching processes for advanced memories application. (PDF)
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13.4.6 Etching Chemistries and Applications

TABLE 2 ETCH CHEMISTRIES OF DIFFERENT ETCH PROCESSES
Material being etched Etching chemistry
Silicon Trench Etching
Deep Si trench HBr/NF3/O2/SF6
Shallow Si trench HBr/Cl2/O2
Polysilicon and Polycide Gate Etching
Poly Si HBr/Cl2/O2, HBr/O2, BCl3/Cl2, SF6
WSi2, TiSi2, CoSi2 CCl2F2/NF3, CF4/Cl2, Cl2/N2/C2F6
Interconnect Metal Etching
Al BCl3/Cl2, SiCl4/Cl2, HBr/Cl2
AlSiCu BCl3/Cl2/N2
W SF6 only NF3/Cl2
TiW SF6 only
Dielectric Etching
SiO2 CF4/CHF3/Ar, C2F6, C3F8, C4F8/CO,C5F8, CH2F2
Si3N4 CHF3/O2, CH2F2, CH2CHF2, SF6/He
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13.4.6 Etching Chemistries and Applications

Step 1: 90% of the W is etched at a high etch rate.
Step 2: The etch rate is reduced to remove the
remaining W with an etchant with a high
Low-pressure CVD (LPCVD) W-to-TiN selectivity.
tungsten (W) has excellent
deposition conformability.

Fig. 30 Formation of tungsten plug in a contact hole by depositing blanket

low-pressure chemical-vapor deposition W and then using reaction ion
etching etchback.
.
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SUMMARY
Advantages Limitations
Wet chemical etching • High throughput • Undercut
(blanket etching) • Loss of resolution in
• Cost effective the etched pattern.

Dry etching • High-fidelity pattern • Low throughput (RIE)

transfer • Plasma-induced
damage.
• Costy

Advancing in Future Directions :

• High etch selectivity,
• Better critical-dimension control, • New gas chemistries
• High aspect-ratio–dependent etching, • Low-pressure, high-
• Low plasma-induced damage, and density, containable
• Excellent etch uniformity. plasma reactors

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