ISSCC 2021 Short Course

Introduction to PLLs:
Phase Noise, Modeling, and
Key Wireless Design Considerations

Behzad Razavi
University of California, Los Angeles

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 1
key wireless design considerations
Outline
• PLL Fundamentals (20 minutes)
• PLL Imperfections (20 minutes)
• Phase Noise in PLLs (20 minutes)
• PLL Modeling (15 minutes)
• Wireless Design Considerations (15 minutes)
Not Covered:
• Digital PLLs
• Subsampling PLLs
• Design of Building Blocks
• RF Synthesis
Most equations are given without proof.
Introduction to PLLs: phase noise, modeling, and
February 14, 2021 2
key wireless design considerations
 They don’t make ‘em like they used to …

[Mijuskovic et al, JSSC, March ‘94]

[Lee et al, ISSCC’20]

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 3
key wireless design considerations
Phase Detector

Example

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 4
key wireless design considerations
Voltage-Controlled Oscillator

φex

 VCO operates as an ideal integrator:

 Output phase cannot be changed instantaneously.

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 5
key wireless design considerations
Problem of Phase Alignment

VCK VVCO

Loop is “locked” if phase difference is constant

 fout = fin.
Introduction to PLLs: phase noise, modeling, and
February 14, 2021 6
key wireless design considerations
Simple (Type-I) PLL Example

Type-I PLL:
 Limited capture range  Need a

phase/frequency detector (PFD)

Finite steady-state phase error, Δφ1  Add one
more integrator to obtain infinite loop gain.

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 7
key wireless design considerations
PFD Implementation

Tres

 Reset pulses are ~ 5 gate delays

wide.

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 8
key wireless design considerations
Forcing Phase Error to Zero
 Add one more integrator in the loop.

Charge
Pump

Vcont

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 9
key wireless design considerations
Loop Dynamics
• Voltage-Domain Analogy:

• PLL:

• Need to construct a linear phase-domain model for PLL.

Introduction to PLLs: phase noise, modeling, and
February 14, 2021 10
key wireless design considerations
First Attempt to Close the Loop

• Two ideal integrators make the loop unstable.

Introduction to PLLs: phase noise, modeling, and
February 14, 2021 11
key wireless design considerations
 Type II (Charge-Pump) PLL
• Add a zero to stabilize the loop:

fin
fout

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 12
key wireless design considerations
Open-Loop and Closed-Loop Responses
Open-Loop Response Closed-Loop Response

“Loop BW” • Minimum BW for stability: fin/2

[Homayoun, TCAS I, June 16]
• In practice, BW < fin/10 to
- Reduce spur levels
- Reduce reference phase noise
contribution

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 13
key wireless design considerations
 Addition of Second Cap to Loop Filter
• Even in locked condition, charge pump
injects unwanted charge, creating ripple.
• Add a second cap to absorb the charge:
Third Pole

• A well-designed loop locks in less than 100TREF.

Introduction to PLLs: phase noise, modeling, and
February 14, 2021 14
key wireless design considerations
 Some PFD/CP Imperfections

• Skew between Up and Down Pulses

• Charge Sharing
Symptoms
• Charge Injection and Clock Feedthrough
• Mismatch between Up and Down Currents
• Channel-Length Modulation

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 15
key wireless design considerations
 Up and Down Current Mismatch

 The net current must have a zero average:

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 16
key wireless design considerations
Quantifying Channel-Length Modulation

 We wish to keep ΔI1,2 / Ip < 10%.

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 17
key wireless design considerations
An Example

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 18
key wireless design considerations
Reduction of Channel-Length Mod. (I)

[Lee, Elec. Let., Nov. 00]

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 19
key wireless design considerations
Reduction of Random & Deterministic Mismatches

[Wakayama, US Patent 7,057,465 B2]

 Op amp must operate with wide input CM range.

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 20
key wireless design considerations
Phase Noise in PLLs
2 Minutes of Phase Noise
• Random aberrations in zero crossings:

• Or random fluctuations in period (i.e., frequency):

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 22
key wireless design considerations
Getting Comfortable with Phase Noise and Frequency Noise

Delay Line

• White voltage noise translates to

white phase noise.

Oscillator

• White voltage noise translates to

white frequency noise.

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 23
key wireless design considerations
Sources of Phase Noise

Crystal Osc.
&
PFD

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 24
key wireless design considerations
 Three Loop Bandwidths (I)
Closed-Loop
Input/Output Response:

Open-Loop Response
(Loop Transmission):

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 25
key wireless design considerations
 Three Loop Bandwidths (II)
From VCO Phase Noise to Output:

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 26
key wireless design considerations
Charge Pump Thermal Noise

• Switching causes complete aliasing

of white noise  spectral density
scaled according to duty cycle:
(within
loop BW)

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 27
key wireless design considerations
Charge Pump Flicker Noise
• Switching replicates flicker noise spectrum:

• If aliasing is neglected:

(within loop BW)

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 28
key wireless design considerations
PLL Modeling
General Considerations

Example: fout = 2.4 GHz, fREF = 50 MHz 

time step ~ 20 ps, lock time ~ 2 us
Objectives:
• Speed up simulation and optimization
• Maintain reasonable accuracy
• Examine loop dynamics, frequency
response, spurs, and phase noise
- Need to keep PFD/CP at transistor
level
- Need to include VCO phase noise

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 30
key wireless design considerations
Speeding up Sims
• Avoid signal sources with sharp transitions:

• Avoid transistor-level dividers:

VCO

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 31
key wireless design considerations
PLL Model

Cadence Verilog-A VCO

• Can obtain loop settling time and

spurs.

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 32
key wireless design considerations
PLL Transfer Function

• Modulate the input phase

with white noise:

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 33
key wireless design considerations
Example
• Select input phase noise much higher than PLL intrinsic noise.

C1 = 9.3 pF

pss/pnoise sim
takes < 1 minute

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 34
key wireless design considerations
Modeling VCO Phase Noise

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 35
key wireless design considerations
 Basic PLL Design Procedure
• Set the damping factor to 1:

• Set the “loop bandwidth” to about one-tenth of ref

freq:

• Select a charge pump current in the

range of 100 uA to 1 mA.
• Find R1 and C1. • Now check for:
• Select C2 ~ 0.2 C1. - Settling behavior (transient analysis)
- Input-output response (pss/pnoise)
- Peaking near the edge of band (pss/pnoise)
- CP phase noise contribution (pss/pnoise)
- Reference phase noise contribution (pss/pnoise)

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 36
key wireless design considerations
Key Wireless Design Issues
Role of Synthesizers

• Channel Spacing
• Frequency Accuracy
• Phase Noise
• Sidebands (Spurs)
• Lock Time
• Power Dissipation
• Reference Freq.

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 38
key wireless design considerations
 Effect of Phase Noise on TX
Interference with Other Users: Ideal Case Actual Case

Corruption of Signal:

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 39
key wireless design considerations
Effect of Phase Noise on RX
Reciprocal Mixing:
Ideal Case Actual Case

• The signal constellation is also corrupted.

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 40
key wireless design considerations
Lock Time

• Causes spillage of TX output power to other channels.

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 41
key wireless design considerations
Sidebands (Spurs)

• Manifests itself in blocking tests and adjacent

channel tests.
• Trades with settling time.
Introduction to PLLs: phase noise, modeling, and
February 14, 2021 42
key wireless design considerations
Basic Integer-N Synthesizer

• Output frequency step = reference frequency

 Can’t operate with arbitrary crystal frequencies

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 43
key wireless design considerations
New Trends
• High-order modulation schemes, e.g., 4096QAM,
require sub-100-fs jitters.
 All sources of phase noise become critical.
• Crystal oscillator phase noise plays a central role:
e.g., 50-MHz crystal with -165 dBc/Hz  ~70-fs jitter in
5 MHz
 Need to find optimum loop BW.
• Typical loop bandwidths are far below fREF/10.
 Good: spurs are low; ΔΣ noise is suppressed
 Bad: - VCO phase noise suppressed less
- VCO supply noise suppressed less
- Large loop filter caps
- Longer loop settling

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 44
key wireless design considerations
Optimum Bandwidth (Neglecting Flicker Noise)
AreaREF

AreaVCO = 4S1f2
f1~ f2
S1

• One-Pole PLL Approximation: AreaREF =

• Optimum BW:

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 45
key wireless design considerations
References [1]
 M. Terrovitis et al., “A 3.2 to 4 GHz 0.25 um CMOS frequency synthesizer for IEEE 802.11a/b/g
WLAN,” ISSCC Dig. Tech. Papers, pp. 98-99, Feb. 2004.
 M. Wakyama, “Low offset and low glitch energy charge pump and method of operating same,”
US Patent 7057465, April 2005.
 A. Homayoun and B. Razavi, “Relation between delay line phase noise and ring oscillator phase
noise,” IEEE J. Solid-State Circuits, vol. 49, pp. 384-391, Feb. 2014.
 A. Homayoun and B. Razavi, “Analysis of phase noise in phase/frequency detectors,” IEEE Trans.
Circuits and Systems - Part I, vol. 60, pp. 529-539, Mar. 2013.
 A. Hajimiri, and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J.
Solid-State Circuits, vol. 33, pp. 179-194, Feb. 1998.
 P. Andreani and A. Fard, “More on the 1/f phase noise performance of CMOS differential-pair LC-
tank oscillators,” IEEE J. Solid-State Circuits, vol. 41, pp. 2703-2712, Dec. 2006.
 A. Mazzanti and P. Andreani, “Class-C harmonic CMOS VCOs, with a general result on phase
noise,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2716-2729, Dec. 2008.
 B. Razavi, Design of CMOS Phase-Locked Loops, Cambridge University Press, 2020.

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 46
key wireless design considerations
References [2]
 A. Homayoun and B. Razavi, ”On the stability of charge-pump phase-locked loops,” IEEE Trans. Ciruits and
Systems - Part I, vol.63,pp. 626-635, June 2016.
 S. E. Meninger and M. H. Perrott, “A 1-MHz bandwidth 3.6-GHz 0.18-m CMOS fractional-N synthesizer utilizing
a hybrid PFD/DAC structure for reduced broadband phase noise,” IEEE J. Solid-State Circuits, vol. 41, pp. 966-
981, April 2006.
 J. Lin et al., “A PVT-tolerant 0.18 MHz to 600 MHz self-calibrated digital PLL in 90-nm CMOS process,” ISSCC
Dig. Tech. Papers, pp. 488-489, Feb. 2004.
 A. V. Rylyakov et al., “A wide power supply range (0.5 V to 1.3 V) wide tuning range (500 MHz to 8 GHz) all-
static CMOS AD PLL in 65 nm SOI,” ISSCC Dig. Tech. Papers, pp. 172-173, Feb. 2007.
 D. Miyashita et al., “A -104dBc/Hz in-band phase noise 3-GHz all-digital PLL with phase interpolation based
hierarchical time-to-digital convertor,” Dig. Symp. VLSI Circuits, pp. 112-113, June 2011.
 T. A. D. Riley, M. A. Copeland, and T. A. Kwasniewski, “Delta-Sigma modulation in fractional-N frequency
synthesis,” IEEE J. Solid-State Circuits, vol. 28, pp. 553-559, May 1993.
 H. Huh et al, “A CMOS dual-band fractional-N synthesizer with reference doubler and compensated charge
Pump,” ISSCC Dig. Tech. Papers, pp. 186-187, Feb. 2004.
 S. E. Meninger and M. H. Perrott, “A 1-MHz bandwidth 3.6-GHz 0.18-m CMOS fractional-N synthesizer utilizing
a hybrid PFD/DAC structure for reduced broadband phase noise,” IEEE J. Solid-State Circuits, vol. 41, pp.966-
981, April 2006.
 J. Yuan and C. Svensson, “High-speed CMOS circuit technique,” IEEE J. Solid-State Circuits, vol. 24, pp. 62-70,
Feb. 1989.

Introduction to PLLs: phase noise, modeling, and

February 14, 2021 47
key wireless design considerations