Numbering Scheme for Logic ICs

Experiment No.1
STUDY OF LOGIC GATES

AIM:
To study about logic gates and verify their truth tables.

COMPONENTS AND EQUIPMENTS REQUIRED

ICs 7408, 7432, 7404,7400 ,7402,7486 and digital IC trainer kit.

AND GATE:

The AND gate performs a logical multiplication commonly known as AND function. The output
is high when both the inputs are high. The output is low level when any one of the inputs is low.

SYMBOL TRUTH TABLE PIN DIAGRAM

A A B Y
Y
0 0 0

0 1 0
B
1 0 0

1 1 1
7408

OR GATE:

The OR gate performs a logical addition commonly known as OR function. The output is high
when any one of the inputs is high. The output is low level when both the inputs are low.
 SYMBOL TRUTH TABLE PIN DIAGRAM

A A B Y
Y
0 0 0

B 0 1 1

1 0 1

1 1 1
7432

NOT GATE:

The NOT gate is called an inverter. The output is high when the input is low. The output
is low when the input is high.

SYMBOL TRUTH TABLE PIN DIAGRAM

A Y
A Y
0 1
1 0

7404

NAND GATE:

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low and
any one of the input is low .The output is low level when both inputs are high.
 SYMBOL TRUTH TABLE PIN DIAGRAM

A A B Y
Y
0 0 1

B 0 1 1
1 0 1
1 1 0
7400

NOR GATE:

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.

SYMBOL TRUTH TABLE PIN DIAGRAM

A A B Y
Y
0 0 1

B 0 1 0

1 0 0

1 1 0
7402
X-OR GATE:

The output is high when any one of the inputs is high. The output is low when both the inputs are
low and both the inputs are high. When number of inputs for an ex-or gate exceeds two the
operation can be described as follows: “When the input contains odd number of 1s then the
output becomes high, when the number of 1s in the input contains even number of 1s or zero 1s
then the output becomes low”.

SYMBOL TRUTH TABLE PIN DIAGRAM

A
Y A B Y

0 0 0
B
0 1 1

1 0 1

1 1 0

RESULT:

Studied different logic gates and verified their truth tables.

 Experiment No. 2
REALIZATION OF LOGIC GATES USING UNIVERSAL GATES

AIM
To realize the standard gates using universal gates and verify their truth tables.

COMPONENTS AND EQUIPMENTS REQUIRED

ICs 7400, 7402 and digital IC trainer kit.

1) NOT GATE

TRUTH TABLE

A Y=

0 1

1 0

1.1) USING NAND GATE

A Y=A

1.2) USING NOR GATE

A Y=A
2) AND GATE

TRUTH TABLE

Inputs Output

A B Y=A.B

0 0 0

0 1 0

1 0 0

1 1 1

2.1) AND GATE USING NAND GATE

A
Y=A.B

2.2) USING NOR GATE

Y=A.B

B
3) OR GATE

TRUTH TABLE

Inputs Outputs

A B Y=A+B

0 0 0

0 1 1

1 0 1

1 1 1

3.1) OR GATE USING NAND GATE

A+B

3.2) OR GATE USING NOR GATE

A
Y=A+B

B
4) XOR GATE

TRUTH TABLE

Inputs Outputs

A B Y

0 0 0

0 1 1

1 0 1

1 1 0

4.1) USING NAND GATE

B
 4.2) USING NOR GATE

RESULT:
Realized the standard gates using universal gates and verified their truth tables.
 Experiment No. 3
REALIZATION OF BOOLEAN EXPRESSION

AIM
To realize the given Boolean expression using various approaches and verify the truth table.

Realize the Boolean expression:

1) In canonical POS form.

2) In equivalent canonical SOP form.

COMPONENTS AND EQUIPMENTS REQUIRED

ICs 7408, 7404, 7432 and digital IC trainer kit.

1) In SOP form

TRUTH TABLE

Inputs Outputs

A B Y

0 0 1

0 1 1

1 0 1

1 1 0

In minterms:
 Circuit:

Canonical form:

2) In equivalent POS form

In minterms:

TRUTH TABLE

Inputs Outputs

A B Y

0 0 1

0 1 1

1 0 1

1 1 0
 Circuit:

Canonical form:

RESULT:
Realized the given Boolean expression using various approaches of Sum of Products (SOP) and product of
Sums (POS) and verified the truth table.
 Experiment No. 4
ADDERS AND SUBTRACTORS

AIM
To implement the half adder, full adder, half subtractor and full subtractor circuits using basic
gates, universal gates and verify their truth tables.

COMPONENTS AND EQUIPMENTS REQUIRED

IC-7486, IC-7432, IC-7400, IC-7404, IC-7402, IC-7408, IC Trainer kit.

THEORY

The simplest binary adder is called a half adder. Half adder has two inputs bits and two
output bits. One output bit is the sum and the other is carry. There are represented by S and C
respectively in the logic symbol.

A half adder has no provision to add a carry from the lower order bits when binary
numbers are added. When two input bits and a carry are to be added, the number of input bits
becomes three and the input combinations increases to eight. For this a full adder is used. Like
half adder it also as a sum bit and carry bit. The new carry generated is represented by C and
carry generated from the previous addition is represented by Cn-1.

A logic circuit for the binary subtraction between two single bit binary numbers is known
as half subtractor. It consists of two input bits and two output bits. One output bit is borrow and
other output bit is difference. They are represented by B′ and D respectively in logic symbol.
From the truth table it is clear that the difference output is zero if X=Y and 1 if X ≠ Y.

1) HALF ADDER

A B S C

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1
K-MAP FOR HALF ADDER

0 1 0 0

1 0 0 1

C=A.B

HALF ADDER USING BASIC GATES

HALF ADDER USING NAND GATES

 2) FULL ADDER

The borrow output is 1 whenever X<Y. If X<Y then the subtraction is done by borrowing 1 from
next higher order bit.

A logic circuit that can subtract three bits at a time is known as full subtractor. The
circuit has three inputs and two outputs. It handles only two bits at time and can be used for the
largest significant column of the subtractor problem. A full subtractor can however take care of
higher order column. The output of the full subtractor represented by D and B′, which is
difference and borrow respectively.

TRUTH TABLE OF FULL ADDER

A B C S Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

K-MAP FOR FULL ADDER

0 1 0 1
i 1 0 1 0
n
 0 0 1 0

0 1 1 1

FULL ADDER USING BASIC GATES

FULL ADDER USING NAND GATES

SUM

CARRY
3) HALF SUBTRACTOR

TRUTH TABLE OF HALF SUBTRACTOR

A B D B′

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

K-MAP FOR HALF SUBTRACTOR

0 1 0 1

1 0 0 0

B’=

HALF SUBTRACTOR USING BASIC GATES

HALF SUBTRACTOR USING NAND GATES

4) FULL SUBTRACTOR

TRUTH TABLE OF FULL SUBTRACTOR

A B C D Bout

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1
K-MAP FOR FULL SUBTRACTOR

0 1 0 1

1 0 1 0

0 1 0 0

1 1 1 0

FULL SUBTACTOR USING BASIC GATES

 FULL SUBTRACTOR USING NAND GATES

RESULT

The half adder, full adder, half subtractor and full subtractor circuits are implemented using
basic gates and universal gates and their truth tables are verified.