DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

ACADEMIC YEAR 2023-24

REGULATION 2021

SUB CODE/NAME: EC3552 – VLSI AND CHIP DESIGN

YEAR/SEM: III/V

TWO MARKS

UNIT- III SEQUENTIAL LOGIC CIRCUITS AND CLOCKING

STRATEGIES
1. What are the classifications of CMOS circuit families?
• Static CMOS circuits.
• Dynamic CMOS circuits.
• Ratioed circuits.
• Pass-transistor circuits.
2. What are the characteristics of Static CMOS design?
A static CMOS circuit is a combination of two networks – the pull-up network
(PUN) and the pull-down network (PDN) in which at every point in time, each gate
output is connected to either VDD or VSS via a low resistance line.
3. List the important properties of Static CMOS design?
At any instant of time, the output of the gate is directly connected to VDD and
VSS. The function of the PUN is providing a connection between the output and
VDD.
The function of the PDN is provide a connection between the output and VSS .
Both PDN and PUN are constructed in mutually exclusive way such that one and
only\ one of the networks is conducting in steady state.
That is, the output node is always a low-impedance node in steady state.
4. What is Dynamic CMOS logic?
Dynamic circuits rely on the temporary storage of signal values on the capacitance of
high impedance node.
• Requires only N+2 transistors.
 • Takes a sequence of precharge and conditional evaluation phases to realizes
logic functions.
5. What are the properties of Dynamic logic?
• Logic function is implemented by pull-down network only.
• Full swing outputs (VOL= GND and VOH = VDD).
• Non-ratioed.
• Faster switching speeds.
• Needs a precharge clock.
6. What are the disadvantages of dynamic CMOS technology?
A fundamental difficulty with dynamic circuits is a loss of noise immunity and a
serious timing restriction on the inputs of the gate. Violate monotonicity during
evaluation phase.
7. What is CMOS Domino logic?
A static CMOS inverter placed between dynamic gates which eliminate the
monotonicity problem in dynamic circuits are called CMOS Domino logic.
8. What is called static and dynamic sequencing element?
A sequencing element with static storage employs some sort of feedback to retain
its output value indefinitely. A sequencing element with dynamic storage generally
maintains its value as charge on a capacitor that will leak away if not refreshed for a
long period of time.
9. What is clock skew?
In reality clocks have some uncertainty in their arrival times that can cut into the
time available for useful computation is called clock skew.
10. What are synchronizers?
Synchronizers are used to reduce metastability. The synchronizers ensure
synchronization between asynchronous input and synchronous system.
11. What is the difference between melay and moore state machines?
In the melay state machine we can calculate the next state and output both from
the input and state.But in the moore state machine we can calculate only next
state but not output from the input and the state and the output is issued according
to next state.
12. Define propagation delay and contamination delay?
Propagation delay (t pd):

The amount of time needed for a change in a logic input to result in a permanent
 change at an output, that is the combinational logic will not show any further output
changes in response to an input change alter time fod units
Contamination delay (tea):
The amount of time needed for a change in a logic input to result in an initial
change at an output, that is the combinational logic is guaranteed not to show any
output change in response to an input change before fed time units have passed.
13. Define Setup time and Hold time.
Setup time (t setup):
The amount of time before the clock edge that data input D must be stable the
rising clock edge arrives.

Hold time (t hold):

This indicates the amount of time after the clock edge arrives the data input D
must be held stable in order for FF to latch the correct value. Hold time is always
measured from the rising clock edge to a point after the clock edge.
14. Difference between latches and Flip-Flop.

S.No Latch Flip-Flo

. p
1. A Latch is Level-Sensitive. A FF is edge triggered.
2. A latch stores when the clock A FF stores when the clock rises
level is low and is transparent and
when the level is high. is mostly never transparent.
15. Define Pipelining.
Pipelining is a popular design technique often used to accelerate the operation of the
data path in digital processors.
The major advantages of pipelining are to reduce glitching in complex logic
networks and getting lower energy due to operand isolation.
16. How the limitations of a ROM-based realization are overcome in a PLA-based
realization?
In a ROM, the encoder part is only programmable and use of ROMs to realize
Boolean functions is wasteful in many situations because there is no cross-connect
for a significant part.
17. In what way the DRAMs differ from SRAMs?
Both SRAMs and DRAMs are volatile in nature, ie. Information is lost if power
line is removed. However SRAMs provide high switching speed, good noise margin
but require large chip area than DRAMs.
18. Explain the read and write operations for a one-transistor DRAM cell.
A significant improvement in the DRAM evolution was to realize 1-T DRAM
cell. One additional capacitor is explicitly fabricated for storage purpose. To store
'I', it is charged to store '0' it is discharged to '0' volt.
19. What is MTBF?
MTBF = (1/P(failure)) = ( Ti e(Ti=tsetup/ti)/Nto)
20. What do you meant by Max delay constraint and Min delay
constraint? Min delay constraint:
The path begins with the rising edge of the clock triggering F1. The data may
begin to change at Q1 after a clk-to-Q contamination delay.
However, it must not reach D2 until at least the hold after the clock edge, lest it
corrupt the contents of F2. Hence, we solve for minimum logic contamination delay:
tcd >= thold – tccq
Max delay constraint:
The path begins with the rising edge of the clock triggering F1. The data must
propagate to the output of the flip-flop Q1 and through the combinational logic to
D2, setting up at F2 before the next rising clock edge.
Under ideal conditions, the worst case propagation delays determine the
minimum clock period for this sequential circuitry
Tc >= tpcq + tpd + tsetup