DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
ACADEMIC YEAR 2023-24
REGULATION 2021
SUB CODE/NAME: EC3552 – VLSI AND CHIP DESIGN
YEAR/SEM: III/V
TWO MARKS
UNIT-II COMBINATIONAL LOGIC CIRCUITS
1. What are the general properties of Elmore delay model?
General property of Elmore delay model network has • Single input node • All the capacitors are between a node and ground • Network does not contain any resistive loop 2. What are the types of power dissipation? • Static power dissipation (due to leakage current when the circuit is idle). • Dynamic power dissipation (when the circuit is switching) and • Short-circuit power dissipation during switching of transistors. 3. What is static power dissipation? Power dissipation due to leakage current when the idle is called the static power dissipation. Static power due to • Sub - threshold conduction through OFF transistors • Tunneling current through gate oxide • Leakage through reverse biased diodes • Contention current in radioed circuits. 4. What is Dynamic power dissipation? Power dissipation is due to circuit switching to charge and discharge the output load capacitance at a particular node at operating frequency is called Dynamic power dissipation. The Dynamic power dissipation at a particular output node is given by Pd = CL Vdd^2 Fclk. a Where, CL = load capacitance; a = activity factor; Vdd =power supply; F clk= operating frequency.
5. What are the methods to reduce dynamic power dissipation?
• Reducing the product of capacitance and its switching frequency. • Eliminate logic switching that is not necessary for computation. • Reduce activity factor Reduce supply voltage 6. What are the methods to reduce static power dissipation? • By selecting multi threshold voltages on circuit paths with low-Vt transistors while leakage on other paths with high-Vt transistors. • By using two operating modes, active and standby for each function blocks. • By adjusting the body bias (i.e) adjusting FBB (Forward Body Bias) in active mode to increase performance and RBB (Reverse Body Bias) in standby mode to reduce leakage. • By using sleep transistors to isolate the supply from the block to achieve significant leakage power savings. 7. What is short circuit power dissipation? During switching, both NMOS and PMOS transistors will conduct simultaneously and provide a direct path between Vdd and the ground rail resulting in short circuit power dissipation. 8. Define design margin? The additional performance capability above required standard basic system parameters that may be specified by a system designer to compensate for uncertainties is called design margin. Design margin required as there are three sources of variation- two environmental and one manufacturing. 9. Write the applications of transmission gate? • Multiplexing element of path selector • A latch element An unlock switch • Act as a voltage controlled resistor connecting the input and output. 10. What is pass transistor? It is a MOS transistor, in which gate is driven by a control signal the source (out), the drain of the transistor is called constant or variable voltage potential (in) when the control signal is high, input is passed to the output and when the control signal is low, the output is floating topology such topology circuits is called pass transistor. 11. List the advantages of pass transistor? Pass transistor logic (PTL) circuits are often superior to standard CMOS circuits in terms of layout density, circuit delay and power consumption. They do not have path VDD to GND and do not dissipate standby power(static power dissipation). 12. What is transmission gate? The circuit constructed with the parallel connection of PMOS and NMOS with short ed drain and source terminals. The gate terminal uses two select signals s and sˉ, when s is high than the transmission gates pass the signal on the input. 13. Why low power has become an important issue in the present day VLSI circuit realization? Indeep submicron technology the power has become as one of the most important issue because of Increasing transistor count; the number of transistor is getting doubled in every 18 months based on moore's law 14. What are the various ways to reduce the delay time of a CMOS inverter? Various ways for reducing the delay time are given below: a)The width of the MOS transistor can be increased to reduce delay. this is known as gate sizing. b) The load capacitance can be reduced to reduce delay. This is achieved by using transistor of smaller and smaller dimension by feature generation technology. c)Delay can also be reduced by increasing the supply voltage Vdd and/or reducing the threshold voltage Vt of the MOS transistors 15. What is the basic operation of a 2- phase dynamic circuit? The operation of the circuit can be explained using precharge logic in which the out- put is precharged to HIGH level during Φ2 clock and the output is evaluated during Φ1 clock. 16. What makes dynamic CMOS circuits faster than static CMOS circuits? As MOS dynamic circuits require lesser number of transistor and capacitance is to be driven by it, this makes MOS dynamic circuits faster. 17. What is glitching power dissipation? Because of finite delay of the gates used to realize Boolean functions, different signals cannot reach the inputs of a gate simultaneously.This leads to spurious transition at the output before it settles down to its final value. 18. List various sources of leakage currents? Various source of leakage currents are listened below: I1= Reverse-bias p-n junction diode leakage current. I2= band-to-band tunneling current I3= Sub threshold leakage current I4= Gate oxide tunneling current I5= Gate current due to hot carrier junction 19. Compare and contrast clock gating versus power gating approaches. Clock gating minimizes dynamic power by stopping unnecessary transitions, but power gating minimizes leakage power by inserting a high Vt transistor in series with low Vt logic blocks. 20. What is Elmore delay model? It is an analytical method used to estimate the RC delay in a network. Elmore delay model estimates the delay of a RC ladder as the sum over each node in the ladder of the resistance Rn-1 between that node and a supply multiplied by the capacitor on the nodes.
