* 3. MC6802 MICROPROCESSOR MC6802 microprocessor nuns in IMI1z clock cycle. It has 64 Kbyte memory address capacity Using 16-bit addressing path (AQ-A15), The bit data path (DO-D7) is bidirectional and has three States, I has 72 instructions which are 1, 2 or 3 byte instructions. MC6802 microprocessor has 1 interrupt inputs. One of them 1s maskable (IRQ), the other one is unmaskable (NMI) and the last one is the reset (RESET). It also has 2 special instructions: SWI (software interrupt) and WAL (wait for interrupt). MC6802's pin numbers and theit connections are shown in Figure 3.1 vecsTa 6 aL fa Cy aa os os a? a 63 pppppe BERge: BREGRER 9: Si Figure 3.1 « MC6082 Microprocessor 3.1. REGISTERS MC6802 Microprocessor has three 16-bit registers and three 8-bit registers available for use by the programmer (Figure 3.2) + 2 Accumulators (Accumulator A, Accumulator B) + Program Counter (PC) + Stack Pointer (SP) + Index Register (X) + Condition Code Register (CCR). (Tj mre as ceo nore a CE orm rote3. MC6802 MICROPROCESSOR M6802 microprocessor runs im PMILz clack cycle Ithas 64 Kyte memory address cxpscity Path (AD-AIS) The Bebit data path (D0-D7) 1s budurectional ard ban Cire peetit addres Mie Inbas 72 instructions which are 1, 2.0" 3 byte imsnsctions MIC602 mictoprocessor has 3 interrupt puts. Ore of them 11 masbable (IRQ), the other one jeunmushable (NMI) and the list one tthe reset (RESET) It also hay 2 special amstructions SWI erupt) and WAL (wait for interrupt) MC6#02"s pin numbers and their connections ere shown in Figure J 3.1 REGISTERS MC6S02 Microprocesot has thre: IG-bit rewsters and thres §-bil 1 by the programner (Figure 3 ) 2 Accumalatars (Accumabstor A, Accumulator B) Program Counter (PC) Sut Poin (SP) Inder Reputer 0 Coalition Cade Reiter CCR) Ss—-- (== meeeAccumulators: The Microprocessor unit (MPU) contains two 8-bit accumulators (Accumulator A and Aceuulator By tht ae ned to bal operate nile resull produced by the anthmeve logic unit (ALU). Program Counter: Its a2-byte (16-bit) repister thal points tothe current program address Stack Pointer: It is 2-byte register that contains the address of the newt available location in an txtemal push-downpop-up stick. The contents of the stack poinir defines the top of the stack im RAM Index Reglster: It is 0 2-byte register thal 1s use to store data or 8 2-byte memory address for indexed memory addressing Condition Code Register: It shows the coniihons occurs us 4 result of un Anthmene Logie Unit operation (Figure 3.2) BuO camry from bit 7 of an arithmetic operation (C) Bil Overflow Mag (V) Bit2; Zero Mag (Z) Negative Nag (N) Interrupt Mask (I) Half earry from bit 3 of an arithnetie operation (11) Unused Unused ‘These bits of the Condition Code Register are used as testable conditions for the conditional branch instructions. Bit 4 of the CCR 1s the interrupt mask bit (1), The unused bits of the Condition Code Register (bit 6 and bit 7) are 1 Figure 3.3 shows the internal connections ofthe registers und the other units of the MCO802 Apap pee DB oe Be Oe mal block diagram of 6802 MPL3.2. ADDRESSING MODES ' MC6802 Microprocessor has 7 addressing modes that cun be used by the programmer 1, Accumulator 2. Immediate 3. Direct 4, Extended 5. Indexed 6, Implied (Inherent) 7. Relative MC6802 instructions may be used with one or more of these addressing modes, The instruction set and their addressing modes are given in Appendix A. Accumulator Addressing In accumulator addressing, cither accumulator A or accumulator B is specified. These are 1- byte instructions Ex: ABA edds the contetns of accumulators and stores the result in accumulator A Immediate Addressing in ummediate addressing operand is located immediately after the apeode inthe second be of the instruction in program memory (except LDS and LDX where the operand isu the second and third bytes ofthe instruction). These are 2-byte or 3-byte instructions. Ex: LDAA #2511 loads the number (25)x into accumulator A Direct Addressing In direct addressing, the address of the operand is contained in ths second byte of the instruction Direct addressing allows the usct to dieclly address the lowest 266 byes of the memory, irevocations O through 255. Enhanced execution times arc achieved By stonng data in these locations. These ure 2-byte instructions Ex: LDAA 2511 loads the contents of the memory adress (25)q into ‘accumulator A Extended Addressing in extended addressing the address contained inthe second byte of the stein’ used as the higher eight bits of the address of the operand. The thd bois of the instruction is used as the lower igh bils ofthe address forthe operand. This 1s an absolte address in the memory. These are 3-byte instructions. Ex: LDAA 100011 loads the contents ofthe memory address (1000)u into accumulator A.Indexed Addressing In indeved addressing, the address containa inthe second byte of the msiruction is aided (9 the ynden reper loweat eight Bits The carry is then add tothe higher on et Dis of hs index fepiser This resus then used to addres memory Te modificd address ts held in a temporany (Dress register so there is no change to Une salen register, These are 2-byte imsinuctions Ex: LDX #100011 LDAA 1OILX Inally, LDX.£1000H yaructon fads 100001 10 the andex register (X) using immediate addr Tuen LDAA 1011. ered addresung, loads the contents of memory address (10), =X = 1010, sto accumulator A instruction, using 174 Implied (Inherent) Addressing at Inthe implied addressing mode, the instruction gives the address mherently (Le, task pointer, tedex reputer, le} Inberent nsiructons are used when no operands need to be fetched, These are I~ byte insrustions jon is "nherent” Ex: INN increases the contents of the Index register by one, The address infor an the instruction itself INCA increases the contents of the accumulator A by one. DECR decreases the contents of the accumulator B by one. Relative Addressing mode 15 used with most of the branching instructions on the 6802 instruction 1s the opcode. The second byte of the instruction 1s falled the offuct The offset 1s interpreted as a signed 7-bit number. Ifthe MSB (most significant bit) Of the offset 1s O, the number 1s positive, which indicates a forward branch. Ifthe MSB of the offset 1s 1, the number 1s negative, which indicates a backward branch. Tlus allows the user to address data in a range of -126 to +129 bytes of the present instruction. These ure 2-byte instructions. Ea: PC HexLabel Instruction 0909 2004 BRA OFt Figure 3.4 shows the address calculation in the execution of the unconditional branch instruction (BRA) Program counter (PC) before the operation 1s 0009, The opcode of the “branch always” instruction (20,)) 15 Fetched f¢om location 000%, in program memory with the offset O4y (00000100,). Then the program counter 1s ancremented to the address uf the neat instruction (O0UBy) Jest before the actual opsrand fetch. The 6802 processor intemally adds the affyet (M,) Wo the current Cconlents of program counter (QUUB,.). The new address 1m the program counter after the “branch always" operation 1s GO0B.-04~UUDF, (0000 0000 0400 1111). The processor then jumps to this new faddress and fetches an instruction trom location ODF. Note that the offset's most significant bit (MSB) 150. This indicates a positive offset, which esuses a forward branch, on Cee em) Aer opera Frearin [eonemaen 1a) Pron m0) cr eel [eemmeneam) omer re Op case wom Com Ta) (ana [anoon } Cer Figure 3.4 - Relauve Addressing (branching forward)operations use relative addressing ‘io Figure 3.3 6 an coample for the use of branch imsructions In the fird brmnch NEXT), the address to be branched 1 109. AS relative addressing is exes, the offset 1B, - 1085 = Oy Whe commnn of PC wbich pois to the nex! imiruction. The offset i =rinen in the io the operand of the branch imsruction (20 Os). The second branch imaraction fs backward branch The displacement (offset) is calcined 10S. - 109 = = 0% coments of PC. As the offset a negative mumber, its 2's complement (F74) used Fn) Machine Code | Avsembly Language Program [Program te _—___} ORG Toor B60110 BEGIN LDAA 10H 103 2004 BRA NEXT 0109 570130 LAST TAA 10H o1os oF Swi BB 0120 ADDA —120H o10c 2077 BRA LAST 10s Figure 3.5 - A program wang branch tostuction5 6802 ASSEMBLY LANGUAGE PROGRAMMING I 4.1 Flags Te 6604 MPU uses six condition code bits of Nags (Figure 4.1) These Mags are grouped into an B-bit register called the Condition Cade Register (CCR) The branch instructions test these Mays to Actermune whether a branch wall be taken oF net the camry Mag (Cp is set to 1 whenever 8 by the most significant bit (MSD) of the sccumulator A sum ta accumulator sss the C flag 10 | ry (or ‘borrow") 1s yercrated out cr than the capacity of the S-hit The overflow flag (V) in the condition code register of the MPU indicates a 2's complement overflow. When dealing with signed numbers, the MSD (B,) of eccumulator(s) ts the sign bit. The femaining 7 bits are srtten an 2's complement form, These 7 bits can kald numbers between dscimal S127 ty -128 This 1s the range of signed numbers. Ifthe result of an aruhinctic operauon exceeds this range, an overflow occurs ann the overflow flag (V) is set fo | Figure 41 - Condition Code Repnter Consider adding the positive numbers 79» and Gy Decimal -79 is OIGOLIIN in 2's complement ard decimal ~64 1s 01600000 in 2°s complement. These 2's complement numbers are faded in Figure 4.2(a). Due t0 the carry from B, to Dz, the sign bat of the result changes to 1. (which indicates @ negative number), This is an error. Figure 4.2(b) shows ow the overflow fag is set an the microprocessor if {wo such numbers (in accumulator A and [) are added. The sum (10001111 40 this cuample) 1s deposited 1n accumulator A after add operation. The overflow flag (V) is set to 1. ndicating that the sum 1s lagger than ~127\« (sum=794,764 014301 Sun by Figure 42 (b) Figure 42+ Addition of pos end CCR (a) 2's complement addition show ing effect on sign bit (by Effcet on overflow fag Je numbers usin 2"s cormplem.TO neyative numbers 794, and) -6¢ Decimal -79 1s 10110001 im 2's 64 1s 11000000 in 2's complement. Since the most sigficant bits af both ‘are | they represent negative numbers between =I and -128 These 2's sare added in Figure 4.3(a) The result 6 101110001. Although the sign bit must ‘the addition results with a 0. This is an error because the sum exceeds the limit -128 ‘of the negative oumbers -79,, (10110001 in 2's complement) and ~64,, (11000000 nt) using the 6802 MPU 1s shown in Figure 4.3(b). The 2°s complement numbers are tored in accumulator A after the add operation. As (V) is set to 1, waning the user that the range of the (C) is also set to 1, indicating the carry out Noriaas-peastoe numer wer) = Rega mes even bt end ince Vygure 49.0) Fagure 4.49) 4.3 - Addinca of eepative number eusng 2's complement and CCR (2) 2s complement adsuon showy tbe eflcct on seg bt (b) Effect on overthom flag flag (Z) in the condition code register of the 6802 MPU is set to 1 wbemever the zero as a result of an operation or data (ranfer The zero ag recs & 0. ‘docs not contain a zero Ive flag (N) in the condition code register of the 6802 MPU indicates a negative } i the sign bit of the accumulator Ifthe resull of the lst anthmetic, ogacal or data 4 negative, the N fag ts set to 1 Ifthe resul is positive, the N flag is resets 0 Phe MSI of the accumulator Program adds (wo I-byte signed numbers in memory locanioms (0120p aad suddition, Af the overflow flay is set, then 10, ts stored into location (O00) sored into the same Location, one on LDAA Row «head the fina number ADDA iit $a them ‘bys voce s branch if overflow is set LDAA 20 “load (10) to accumlaor A STAA 40 More 0 io memory lcwton (O40), RA stor Jump 0 the ena ofthe pga 10 al programThe following program adds two 1-byte unsigned numbers in memory locations (0120) and 21) and stores the result, represented as a 2-byte number, into two consecutive memory locations 122), and (0123), After the addition operation accumulator A is stored at into address (0123), If 1s no carry, 0 1s stored into the location (0122), . Otherwise carry flag is stored into (0122)j, sng ADC 12H and STAA 122H instructions) ORG 10011 LDAA #0H Clear the most significant bit STAA 122H LDAA 120H load the first number ADDA 121H | add them STAA 123H_; store result BCS. CROCC ; branch if carry occurs LDAA #0H clear the most significant bit STAA 12H BRA STOP; jump to the end of the program OCC. LDAA *0H 4 Sct accumulator to 0 ADCA 122H__ , save carry bit in accumulator A STAA 122H Swi + end program , 12 Looping Loops help to repeat a section of a program for a number of times. There are three main types f loops 1. Repeating a program section indefinitely Output a on Bit 2 of Date Pon F gure 4.1 Infinite Loop. Above code outputs a1" on bit 2 ofa data pon indefinitely2. Repeating a program section until some predetermined condition becomes true (Figure 4.2) Figure 42 - Conditnonal loop The loop i repeated until a “I” appears at input bit 4 ofthe dats por 3. Repeating a program section for a predetermined number of passes oi Oats Port Figure 4. - Loop with loop count. Above code ourputs 0 "0" on bit 6 of a data pon $000 mes For looping in assembly language programs, branch instructions are needed. Jump and branch instructions of the 6802 microprocessor are shown in Table A.2. These nstructions transfer the control {rom one point to another inthe programVx tw the following proysam, accumulator A ts incremented by 2 dunng each ieraton of the oop Accumulator Hts used as a counter and decremented by 1 at each iteration, until st reduces to 0 onc 1001 LDAA wool «foal (0), to accumulator A Lpan malt $ load (10)y to accumulator B COMPARISON. UEQ stor + exit from the loop if accumulator B is 0 ADDA mnt + increment accumulator A by 2 been + decrement counter mA COMPARISON. ; branch to the beginning of the loop sror STAA 15011 Store the n SWI end program er in uccumulator A Far The index repister ty often used when the program must deal with data in the form of a table. “The mssembly language program listed in Tigure 4.8(a) adds numbers from tables of the augends and aildends in Figure 4.8(b) and places the sun in the table of sums ta the bottom of this memory map Vor instance, the program first adds Oly + O2,, placing the sum 03, in the "table of sums” to the memory location OOAOLL Then it repeats this process by adding 034, 1 04), placing the sum of 07 in the “tuble of sums” to the memory location O41 y, ete, The program in Figure 4,6(a) also has a feature thot supports the termination af the program Wf the sum of the numbers exceeds FF (using BCS i mn) Program memory ‘Aaaress | Contents (ne) | (hox) ‘oa00) Program Latal] Mremonie Operand]Commenta [ton [502200 | vaten en aren a OOH ; 7 Toor] —LOKA | Gort | Led auger tem frat atin in COT rencry (x eltet of 0M ) eta Data memory eccussator h 0020_[ Ot TODR | On | Aas isons rom eeeand oo ‘oo21_[__03 | Tabio of rsmmary(X+ eet 1001) 0022 [05] augends 22 occurs A 0023 [FF] (data) BES | STOP [WC tag = 8, ten trareh ters ‘ozs | 7 lo S10 (er greqyam i any arm restr wan FFA) o030_[_02 TONE | Stam acesmulsir Kea )a ‘0031 02 | Table ot vrata marry (% tt 0032 [05] addends ay (0033 S| (ata) Teron extra onto 0024 [60 Wane | Cernpara eden rier wn O02EH tae 02504 Wom eta ct 0040 eon wer) OH Table of (OOP |Z. tag = 0 wien tzarch tae to 0082 sums eres wastes ce LOOP O43) (¢ata) ra Craw 0084 Figure 4 ¥4a) - Assembly language program Fryure 4 (0) - Memory map The first instruction in the pro 0020, LDAA OO, accumulator A. Th Coon, «06, in listed in Figure 4.8(a) initiahzes the indes register to instruction loads a number from the table of augends in data memory first number to be loaded ts Oly from the memory location 0020, Gou,,) Note that the instruction in fine 2 hay a label LOOP and as the target of ackstard branch from the BNE LOOP operation towards the bottorn of the program. ADDA VON. stra faecumulatin A The addend’s m man Hine 3 ads the addcnd in data memory to the auyend which 19 19 mory Iucation 45.0080), (0020, + 10, = 0930)The fourth instruction (BCS STOP) checks whether the carry Nag is set to FAC = 1. this indicates that the sum exceeded FFy and the control 1s transferred to the end of the program While C=O, execution continues from line $ The STAA 20H.X instruction causes the sum in accumulator A to be stored in the “table of sums” In the first pass of the loop, the sum 1s stored into the memory location 0040,, (0020, * 20, ~ 00404) The INX instruction in line 6 increments the contents of the index register. The CPX n0025H instruction in ine 7 compares the current contents of the index register with 0025); to see whether the end of the lable of aurends 1s reached or not. The compare instruction is w subtract operation that ts used to set or reset the Z flag. The BNE LOOP instruction in line 8 checks Z flog. If Z flag ~ 0, the branch test 1s truc for the BNE instruction and the program branches back to the symbolic address LOOP in tine 2 When the index register reaches 0025y, the compare operation sets the Z flag to I. branch test of the BNE instruction becomes false, and the program continues with the next instruction in sequence. This 15 SWI instruction, which terminates the run,$. 6802 ASSEMBLY LANGUAGE PROGRAMMING IL 5.1 Increment and Decrement Instructions Increment (INC) and decrement (DEC) instructions allow the contents of a register or memory location to be increased or decreased by | respectively 8.2 Compare Instruction Consider the problem of testing the accumulator contents, e.g, whether it contains 37y oF not This can be achieved using substraction and BEQ instructions as shown in the following, program. SUBA #37H —; Subtracts the value 37y from the AccumularorA BEQ PASS: If the Zero Flag is set, branch to the label “PASS™ FAIL) LDAB HOIH | Zero flag is not sct so place 001 in AccumulatorB, BRA STOP. ; Returnsto start PASS. LDAD BFFH Zero flag is st so place FF, in Ace B 7 STOP: SWI Subtracting 37y from the accumulator causes the zero fla {0 be set if the sscumulator containes 374. Accumulator B is loaded with cither FF or 01y, to indicate an accumulator value of 374 for non-37y respectively. The difficulty with this technique is that it destroys the contents of the ‘accumulator. Since this is a very common problem in assembly’ language programming, 6802 provides ‘compare instructions (CMPA, CMPB, CBA, and CPX) which operate like subtraction but do not destroy the register contents. Compare instructions subtract the contents of the accumulator or index register from the destination and change the condition of Mags in CCR according to the result. Contents of the ‘accumulator (or index register) and destination are unaffected by the exccution of this instruction. ‘The above example program can be rewritten using CMPA instruction as follows, MPA #37H BEQ PASS FAIL: LDAB rOLH BRA sToP PASS. LDAB uFFH STOP: SWI ‘The CMPA instruction subtracts the value 37, from the Agcumulator but does not place the result in the accumulator. It only changes the flags of the CCR. Ifthe value 37), is equal to the contents of the Accumulator: Ifthe value 37) is greater than the contents of the Accumulator: Ifthe value 37) is less than the contents of the Accumulator: Carry Flag = 05.3 Logic and bit manipulation Instructions Logical Operators Logical instructions (AND, OR, Exclusive OR) can be wed to fest or change group of bits AND, OR and Exclusive OR are logical operators AND on OANDO-0 oono-0 OANDI=0 oont=1 OXOR1=1 TANDO-0 TORO=1 UXORO-1 VANDI = ToRT=1 1XOR1-0 Example: ono o101 ‘a100 Notice that any given bit in the result can only be 1 if both of the numbers have a 1 in that position. This property can be used 10 change specific bits in u register or memory location, In the fallowing example the contents of a ropister is 99y, To change the rightmost 4 bits to 0 and keep Whe other bits unchanged, the AND operation with FO, can be used, y= 10011001 FOq= 1110000 AND TOOTOOO The 6802 AND insiructions (ANDA, ANDB) can operste upon memory, register or immediate data ANDA OFFH :ANDs accumulator A with the contents of address location OOF Fy, ANDA 10HX = ANDs accumulator A with the contents of ‘address location (10) + offset of index register) ANDA #20H | ANDs accumulator A with the value 20, Other logical operations also use the same addressing modes: ANDA AND with accumulator A ANDB_ AND with aecumulator B ORAA OR with accumulator B ORAB OR with accumulator B EORA XOR with accumulator A EORB XOR with accumulator B Complement Instruction COMA, COMB und COM instructions complement the contents of the specified accumulator or u ‘memory location Complement instructions offer indexed and extended addressing modes. COMA or COMM insreton complement the content ofthe specified secular No othr sa bil oF register contents are affected. If accumulator B cont 3Ay (00111010), aft i b ins 3A aller the COM ‘Instruction ts executed, accumulator B contains C5y(11000101;). coComplement mstrection can alsa be use to complement the contents of the specified meman) location W the coments of the yndex register ate 01094, and contents of the memory Hocation O14) 2 (00100011), afler COM AMEN instruction 1s executed, the memory location O11, contacts DCy (110111009) The Bit Test Instruction The Dat Tet instruction (HHT) 1 similar Wy te lopscal Curpare The content of t sccumulator or memory locaton are ANDed with a mask However, esther the accumulator nor the enation 1s modificd by this wntrection on the aps are afte DITA. FOTN texts the bits 1.2 and Vof accumulator A an ithe sora flag Af Whe cradiion is tae Example: Following program cxamince ths byte at Focation 120 Mat 1 of Location 10 act $5u 9 stored in location 110), otherwise program Kcrminatey ona oot LDAA W301 toad bye DITA POM ivbit Pact? BLO STOP lit potsct, ed preva oan ESSE atare $$), a memory location 1304 STAD vot stor sw pool propa . $4 Arithmetic Operations S41 Addition Instructions Add Accumulatory ADA waraction ad) the contents of occumulater B to ti conssess of store the fesull i eccumalt ccumulslot A eotins By and asremslaor D afler tbe ADA unstracton 1s Add Memory to Accumulator ADDA. ADDIE respectively without ot mstrucuoe are sspportad ractions add We 6 sadeniny ents of a mony keaton wo asemstator A er D amy watus, The samme memory aiiresung optics a ADC Ea (bbls addition): The folowing program ats the content of memurylecatioms OD40, and OO tend place the result in the cmary lovaben OM. ono ol LDAA 40H ADDA aut STAA at swt ol progrAdd Memory, with carry, to Accumulator ADCA or ADCB instructions add the contents of @ memory location to accumulator A or B respocuvely 4 addressing modes are supported: 1 Immediate 2 Direct 3 Extended 4 Indexed Addition with carry using Immediate Data This type of instrucuon adds the immediate data with the carry bit to accumulator A. If accumulator A contains 3A), the carry bit ts 1, after the instruction ADCA #7CI is executed, the accumulator A contains B7y, Addition with carry using Direct Memory Addressing. This type of instruction adds the contents of a specified direct memory address and the carry bit to accumulator B. If accumulator B contains 3Ay and memory address 1Fy contains 7Cy, and carry bit contains | Afler the instruction ADCB IF It 1s exccuted, accumulator B contains B7), Addition wuth carry using Extended Addressing This type of instruction is similar to the addition with carry using direct addressing. Only difference is that ADCA 3FF2y instruction allows extended addressing Addinon with carry using Indexed Addressing This type of instruction adds the carry bit and the contents of a memory location addressed by the sum of index register and the first operand of ADCA instruction to accumulator A. If accumulator A contains 3Ay, Index register contains $0D,,, memory address $234 contains 76,, and the carry bit is 1, Afler the instruction ADCA IGIL,X is exccuted, accumulator A contains B1y, Ex (16-bit addition): Following program adds 16-bit number in memory locations 0040), and 00414, to the 16-bit number in memory locations 00421, and 0043,, The most significant eight bits are in memory locations 0040), and 0042), Then the result is stored into memory locations 0044y, and 0045), where the most significant bits are in 0044), ORG oH LDAA 41H ADDA 43H , add least significant bits STAA 45H LDAA 40H ADCA 42H add most significant bits with carry STAA 44H SWI send program ADCA 4211 adds the contents of accumulator A and the memory locati Fy location 0042, plus the « Cary (C) bat. The carry from the addition of the least significant eight bts ts thus incluhet edhe addition of the most significant exght bits ietaded tn the$4.2 Subtraction Subtract Memory from Accumulator SUDA, SUBD instructions subtract the contents of the selected memory byte from the contents of accumulator A or and I respectively. The same addressing modes of ADC instruction are supported If the memory address 0031y contains AO, and accumulator B contains E3,, after the SUBD MM instruction 1s executed accumulator B contains 434, $4.3 Shift Operations Logical Shift Operations LSRA, LSRD, LSR instructions perform a one-bit logical right shift on accumulator A, B or and a specified memory location respectively. The least significant bit is shifted into the carry bit in CCR and 0 15 inserted as a most significant bit If accumulator B contains 7A (01111010;), afer LSRB instruction 1s executed, accumulator B contains 3D,, (001111013) and the carry status bit ts set to 0 LSR instruction shifls the contents of the specified memory location towards right I-bit. Indexed and extended addressing modes are available for LSR instruction. If the contents of the ‘memary location O4F Ay is OD,s(000011013), after LSR OSFAI is exccuted, the carry bit 1s | and the ccantents of location O4F Aj, 1s 06 (000001103), Ex: Following program separates the contents of memory location 0040, into two 4-bit numbers and stores them in memory locations 0041, and 0042, It places the four consequitive most significant bits of memory location 0040, into the four least significant bit positions of memory location O04; and the four least significant bit positions of memory location 0040,, into the four least significant bit positions of memory location 0042s, LDAA ou ‘load data ANDA *0FH {mask off four MSBs STAA 2H + store at address 0042), LDAA son + reload data LSRA + shifl accumulator to right 4 bits, clearing the most significant bits LSRA ; LSRA i LSRA F STAA sin {store at adress 0041 Swi + end program Arithmetic Shift Operations ASLA or ASLB instructions perform a one-bit arithmetic left shift on the contents of accumulator A or B. If accumulator A contains TAy (OI111010;), after ASLA is executed Fay, (11110100,) 1s stored 1m accumulator A, carry bit is set to 0, sign bit is set 1 (as the leftmost bit is 1) and Zero bit 1s set to 0 ASL instruction performs a I-bit arithmetic left shift on the contents of « memary location The extended and mdexed addressing modes are supported, If the Index register contains 3F3Cy, and the memory address 3FR6y contains CBy, afer the ASL 4AHX instruction i executed, the memory address 3F86, contains %y, and Carry Mag is set to 1. The ASL instruction is ofen used ‘muluphcation routines Note that execution of a single ASL instruction results with its operand ‘muluplicd by a factor of 2[ASR instruction performs a one-bit arithmetic right shifl on the contents of accumulator A or Bor the contents of a selected memary byte. ASR is frequently used in division routines. Rotate Operations ROLA or ROLB instructions rotate the specified accumulator or a sclected memory byte one bit towards left through the carry bit, ROLA or ROLB instructions rotate contents of the specified accumulator and the carry bit as a block towards left one bit. If accumulator A contains 7A (O11110103) and the carry bit is 1, afer ROLA instruction is executed, accumulator A contains FSu (II1101014) and the carry bits resct to 0 ROL instruction rotates the contents of the specified memory location one bit to the left through the carry. Indexed and Extended addressing modes can be used with ROL instruction. Example: Ifthe contents of memory location 1403, is 2E1 (00101110,) and the Carry bit is 0, after ROL 140311 ts executed, memory location 1403y contains $C), (0101 1100,). RORA, RORB ot ROR instructions rotate the specified accumulator or contents of a sclected memary location and the carry bit as a black one bit towards right. These instructions operate similarly with the ROL instruction Ex (8-bit binary multiplication): Following program multiplies an 8-bit unsigned number in memory location 0041), by another 8-bit unsigned number in the memory location 0040, and places the most ‘agnificant bits of the result in memory location 0042y. and eight least significant bits im memory location 00434 Muluplying a number by zero results with zero, multiplying by one results with the number itself Therefore the multiplication can be reduced to the following operation: If the current bit is 1, add the rmuluplicand to the partial product. CLRA ; product MSB = Zero CLRB | product LSB = Zero LDX 8 —_; Joad number of bits of the multiplier to index register SHIFT ASLB { shuft product left 1 bit ROLA ASL 40H, shifl multiplier lef to examine next bit BCC DECR + ADDB 41H ; add multiplicand to the product if'carry 1s 1 ADCA #0 DECR. DEX BNE SHIFT; repeat until index register is 0 STAA 42H; store result STAB 4311 SWI «end program ‘The following operations are performed to ensure that everything is lined up correctly every time: 1) Shift muluplier left one bit so that the bit to be examined is placed in the Carry. 2). Shift product lef one bit so that the next addition is lined up correctly. ‘The complete process for binary multiplication is as follows: Step 1 - Iniualization The Indes register is wed as a counter, CLRA and CLRB set the product and carry bt to 0. Product0 Coumer=8Step 2 - Shifl Product fo let so as to line up propery. The instructions ASLB and ROLA together act ay a 16-bit anthmetic left shift of the product in accumulators A and B (MSBs in A}. Step 3 - Shift Muli to eft so the next hit goes o Carry to multiply The instruction ASL 40H shifls the contents of memory I significant bit inthe Cary and etearng the least significant it ion OO4OH left one bit, placing the mast Step 4- Add Moluplicand to Product ifeary is 1 The instruction ADDB 41H adds the mmultiplicand to the product, The instruction ADCA #0 adds the carry fag from that B-bit addition to the most significant eight bits ofthe product (in accurnulator A), IfCamry=1, Product ~ Product + Multiplicand ‘Step $ - Decrement counter und check for zero Counter = Counter = 1 If Counter #0, go to Step 2 If muluphier ts 61, and the multiplicand is GFy. the process works as follows: Initiaisation: Product 0000 Multiplier 61 Multiplicond — 6F Counter 08 ‘After first eration of steps: Product 000 Muluplier = C2 Muluphicand OF Counter 7 Carry from Multiplier 0 After second iteration: Product 0G Multiplier 84 Muliiplicand —6F Counter 06 Carry from Multiplier 1 After tied iteration Product o1aD Moltiplicr 08 Multiplicand OF Counter 05 Cary fom Multiplier 1 Goes like this until counter 1s equal to 0Ex (&-bIt binary diviston): Following program divides an 8-bit unsigned number in memory location (0040, by another 8-bit unsigned number in the memory location 0041, and stores the quotient in memory location 0042, and the remainder in memory location 0043, Initially accumulator “A ts cleared and dividend 1s loaded into accumulator B- Dung the division, the quotient replaces the dividend in accumulator B as the dividend ty shifted left to accumulator A. At the end, remainder 1s found in accumulator A and quotient in accurnulator B, LDX CLRA LDAB DIVIDE. ASLB ROLA MPA BCS SUBA INCB CHKCNT: #8 : load mumber of bits of the divisor into index register 40H + load dividend to accumulator B + shift left dividend-quotient. aunt + compare accumulator A and divisor CHKCNT branch ifaccumulator A is smaller than divisor st { subtract divisor from accumulator A, increment quoticnt decrement counter DIVIDE 2H store quotient aa {store remainder {end program Figure $ 1 - Flowchart of division program6. 6802 ASSEMBLY LANGUAGE PROGRAMMING III 61 STACK OPERATIONS {~ Aste” is simply an area of rhemory shore w fst of data items is stored consecutively hn consists of any numbst of locations in RAM memory, The tesetion in ths lst of th elements Hi Poe ints an be added or removed at one end of the Hist nly. This ends usually calle “Yop of eee ihe aruclare is sometimes referred 10 as a “pustrlown” suck. This Une of sonet seehamem 1 Lastln-First-Oul *LIFO™; the lst data item placed on the tac, js the ist one emoved when retnval begins PUSH operation places a new item on the sack. PULL operation removes the top item from the stack. AIC6s2 microprocessor allows @ porion of memory to be used us a sacl The inicroprocessing unt has a V6-bit slack pointer (Figure 6.1), When a byte of nformatien stored in the aioe stored af the address which is contained in the stack pointer. The stack point 1s Tesrenented {by onc) immediately following. ths storage of each byte of information it the stack Comerscly, the stack pointer is incremented (by one) immediately Before retest cach byte of wore fom the sack, and the byte 8 then obtained from the address contained 4m The stock pointer The programmer must ensure that the stack polnter Is initialized to the required address roe she fest execution of an instruction which manipulates the stack. Stach pointer &t be TiMatized to use any portion of read-wrile memory, usually to the highest address of RAM (Figure 6. DATA N xX MEMORY STACK POINTER Figure | Stash Pointer MEMORY. ~~ “Program ‘ond data aroa 7 ana in thus 00 A stack area grom in rss rect ‘Stack aroa . ob AFF Fugure 62 = Memory wageStack operations are used: + while executing subroutines + while handling interrupts + while doing arthmetic operations 6.1.1 PUSH Operation 7” PSII instruction 1s used for storing a single byte of data in the stack. This instruction addresses ceuther accumulator A of accumulator B (PSHA and PSHB respectively). The contents of the specified accumulator are stored in the stack. The address contained in the slack pointer is decremented. If accumulator A contains 3Ay and the stack pointer contains 1FFFy. After the instruction PSHA is executed 3A, is stored into the location IFFFy and the stack pointer is altered to IFFEy, the PC is O01 1, (Figure 6.3), Before Push Operation ‘After Push Operation A aa A ae se Oro se (OF Fe PC 00 10 PC 00 iW Memory Memory pc -» oo10 [TPSHA oro [PSH ont Pc > oott ‘Stack Memory ‘Stack Momory_ AFFD FFD ‘FFE SP > tFFE SP > FFF were [7 Figure 6.3 « Push (PSHA) instruction 6.1.2 PULL Operation >< PUL instruction retrives data from the stack, This instruction addresses cither accumulator A. oor accumulator B (PULA and PULB respectively). The address contained in the stack pointer is incremented, A single byte of data is then obtained from the stack and is londed into the specified accumulator, If the stack pointer contains 1FFEy and location 1FFF, contains CEy. After the instruction PULB 1s executed, accumulator B contains CEy, and the stuck pointer contains 1FFF (Figure 6.4) Before Pull Operation ‘Alter Pull Oporation 8 cry 8 cE sp (FTE se (FF pc [0 10 ec [Ceo Memory Mornory Pc -» ooo [Puig coo [puis ‘011 PC > ont suck |__Memory Stack |__Memory 1FFO AFFO SP —» FFE FFE wer (CE se -» sfF [cE6.1.3 Other Stack Operations The address stored in the stack pointer is affected by the execution of the instructions PSI, PUL, SWI, WAL, RTI, BSR, JSR, and RTS, and also by the servicing of a non-maskable interrupt or an interrupt request from a peripheral device ‘The address in the stack pointer may also be changed without storing or retricving information in the stack. This is carried out by the following instructions DES — decrement stack pointer INS increment stack pointer Lbs load the stack pointer TXS transfer index register to stack pointer ‘The contents of the stack pointer is also involved in the execution of the following instructions STS store the stack pointer TSX transfer stack pointer to index register STS instruction stores the contents of the stack pointer into two contiguous memory locations ‘This instruction offers direct, indexed and extended addressing modes. The STS instruction stores the high byte of the stack pointer into the specified memory address and the low byte into Wie menhary lddrese immediately following i. In figure 6.5, the contents of the stack pointer 1s FFF», and the emory address to store the stack pointer is given as 0080, in the STS FBO instruction. Afi STS retruction is exceuted, memory location 0080, contains the high byte of stack pointer (1 Fu) and memory location 00814, contains the low byte of stack pointer (FF) Before STS Operation Altor STS Operation sp (iF FF sp (iF FF | pc [00 _ 10 pc [00 2) Memor Memor PC —> 0010 ‘STS# 0010 oor [eon | oor [sts# | [eon | Sole PC > 0012 0080 0080 1F 0081 0081 Figure 6.5 - Store Stack Pointer (STS) instructionTSX instruction moves the contents of the stack pointer plus onc to the index register so that the index register points directly to the bottom of the stuck. In Figure 6.6, SP is IFFEy. After the execution of TSX instruction, index register contains IFFFy, The MC6802 employs a decrement alter vwnite, increment before read stack implementation scheme, Belore TSX Operation After TSX Oporation x x F FF se [iF FE sp [1 FE ec [on 10 ec [0 tt Data Memory Data Momory Program Memory Program Momory PC —p0010 TSK onto TSK 0011 Pc —p0011 Figure 6.6 - TSX Inctretion TXS instruction moves the contents of the index register minus 1 to the stack pointer. In Figure 6.7, contents of the index register is IFFF), After TNS is executed, stack pointer contains IFFE,, Before TXS Operation After TXS Operation x iF FF x iF FF SP sp iF FE ec (“oo —0 a a |_Oata Memory _| Data Memory Program Memory Program Memory Pc —»0010 1x3 oo10 TxS oon Pc —»o0it Figure 67 - Mave From Index Repister to Stick Pointer (TXS) instruction Example: In the following program, the contents of the accumulators are stored in the stack before branching to a rouune and at the end of routine, the orginal values of the accumulator are restored from the stack ORG 1001 LDAA #0311 LDAB #0411 LDS IFFFIL PSHA Psu. BRA LDRTCONT PULA PULB ABA STAA SWI LDRT- LDAA LDAB ABA STAA BRA 61H #O1H 02H GOH CONT At the beginning of the program accumulator A and B is loaded with 03 and 04), und stack pointer ts tialized to point the cud of memory (1FFFy). Then, before branching to the routine LDRT these numbers are stored in the stack using PSH instructions. In LDRT routine, O1y and 02,, are added using ABA instruction and (03,) is stored in memory location 0060, and CONT is branched. Then the onginal values of the accumulators are loaded from the stack using PUL instructions, the result (07) 15 stored in 00614 and the program ends with the exccution of SWI instruction.6.2 a In a given program itis offen necessary to perform a panicular task a number of times on the same or on different data values (such as subroutines to obtain time delay, subroutine to sor a Hist of values, etc ) including the block of instructions to perform the task al every place where it 1s needed in the program causcs a Waste of memory Instesd, itis better (a place only onic copy of this block of machine instructions in the main memory as a subroutine, and in the program branch tw the beginning of the subroutine whenever required In figure 6.8, the exccution of a jump to subroutine instruction (JSR) and retum froin subroutine instruction (RTS) are given. Afler JSR LONI instruction is exccuted, MC 1s set to the defined eddress and execution continuss vath the ADA msiruction, The program retums from this subroutine after the RTS instruction 1s executed. Program counter (PC) 1s set to 0023y and the programm execution continucs with ANDA. #7FIT inst Memory PC-» 0020|— JSR oo2i[ — or ———0022{ ——orr 0023} ANDA a |__+ ot00[ aga RTS SUBROUTINE Figure 63 - A subroutine execution process Rte 6.2.1 Jump toa subroutine JSR insiruchion uses extended and indexed addressing modes. After JSR instruction is executed, program counter 1s decremented by 3 (if extended addressing is used) of 2 (if indexed addressing ts wed), and then 15 pushed onto the stack. The slack pointer is adjusted to point to the next empty location in the stick. The specified memory address is then loaded into the program counter and execution conlinucs wth the first instruction inthe subroutine. Using Extended Addressing, Execution of JSR instruction with extended addressing mode is shown in Figure 69. After JSR OLOOIT instruction is erecuted, address ofthe next mstniction (AND_——-#TFIL instruction) 1s ‘stored on top of the stack, and SP 1s decremented by 2. Address of the first mstruction 1m the subroutine (0100,) 1s stored into the program counter, and the program continues trom this point. ABA instruction. 1s the next instruction to be executedBefore JSR Operation ‘Aster JSR Operation sp 7 F - FF. Pc. oor PC o_o [Program Memory | Program Nemor pc—> cou7[ ISR oor] SR, ‘oote|___at oove|___oF 19] 00, cots] 00 ootal__ AND ole co1e|___7FH coe] 7F o100[ ABA, Pc —» 0100___ABA, oxo1[_AT5, ororf_RIS, Stack 1FFO se —» FF Of FFE reo sp —> 1FFF| irre Figure 69 Jump to subrostine USR) nstraction, wing extended Using Indexed Addressing Exccunoa of JSR instruction with indexed addressing mode ts shown in Figure 610 Aber JSR AOI. instruction ts executed, address of the next ynstrucbon (001%) 1 stored on top ‘ack and SP 1s decremented by 2 Jump address 1s calculated ay the value of the undew regaster pls address part of the snstrusuon (1100, > 30, ~ 1130,) and atts stored in PC The program c= wath the ABA instructoa in the subrouune Before JSR Operation ‘After JSR Operation x a} x nC} SP FFF se a) PC cor Pc aE} [Program Memory Program Memory | Pc oo7[ ISR. co7[ ISR. corel 30x coef ux cor[ AnD & cors[__ANO coral eota[ TF 1130 Pc—» 1130[ ABR ais v3 as. Suck Stack Fro sb —b iro} wre wre op > FF wil) Vigare 610) tune (IR) tnstraston, ening a6.2.2) Return fi nn subroutine RTS instruction movey the contents of the lop (Wo st neat instruction after JSR) to propram counter Instruction to be executed. Presious program cou A bytes (whitch ts the address of the Thess two bytes provide the address of the next er contents are lost_ RTS instruction also increments, the stack pointer by 2 (Fig 6 11) Every subroutine must contain at [cast one Return unstruction; which 1s the last instruction to be execute in the subroutine: Ostore RTS Operation Alter RTS Operation sp Fo SP FF Pc or oF, po [0 Program Memory Program Memory | a cou|__aeR cote] __—or coral or ote{___o9 ors co. coral ave pc—» 0014] —ANOe cota[—— Ter ‘o01e[ — 7H 102] 7am, o1co| 7B, Po—» o1oi[—_ars o1oi___kIS Stack Stack sP— sFFO| FF] 1FeE| oo sFFe| 1FFFL a sp —> 1FFF| Figure 6.11 - Retum from subroutine (RTS) instruction Example: Determine the lengths of two strings of ASCII characters. Starting addresses of the strings are 434 and 63,1, End of a string is marked by a carriage return character (OD,), Write a subroutine which calculates the length of a slring (excluding camaye return character) and places it in accumulator B. Also wnte 4 calling program which calls this subroutine (0 calculate the lenghts of two strings and stores the results (1m accumulator B) in memory addresses 4211 and 62H, Calling Program: ORG on Los S001 LOX aH JSR STLEN STAB 2H LDx’ 63H JSR STLEN STAB eH swt Subroutine: ORG 100H STLEN: CLRB LDAA #ODH CHKCR. cMPA x BEQ DONE INCB INCX BRA CHKCR DONE RTs « Start stack at location SOOH + Get starting address of the first string « Determine string length 3 Store string length # Get starting address of second stn Determine string length Store sting length : String length = 0 Get *CR’ far comparison Is churacter ‘CR? + Yes, end of string No, add I to string length,The culling program initializes the stack pointer {0 $00, and then performs the following. steps for each string 1 places the starting address of the string in the Index register 2 calls the subroutine 3 stores the result in accumulator B 10 memory. The stack pointer must be initialized to an appropriate area in memory (in this example 500,;) so that the stack doey not use the addresses in the program area The subroutine determines the lenyth of a string of ASCII characters and places the length in accumulator B. Starting address of the stnng 1s a parameter to the subroutine. It is placed in the index register before the subroutine is jumped. The result is returned in accumulator B. If the first siring is only a camage retum character and index register (X) contains 0043y,, after the first call of the subroutine, contents of the registers and memory are as follows: Memory. 8 00 oa42[ xCa a 0430p. Fipure 6.12 = Memory allocated for the first string. If the second string is RATHER" and index register contains 0063), after the second call of the subroutine, contents of the registers and memory are ws follows: Memory 8 (os o062|— 06 x(_00 63 o063[__ 52, o064[ 41 o06s|_54 ooes| 48 oos7| 45 oosa|_—_52 0069{ 00 Figure 6 13 - Memory allacated for the second string$.2.3 Subroutine Nesting [A subrounine may jump to another subroutine as shown in Figure 614. This situation can be ‘extended to the case whste ths sscond subroutine jumps to w third subroutine and so on. This is ealled subroutine nesting, and can be cared out to any depth wan pHocRan re secowo cevet fusnounint Figure 6.14 - Subroutine nesting Example: The following program uses subroutine nesting to write the number FF) into a memory block Starting address of the memory block is 0), and the end of the block 1s determined by the number in accumulator B. Subroutine FILL, in a loop, stores 00,1 to the memory location pointed by the index register (X) and calls subroutine DECR to decrement accumulator B. ‘ORG Los LDx LDAA LDAB JSR SWI ‘ORG FILL: STAA INx JSR CMPB BNE RTS ORG DECR: DECB RTS 100H "FFF 00H +OFFH + itialize stating address of stack area ‘initialize index register keep FF in accumulator A + length of the memory block is 254 + start filling j store FF in the memory address pointed by 2 + increment X to point to the next location «jump to DECR subroutine {Isthe end of memory block reached? No, continue with the filling procedure Yes, end of subroutine + decrement accumulator B + Feturn to FILL subroutine5.3. MACROS In source programs, particular sequences of instructions may occur many times Programmer can avoid repeatedly writing out the same instruction sequence by using a macro Macros allow the programmer to assign a name to an instruction sequence. This macro name is then used in the source program in the place of the related instruction sequence. Before assembling ‘macroprocessor replaces the macro name with the appropriate sequence of instructions. Macros are not the same as subroutines. A subroutine occurs in a program, and program ‘execution branches to the subroutine. A macro is expanded to an actual instruction sequence cach time the macro occurs; thus a macro does not cause any branching. Figure 6.15 shows the source program with macro calls and the object program after the macro expansion. Source Program ‘Object Program Figure 6.15 - A macro call example $3.1 Macros in Cross-32 Cross Assembler MACRO and ENDM directives define the sequence of instructions in the source file as macro, Format of a macro definition is as follows Label: MACRO cexp(1), exp(2), .. exp (n) ; comment ine 1 line 2 ENDMUpon encountering a MACRO directive, Cross-32 stores the source code between the MACRO directive and the next ENDM directive, assigning the label on the MACRO line to it Although the code within the macro definition is checked for syntax crrors, the sulting machine code is not written to either the list or hexadecimal files. When the macro’s label is found as a macro call later in the assembly source code, the entire MACRO is expanded at this location. Any expressions appearing after the macro definition are replaced by those appearing after the macro call in the expanded code. These are character by character replacements, so ensure that the expressions in the macro definition are truly unique. The number of expressions in the macro definition must be equal to the number of expressions in the macro call. Nested macros are not permitted. Ex: Following program is an example for macro definitions and macro calls. cpu "6801.TBL" HOF "MOTS" ADDITION: | MACRO ZY; macro definition steps LDAA WZ ADDA AY ENDM ; macro ends ORG OH —— ; begin program ADDITION ——_10H,20 ; macro Call STAA 1000H__; store result in memory location (1000), ADDITION —12H,15_; macro Call STAA 1001H _; store result in memory location (1001), Swi ; End Program END B Examine the list file of the program to see that the Macro calls are replaced by the Macro definition.IF, ELSE, and ENDI - Conditional Assembly Cross-32 supports conditionaly assembly using the IF, ELSE and ENDI directives. This feature i usually used (0 re-configure a single assembly language program for diferent hardware environments Conditional assembly has the following syntax IF expression comment tine 1 ins 2 Ione n ELSE +comment Wine 1 lune 2 lune 0 ENDI + comment Upon encountering an IF statement Cross-32 evaluates the single expression following it AM Labels used in tis expression must be defined previous to the IF, Ifthe expression evaluates 10 zero, the statements between the IF and either an ELSE of an ENDI are not assembled. Ifthe expression results tn a non-zero value the statements between the IF and either an ELSE or an ENDI are assembled ELSE wan optional directive, allowing only one ofthe two sections of the source file within the TF block to be astembled. All conditional blocks must have an IF directive and an ENDI directive, the ELSE direeuve being optional. If blocks may be nested 16 deep before a fatal error occurs. ‘An cxample of conditionally assembly follows, where # microprocessor type is selected CPU “6801,TBL" HOF °MOTS" OPTION, EQUI IF OPTIO: + 16800 selected BRAVAR: — EQU —100H 7 ENDI IF OPTION + 176802 selected BRAVAR: == EQU. IIOH ENDI ORG 70H BRA BRAVAR CONT: STAA 85Hl Swi ORG 10011 LDAA #02H BRA CONT ORG 10H LDAA #03H BRA CONT END In this example Option 1 is selected so BRAVAR variable is set to 10OH. Accu Toaded with 02y, and then this value is stored in memory location 85y. If Option 2 is sel BRAVAR variable 1s set t0 110, which means that accumulator A is to be loaded with 03), and this Value 1s going to be stored in memory location 85y,1 MICROPROCESSOR INPUT/OUPUT TECHNIQUES. 7.1 MONITOR SUBROUTINES The DTOKO2 Microprocessor Traiminy Kit Monitor Proyram has subroutines dealing wath the 4eypad und the seven sepment display These subroutines accept an input from the keypad, and convert the output data into a suitable format that ean be displayed on the seven seyment display, DTOSO2 Monitor subroutines and thew sani adaresses ate shown in Table 7.1 Momory | Monitor Addross | Subroutine [“pFAOH | CLEARD | DFAIH PATCON DFAGH. DISPAT DFAGH RKEYC, Table 71 - Monitor Subroutines for VO Label CLEARD Memory Address * DFAO Function Clears the contents ofthe seven seyment displays. Input Parameter None Output Parameter~ None Example JSR ODFAGH + clears 7-segment display Label PATCON Memory Address ODFA3IT Converts the output into a binary number which can be displayed on the seven Function segment display. This subroutine sets the bits, which light the segments of the seven- segment display to 1 The data to be displayed must be loaded into accumulator A Input Parameter ‘Output Parameter The converted binary number is in accumulator A Example LDAA WOH JSR ODFASIT In this example, accumulator A is loaded with “O" and then the program jumps to the subroutine at addressed ODFA3H. After the subroutine is exccuted, accumulator A contains O3FH which is the code to light the segments of the display for displaying churucter “0”. Label = DISPAT. Memory Address . ODFA6IL Function 2 Selects a seven segment display for displaying a cl Input Parameter: The converted data must be in accumulator A, and code of the selected 7- segment display must be in accumulator B. Output Parameter; None iricter Example LDAA HOH JSR ODFAOH LDAB #OIH JSR ODFAGH In this example, character 0 is displayed on the first seven segment display. Note that before jumping 10 DISPAT subroutine, the data must have been converted using PATCON subroutine and the code of the selected seven segment display must exist in accumulator B. Codes for selecting the seven segment Aduplays are given in Table 7 2Table 7.2 - Codes for te seven segment displays Label RKEYC Memory Address : ODFASH Function + Wats for an input from the keypad. When 1 key is pressed, the predetermined value of this key is loaded 10 accumulator A. Input Parameter: None Output Parameter: Value of the key pressed is in accumulator A Example JSR ODFAQH ANDA 13FH When key is pressed, its predetermined value is loaded to accumulator A (Table 7.3), Then accumulator A is ANDed with 3FH. The keys and their predetermined values are given in Table 7.3. Predetermined value ed V 0 oor OAH 1 on oBH 2 02H OCH 3 03H oD 4 4H OE 5 Osi OFH 6 OGIL loll 7 O7H un 8 8H 9 OoH ‘Table 7.3 - Predetermined values of keypad heys,7.2 Baste InpuvOurput Figure 7'I shows the MPU bus and control structure where procewsor's inputs and outputs Coy fumetonal categories. data. adress, control and supcrisory MCUSUI AMictopereessor has oy 8c bidirectional bus to faciiate data low throught the system(Dala bus). Addron De dows met only PRecily memory addressss, but also it a tool to specify 10 devices. By means of ils connections te Data Bus, Control Bus, and selected address lines, the LO interface ws allocated wan ares of memory Hse may converse with VO using any of the memory interface reference instructions, sleclung the desired perpheral with memory address. Control Bus 1s provided for the memory and interface devices Consists of a heterogenous mix of signals to regulate system operation. MPU supervisory, «used for liming and contro} of the MC6802 stscif. Three signals are shared with the control bus and afleet the memory and 1/0 device as well Say = _—a ee mY . TI » td eats ora |“ Figure 7.1 « MC6802 Bus and Control Signals Every penpheral device is assigned a block of memory addresses (These blocks do not intersect), During instruction decoding. the address decoding citcuit of the microprocessor enables only fone peripheral device and other devices are set to high impedance mode Inputs of the address decoding circuit are connected to the address bus and necessary control ourputs (such as RW, E, .) and outputs of this circuit are connected to chip select lines (CS) of each penpheral device. 74ALS27 (NOR Gate) and 74LS30 (NAND Gate) in Figure 7.2 are used for address decoding circuit (chip select), 74LS125 (Tri-state buffer) und toggle switches are used for input om ae ine Cen ey Tay ii raat ras Figure 7.2 - Input to a microprocesor unitIn Figure 7.2 CS output is reset to Logic “0” only when AIS@A13A12°A10~AB=R\W~E= Logic “17 and Ald=A11=A9= Logie “0 where A is the address line, R\W is the Read\Woite output , E is the Enable output ‘That ts: aps ea eee apepeperars aye sbel+t:tet+tet+t+)xlelxtutxTxt | | q q g 8 3 When the address output of the microprocessor is between BS00,, and BSFFy, and R/W ts Read”, and E is 1, 74L5125 tn-state buffer (whose state diagram and truth table 1s shown in Figure 7.3) 1s enabled, which means that the inputs from the toggle switches are read and the data is scnt 10 MPU using data lines. Otherwise the buffer 13 in high impedance mode. Cc — cs Q D Q High ojo Tri-state Truth Table Figure 7. - Tn-state bufler and ts state diagram Example: The following program applies an input to the microprocessor unit ORG 10011 LOAD B500 read toggle switches ANDB #OFH —, mask four MSBs STAB O1OOH write data read from toggle switches into address 0100), sw Example: The following program clears the display then starts an infinite loop which reads the status of the toggle switches and displays the resull on the seven segment display ISR ODFAOH : CLEARD RETOG: LDAA BSOOH + read toggle switches ANDA #OFH mask four MSBs JSR ODFAIH : PATCON LDAB #OIH | select seven segment display JSR ODFAGH DISPAT BRA RETOG infinite loop JSR ODFAOH instruction clears the display. Then, program reads the input from toggle switches (when B50, is given as input to the address decoding circuit), and jumps to the subroutine at address ODFA3,, (PATCON). This subroutine, converts a data into a ‘code which can be displayed on the seven segment display. Then the program jumps to the subroutine at address ODFA6y, (DISPAT). which display’ the converted data on the seven segment display. This process is repeated in an infinite loop. In this loop when the condition of the toggle switches changes, the data displayed on the seven segment display also changes13 MC6820 PIA (Peripheral Interface Aday The MC6R20 Per ‘eripheral Interfa connecting byte-oriented peri ice Adapter (PIA), in Figure 7.4, provides w flexible eens werent the MPU, The PLA, while relively conpies hee eat programming. OF equipment types with minimum addivonal logic end simple pter) Figure 7.4 - MPUMPIA Interface Data flows between the MPU and the PIA on the System Data Bus via cight bi-directional data lines, DO through D7. The direction of data flow is controlled by the MPU via the Read/Write ‘mput to the PLA. The “MPU side” of the PIA also includes three chip select lines, CS0, CS1, C52, for selecting 3 panicular PIA. Two register select inputs, RSO and RSI, arc used in conjuction with a control bit (b) within the PIA for selecting specific registers in the PIA. Figure 7.6 shows the PIA control register format. The MPU can read or write into the PIA’s internal registers by addressing PIA via the System Address Bus using these five input lines and the R/W signal. From the MPU's point of view, each PIA is simply four memory locations that are treated in the same manner as any other read/write memory. Table 7.5 shows the memory addresses that can be accessed by the MPU and the corresponding PIA registers. ‘Address _| PIA Register E0004 ‘Output and data direction register (Pon A) E001, Control register (Port A) E0024 Output and data direction register (Pon B) | E003, Control register (Port B) Table 7 $- PIA Register Addresses The MPU also provides a timing signal (o the PIA via the Enable input. The Enable (E) pulse is used to condition the PLA’s internal interrupt control circuitry and for the timing of peripheral control signals. The “Penpheral side” of the PIA includes two 8-bit bi-directional data buses (PAO - PAT and PBO - PB7) and four interrupvcontrol lines (CAI, CA2, CBI, CB2) (Figure 7.5). All of the lines on the “Peripheral Side” of the PLA are compatible with standard TTL Logic. In addition, all lines serving as ourputs on the “B” side of each PIA (PBO-PB7, CBI, CB2) will supply up to one miliamp of drive current at 1.$ vols, therefore resulting in a more suitable part to use with current requesting peripherals (such as leds ete.)on on) Ese] -* Figure 75 - PIA Repisiers Internal Organization Inmemally, the PIA 1s divided anto symmetrical independent fo eer res. an Output Register, a Control Register, and a Date Direc! deena yy AIPU as. memory locations from which data can Be either read or To iteputers on each side represents 2 single memory localjon My panes raternal to the PIA. and determined by'a bit in their Control Sera data structure implies the third bit from the least has three 75) These requsters are written. The Output and Data Dar the MPU. The selection between U x (at is common convention that bit ine mo the establish each individual peripheral bus ‘MPU wnte “ones” of "Zero: ding peripheral data lines to function Dats Direction Registers (DDR) are used to ether an input or an output. This 1s accomplished by having the fight bit positions of the DDR. Zeros or ones eause the correspon ‘as inpuls or outpuls, respectively Output Registers, when addressed, store the ante operation. This data will immediately appear on hose peripheral lines that programmed a5 outputs. Dunng an MPU Read operation, the data present on peripher programed as inputs, transferred directly tothe system Dats Bus Data Bus during MPU ve been hines, data present on the MPU the MPU to establish and control the operating modes of the Two Control Registers, allow ssed back and forth between the PIA. Itis by means of these four lines that control information 1s pas: MPU and penpheral devices. he register select lines to select the status bit b of the Data Data Direction Register access is used in conjunction with 1 1=0) or the Output Register (if between intemal registers. For @ given register select combination, Durecuon Register determines whether the Data Direction Register (if b2 bb2=1) 1s addressed by the MPU.