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ELEC 2607 Pre Lab 4

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63 views4 pages

ELEC 2607 Pre Lab 4

Uploaded by

diaansiddiky
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ELEC 2607 Prelab 4

2.

module binary_2_seven_seg(
input [3:0] binary_input,
output reg [6:0] bits_out
);

always @* begin
case (binary_input) // CG, CF, CE, CD, CC, CB, CA
4'b0000: bits_out = 7'b0000001; // '0'
4'b0001: bits_out = 7'b1001111; // '1'
4'b0010: bits_out = 7'b0010010; // '2'
4'b0011: bits_out = 7'b0000110; // '3'
4'b0100: bits_out = 7'b1001100; // '4'
4'b0101: bits_out = 7'b0100100; // '5'
4'b0110: bits_out = 7'b0100000; // '6'
4'b0111: bits_out = 7'b0001111; // '7'
4'b1000: bits_out = 7'b0000000; // '8'
4'b1001: bits_out = 7'b0000100; // '9'
4'b1010: bits_out = 7'b0001000; // 'A'
4'b1011: bits_out = 7'b1100000; // 'B'
4'b1100: bits_out = 7'b0110001; // 'C'
4'b1101: bits_out = 7'b1000010; // 'D'
4'b1110: bits_out = 7'b0110000; // 'E'
4'b1111: bits_out = 7'b0111000; // 'F'
default: bits_out = 7'b1111111; // Blank display
endcase
end
endmodule

3.

4.
5. I'm not sure

6. module System
// Inputs
input [15:0] SW // Switches for input values
input Load_Reset_BTN // Button to load/reset values
input Count_BTN // Button to increment count

// Outputs
output [6:0] C_A_F // 7-segment display output (A-G)
output [3:0] AN_0_3 // Digit enable (anodes for each 7-segment display)

// Internal Registers
reg [3:0] Reg_0 // 4-bit register to store SW[3:0]
reg [3:0] Reg_1 // 4-bit register to store SW[7:4]
reg [3:0] Reg_2 // 4-bit register to store SW[11:8]
reg [3:0] Reg_3 // 4-bit register to store SW[15:12]

// Seven-Segment Controller Instance


SevenSegmentController segment_controller (
.digit0(Reg_0),
.digit1(Reg_1),
.digit2(Reg_2),
.digit3(Reg_3),
.segment_output(C_A_F),
.anode_output(AN_0_3)
)

// Load or Reset Logic


always @(posedge Load_Reset_BTN) begin
// Load switch values into registers if Load_Reset_BTN is pressed
Reg_0 <= SW[3:0]
Reg_1 <= SW[7:4]
Reg_2 <= SW[11:8]
Reg_3 <= SW[15:12]
end

// Count Logic
always @(posedge Count_BTN) begin
// Increment Reg_0 value on each Count_BTN press
Reg_0 <= Reg_0 + 1
// Add any overflow handling if necessary
end
endmodule

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