COMPUTER

ORGANIZATION AND
ARCHITECTURE
1
Course Code : CSE 2151
Credits : 04
FACULTY DETAILS

▪ Name: Mrs. Mahadevi S.

▪ Qualification: B.E., M.Tech., PhD(NITK)
▪ Phone: +91 8147797892
▪ Email: [email protected]
▪ Address: 5th floor, Faculty room no: 2, MIT Building

2
COURSE OBJECTIVES
This course will enable students to

▪ Summarize the fundamental concepts of the organization and architecture of a computer.

▪ Analyze taxonomy of Execution, Processor, Memory and I/O Units.

▪ Explain the pipelining principles, Data dependencies and hazards, SIMD and Multiprocessor concepts.

3
COURSE MODULES
1. Basic structure of computers

2. Instruction set architecture

3. Arithmetic and logic unit

4. Control unit

5. Memory systems

6. Input/output organization

7. Introduction to parallel architecture

4
COURSE OUTCOMES
No. of
At the end of this course, the student should be able to: Marks
Hours

Describe the functionalities of the various units of computers and the

CO1 10 20
instruction set architecture.

Appreciate the hardware implementation of addition, subtraction,

CO2 7 16
multiplication, and division and perform arithmetic operations.

CO3 Design the control unit for simple algorithms. 10 20

Explain basics of memory system such as cache memories, mapping

CO4 functions, replacement algorithms and virtual memory concept and 10 20
design simple memory systems.
Outline the I/O handling techniques and realize the improvement in
CO5 11 24
performance using the concepts of pipelining and parallel processing.

Total hours/ Marks 48 100

5
TEXTBOOKS AND REFERENCE BOOKS
Textbooks:
1. Carl Hamacher, ZvonkoVranesic and SafwatZaky, Computer Organization and Embedded Systems, (6e), McGraw Hill
Publication, 2012.
2. William Stallings, Computer Organization and Architecture – Designing for Performance, (9e), PHI, 2015.

3. Mohammed Rafiquzzaman and Rajan Chandra, Modern Computer Architecture, Galgotia Publications Pvt. Ltd., 2010.

Reference Books:
1. D.A. Patterson and J. L. Hennessy, Computer Organization and Design-The Hardware/Software Interface, (5e),
Morgan Kaufmann, 2014.
2. J. P. Hayes, Computer Architecture and Organization, McGraw Hill Publication, 1998.

6
INTRODUCTION
▪ What is Computer Organization and Architecture?

7
INTRODUCTION

▪ Addition of 2 bits

Figure 2: Structure to add two bits

Figure 3: Half Adder using NAND gates.

8
INTRODUCTION

▪ Addition of 2 bits

Figure 2: Structure to add two bits

Figure 4: Half Adder using NOR gates.

9
INTRODUCTION
▪ Computer Architecture: refers to those attributes of a system visible to a
programmer or those attributes that have a direct impact on the logical
execution of a program.
▪ Example: instruction sets, the number of bits used to represent various datatypes, I/O mechanisms and
techniques for addressing memory.

▪ Computer Organization: refers to the operational units and their

interconnections that realize the architectural specifications.
▪ Example: hardware details transparent to the programmer, such as control signals, interfaces between
the computer and the peripherals; and the memory technology used.

10
BASIC STRUCTURE OF COMPUTERS
• The different types of computers
• The basic structure of a computer and its operation
• Machine instructions and their execution
• Number and character representations
• Addition and subtraction of binary numbers

MODULE 1
TYPES OF COMPUTERS

1. Embedded computers

2. Personal computers

3. Servers and Enterprise systems

4. Supercomputers and Grid computers

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TYPES OF COMPUTERS
▪ Embedded computers

▪ Integrated into a larger device or system in order

to automatically monitor and control a physical

process or environment.

▪ Used for a specific purpose.

▪ Applications include industrial and home

automation, appliances, telecommunication
products, and vehicles

13
TYPES OF COMPUTERS
▪ Personal computers

▪ Primarily for dedicated individual use.

▪ Types of personal computers

i. Desktop computers

ii. Workstation computers

iii. Portable and Notebook computers

▪ Applications include general computation, document

preparation, computer-aided design, audiovisual

entertainment, interpersonal communication, and
Internet browsing

14
TYPES OF COMPUTERS
▪ Servers and Enterprise systems

▪ Large computers shared by many users through

personal computer over a public or private

network.

▪ May host large databases and provide information

processing for a government agency or a

commercial organization.

15
TYPES OF COMPUTERS
▪ Supercomputers and Grid computers

▪ Offer the highest performance

▪ Most expensive and physically the largest

category of computers.

▪ Supercomputer

▪ High-cost systems.

▪ Performance of a supercomputer is measured in

floating-point operations per second (FLOPS) instead

of million instructions per second (MIPS)

▪ Applications include high demanding computation

systems such as weather forecasting, engineering

design and simulation, and scientific work. 16
TYPES OF COMPUTERS
▪ Supercomputers and Grid computers

▪ Grid computers

▪ More cost-effective alternative

▪ A grid of large number of personal computers and

disk storage units are created using a physically

distributed high-speed network, which is managed as
a coordinated computing resource.

▪ The computational workload is distributed across the

grid to achieve high performance on large

applications ranging from numerical computation to
information searching.

17
TYPES OF COMPUTERS
▪ Cloud Computing

▪ Distributed computing and storage server

resources for individual, independent, computing
need accessed via personal computers.

▪ Communication facility via internet.

▪ Cloud hardware and software service providers

operate as a utility and charge on a pay-as-you-use

basis.

18
TYPES OF COMPUTERS

1. Embedded computers

2. Personal computers

3. Servers and Enterprise systems

4. Supercomputers and Grid computers

▪ Cloud Computing

19
FUNCTIONAL UNITS
▪ Input Arithmetic
Input and Logic
▪ Output
Interconnection
▪ Memory Network
Output Control
▪ Arithmetic and Logic Unit
I/O Processor
▪ Control Unit

Memory

20
HOW DOES THE COMPUTER HANDLE INFORMATION?
▪ Instructions are explicit commands that

▪ govern the transfer of information within a computer as well as between the computer and its I/O devices

▪ specify the arithmetic and logic operations to be performed

▪ A program is

▪ a list of instructions which performs a task.

▪ stored in the memory.

▪ Data are
▪ numbers and characters that are used as operands by the instructions.

▪ stored in the memory.

▪ Instructions and data are encoded in binary format (0 and 1) 21

INPUT UNIT
▪ Keyboard
▪ Whenever a key is pressed, the corresponding
letter or digit is automatically translated into its
corresponding binary code and transmitted to the
processor

▪ Graphic input
▪ touchpad, mouse, joystick, and trackball.
▪ Audio and Video input
▪ The audio input captured by microphones and
video input captured by camera are sampled and
converted into digital codes for storage and
processing.

▪ Digital communication facility: Internet

▪ provides input to a computer from other
computers and database servers. 22
OUTPUT UNIT
▪ send processed results to the outside world.

▪ Graphic display

▪ Printers

▪ Audio output: Speakers, headphones

23
MEMORY UNIT
▪ Store programs and data

▪ Two classes of storage

▪ Primary memory or main memory
▪ Secondary Storage

24
MEMORY UNIT
▪ Primary Memory
▪ Fast memory
▪ Programs are stored in this memory while being
executed
▪ Large number of semiconductor storage cells
capable of storing one bit of information
▪ Words: groups of cells, fixed size.
▪ Word length of the computer: number of bits in each
word -16, 32, or 64 bits.
▪ Address: associated with each word location.
Consecutive numbers, starting from 0, that identify
successive locations.
▪ Random-access memory (RAM): A memory in
which any location can be accessed in a short and
fixed amount of time after specifying its address
▪ Memory access time: The time required to access
one word. This time is independent of the location of
the word being accessed. Typically ranges from a
few nanoseconds (ns) to about 100 ns.
25
MEMORY UNIT
▪ Primary Memory
▪ All programs stored in the secondary
memory must be loaded from secondary
memory to primary memory (RAM) before
its execution.
▪ The data is then transferred to the cache, a
smaller, faster RAM unit, for fast retrieval of
instructions to the CPU

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26
MEMORY UNIT
▪ Cache Memory
▪ Used to hold sections of a program that are
currently being executed, along with any
associated data
▪ is tightly coupled with the processor and is
usually contained on the same integrated-circuit
chip
▪ facilitates high instruction execution rates

27
MEMORY UNIT
▪ Cache Memory
▪ At the start of program execution, the cache is
empty.
▪ As execution proceeds, instructions are fetched
into the processor chip, and a copy of each is
placed in the cache.
▪ Suppose several instructions are executed
repeatedly as happens in a program loop and
these instructions are available in the cache, they
can be fetched quickly during the period of
repeated use.
▪ Similarly, if the same data locations are accessed
repeatedly while copies of their contents are
available in the cache, they can be fetched
quickly.

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28
MEMORY UNIT
▪ Secondary Memory
▪ used when large amounts of data and many
programs must be stored, particularly for
information that is accessed infrequently.
▪ Access times for secondary storage are longer
than for primary memory.
▪ magnetic disks, optical disks (DVD and CD), and
flash memory devices.

▪ Memory Hierarchy
▪ Secondary > Primary > Cache (storage)
▪ Secondary < Primary < Cache (speed and cost)

29
ARITHMETIC & LOGIC UNIT
▪ Most computer operations are executed in ALU of
the processor.
▪ Load the operands into memory – bring them to
the processor – perform operation in ALU – store
the result back to memory or retain in the
processor.
▪ Registers-high-speed storage elements-store one
word of data
▪ Fast control of ALU

30
CONTROL UNIT
▪ All computer operations are controlled by the
control unit.
▪ The timing signals that govern the I/O transfers
are also generated by the control unit.
▪ Control unit is usually distributed throughout the
machine instead of standing alone.

31
OPERATIONS OF A COMPUTER
▪ Accept information in the form of programs and
data through an input unit and store it in the
memory
▪ Fetch the information stored in the memory, under
program control, into an ALU, where it is then
processed
▪ Output the processed information through an
output unit
▪ All activities inside the machine are controlled
through a control unit

32
BASIC OPERATIONAL CONCEPTS
▪ A typical instruction set:
▪ Load R2, LOC

▪ Add R4, R2, R3

▪ Store R4, LOC

▪ Load R2, LOC

▪ reads the contents of a memory location with address
represented as LOC and loads them into processor
register R2
▪ Add R4, R2, R3
▪ adds the contents of registers R2 and R3 and stores
the result in R4
▪ Store R4, LOC
▪ copies the operand in register R4 to memory
location LOC

33
CONNECTION BETWEEN THE PROCESSOR AND THE MEMORY

34
REGISTERS
▪ Instruction register (IR)
▪ holds the instruction that is currently being
executed. Its output is available to the control
circuits, which generate the timing signals that
control the various processing elements
involved in executing the instruction
▪ Program counter (PC)
▪ points to the next instruction that is to be
fetched from the memory
▪ General-purpose register (Accumulator Register)
▪ R0 – Rn-1
▪ Holds operands that have been loaded from the
memory for processing

35
PROCESSOR-MEMORY INTERFACE
▪ It is a circuit which manages the transfer of data
between the main memory and the processor.
▪ If a word is to be read from the memory, the
interface sends the address of that word to the
memory along with a Read control signal.
▪ The interface waits for the word to be retrieved,
then transfers it to the appropriate processor
register.
▪ If a word is to be written into memory, the
interface transfers both the address and the word
to the memory along with a Write control signal.

36
TYPICAL OPERATING STEPS
▪ Programs to be executed must be in main memory

▪ PC is set to point to the first instruction

▪ The contents of PC are transferred to memory along

with a Read control signal
▪ The first instruction read out is transferred to IR

▪ The instruction is ready to be decoded and executed

▪ Get operands for ALU

▪ Memory
▪ General-purpose register

▪ Perform operation in ALU

▪ Store the result back

▪ To general-purpose register
▪ To memory

▪ During the execution, PC is incremented to the next

instruction 37
INTERRUPTS
▪ Normal execution of programs may be preempted
if some device requires urgent servicing.
▪ The normal execution of the current program must
be interrupted – the device raises an interrupt
signal.
▪ Interrupt-service routine

▪ Current system information backup and restore

(PC, general-purpose registers, control
information, specific information)

38
EXERCISE
▪ List the steps needed to execute the machine instruction

Load R2, LOC

▪ Solution:
▪ Send the address of the instruction word from register PC to the memory and issue a
Read control command.
▪ Wait until the requested word has been retrieved from the memory
▪ load it into register IR, where it is interpreted (decoded) by the control circuitry to
determine the operation to be performed.
▪ Increment the contents of register PC to point to the next instruction in memory.
▪ Send the address value LOC from the instruction in register IR to the memory and issue
a Read control command.
▪ Wait until the requested word has been retrieved from the memory, then load it into
register R2

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EXERCISE
▪ Repeat for
i. Add R4, R2, R3
ii. Store R4, LOC

40
EXERCISE
▪ Give a short sequence of machine instructions for the task
▪ Add the contents of memory location A to those of location B, and place the answer in location C
▪ Following instructions are the only instructions available to transfer data between the memory
and the general-purpose registers.
▪ Load Ri, LOC

▪ Store Ri, LOC

▪ Do not change the contents of either location A or B.

41
TOPICS COVERED FROM
▪ Textbook 1:
▪ Chapter 1: 1.1, 1.2, 1.3

42
EXERCISE
▪ Give a short sequence of machine instructions for the task
▪ Add the contents of memory location A to those of location B, and place the answer in location C
▪ Following instructions are the only instructions available to transfer data between the memory
and the general-purpose registers.
▪ Load Ri, LOC

▪ Store Ri, LOC

▪ Do not change the contents of either location A or B.

▪ Solution:
▪ Load R3, A
▪ Load R4, B
▪ Add R5, R3, R4
▪ Store R5, C

43
NUMBER REPRESENTATION AND ARITHMETIC OPERATIONS
▪ Number representation
▪ Decimal number system:
▪ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9
▪ Each digit has a position value in terms of powers of 10
▪ 123= 1 * 102 + 2 * 101 + 3 * 100

▪ Binary number system

▪ 0, 1
▪ Each digit has a position value in terms of powers of 2

44
INTEGER
▪ Unsigned integer
▪ If the integers are represented using 4 bit
▪ 0(10) in binary?
0000
▪ 15(10) in binary?
1111 = 1 * 23 + 1 * 22 + 1 * 21 + 1 * 20

▪ Signed integer

45
INTEGER
▪ Unsigned integer
▪ If the integers are represented using 4 bit
▪ 0(10) in binary?
0000
▪ 15(10) in binary?
1111 = 1 * 23 + 1 * 22 + 1 * 21 + 1 * 20

▪ Signed integer
▪ Sign and magnitude
▪ One’s complement
▪ Two’s complement

▪ In all three systems,

▪ the positive numbers have the same bit representation
▪ the negative numbers have different bit representation
▪ positive numbers - the leftmost bit is 0
▪ negative numbers- the leftmost bit is 1
46
SIGNED INTEGER: SIGN AND MAGNITUDE
▪ Negative values - most significant bit of the Positive Value b3 b2b1b0 b3 b2b1b0 Negative Value
corresponding positive value changed from 0 to 1 1111 -7
+7 0111
▪ Sign- MSB
+6 0110 1110 -6
▪ Magnitude (or number)- remaining bits
+5 0101 1101 -5
▪ 0 represented as positive and negative
+4 0100 1100 -4

+3 0011 1011 -3

+2 0010 1010 -2

+1 0001 1001 -1

+0 0000 1000 -0

47
SIGNED INTEGER: ONE’S COMPLEMENT
▪ Negative values - complementing each bit in Positive Value b3 b2b1b0 b3 b2b1b0 Negative Value
the corresponding positive value +7 0111 1000 -7
▪ Negative to positive- complementing each bit 1001 -6
+6 0110
in the corresponding negative value
+6 0110 +5 0101 1010 -5

-6 1001 +4 0100 1011 -4

▪ For n-bit numbers, this operation is equivalent +3 0011 1100 -3

to subtracting the number from 2n − 1.
+2 0010 1101 -2
▪ Example: +6 to -6 in a 4-bit representation
+1 0001 1110 -1
▪ 2n-1 =15 1111
+6 0110 +0 0000 1111 -0
-6 1001
▪ 0 represented as positive and negative

48
SIGNED INTEGER: TWO’S COMPLEMENT
▪ Negative values - adding 1 to the 1’s- Positive Value b3 b2b1b0 b3 b2b1b0 Negative Value
complement of corresponding positive value +7 0111 1000 -8
▪ Example: +6 to -6 in a 4-bit representation 1001 -7
+6 0110
▪ 2n-1 =15 1111
+5 0101 1010 -6
+6 0110 conversion using
1001 1’s complement +4 0100 1011 -5
+1 0001 1100 -4
+3 0011
-6 1010
+2 0010 1101 -3
▪ For n-bit numbers, this operation is equivalent
1110 -2
to subtracting the number from 2n. +1 0001

1111 -1
▪ Example: +6 to -6 in a 4-bit representation +0 0000
▪ 2n 10000
+6 00110
-6 01010
▪ 0 represented as positive 50
SIGNED INTEGER: TWO’S COMPLEMENT
▪ 4 bits: -8 to +7
-24-1 to +24-1-1
▪ 5 bits: -16 to +15
-25-1 to +25-1-1
▪ 6 bits: -32 to +31
-26-1 to +26-1-1
▪ n bits: -2n−1 to +2n−1 − 1

51
SIGNED INTEGERS
▪ For 4-bit numbers, the value −8 is
representable in the 2’s-complement
system but not in the other systems.
▪ Sign-and-magnitude system seems the
most natural
▪ 1’s-complement system is easily related to
this system
▪ 2’s-complement appears unusual.
▪ However, it leads to the most efficient way to
carry out addition and subtraction operations.
▪ It is the one most often used system in
modern computers.

52
UNSIGNED INTEGERS: OPERATIONS
▪ #include <iostream>
using namespace std;
int main() {
unsigned short x=65535, y=65537;
cout<<x<<" "<<y<<endl;
return 0;
}
▪ x=65535, y=1
▪ unsigned short: 16 bits
▪ 0 to 65535 (0 to 2n-1)
▪ If the value is out of range, it is divided by largest_number+1 of that datatype, and
only the remainder kept.
▪ Here, 65537 % 65536= 1
▪ Any number bigger than the largest number, “wraps around” the largest number in
that type.
53
UNSIGNED INTEGERS: OPERATIONS
▪ #include <iostream>
using namespace std;
int main() {
unsigned short x=0, y=-1;
cout<<x<<" "<<y<<endl;
return 0;
}
▪ x=0, y= 65535
▪ wraps around to the top of the range.

54
UNSIGNED INTEGER: ADDITION
▪ 7 (0111) + 5 (0101) = ?
▪ From 7 move 5 units in clockwise direction
▪ 12

▪ 9 + 14=?
▪ From 9 (1001) move 14 units in clockwise direction
▪ 7

55
UNSIGNED INTEGERS: ADDITION
▪ 2-bit addition:

▪ Multiple bit addition

▪ Similar to decimal addition method
▪ add bit pairs starting from the low-order end of the bit vectors, transmitting the carries
toward the high-order end
▪ The carry-out from the previous bit pair becomes the carry-in to the current bit pair
▪ The carry-out from the bit pair in the right must be added to the current bit pair to
generate the sum and carry-out at that position
▪ If both bits of a pair are 1 and the carry-in is 1, then the sum is 1 and the carry-out is 1

56
TOPICS COVERED FROM
▪ Textbook 1:
▪ Chapter 1: 1.4.1

57
SIGN AND MAGNITUDE: ARITHMETIC OPERATIONS
▪ Add +5 and -2 = +3 (4-bit representation)
0 101 +
1 010
111 (7) incorrect

▪ Subtract -6 and 1 = -7 (4-bit representation)

1 110 -
0 001
101 (5) incorrect

▪ Hence, not suitable for arithmetic operations

58
1’S COMPLEMENT: ARITHMETIC OPERATION
▪ Add +1 and -1 = 0 (4-bit representation)
0 001 +
1 110
111 (wrong answer!!)
+ 1
000 (correct answer)

▪ Additional step (hardware) required to arrive at the correct answer.

▪ Hence, not suitable for arithmetic operations

59
2’S COMPLEMENT: ARITHMETIC OPERATION (ADDITION)
▪ Add +7 and -3
▪ +7 is 0111 and -3 is 1101,
▪ Locate 0111 in the diagram and move 1101 (13) steps in clockwise
▪ Solution: 0100
▪ 2’s-complement representation of −3 is interpreted as an unsigned
value for the number of steps to move.
▪ Adding bit pair wise:
▪ ignore the carry-out

60
2’S COMPLEMENT: ADDITION
▪ +2 + (+3) ▪ -5 + (-2)

+2→ 0010 + -5→ 1011 +

+3→ 0011 -2→ 1110
+5→ 0101 -7→ 1001
Carry is ignored

▪ +4 + (-6) ▪ +7 + (-3)

+4→ 0100 + +7→ 0111 +

-6→ 1010 -3→ 1101
-2→ 1110 +4→ 0100
Carry is ignored

61
2’S COMPLEMENT: ADDITION AND SUBTRACTION
▪ To add two numbers (X+Y),
▪ Represent X and Y in binary format (2’s complement representation)

▪ add their n-bit representations,

▪ ignore the carry-out bit from the most significant bit (MSB) position.

▪ The sum will be the algebraically correct value in 2’s-complement representation if the actual result is in the
range −2n−1 through +2n−1 − 1.

▪ To subtract two numbers X and Y (X − Y),

▪ Represent X and Y in binary format (2’s complement representation)

▪ form the 2’s-complement of Y,

▪ add it to X using the add rule.

▪ The result will be the algebraically correct value in 2’s-complement representation if the actual result is in
the range −2n−1 through +2n−1 − 1.
62
2’S COMPLEMENT: SUBTRACTION
▪ -7- (-5)
-7→ 1001 - -7→ 1001 +
-5→ 1011 Becomes: 5→ 0101
-2→ 1110
▪ -7- (+1)
-7→ 1001 - -7→ 1001 +
+1→ 0001 Becomes: -1→ 1111
-8→ 1000

▪ +2- (-3)
+2→ 0010 - +2→ 0010 +
-3→ 1101 Becomes: +3→ 0011
+5→ 0101
63
2’S COMPLEMENT: SUBTRACTION
▪ -3- (-7)
-3→ 1101 - -3→ 1101 +
-7→ 1001 Becomes: 7→ 0111
+4→ 0100
▪ +2- (+4)
+2→ 0010 - +2→ 0010 +
+4→ 0100 Becomes: -4→ 1100
-2→ 1110

▪ +6- (+3)
+6→ 0110 - +6→ 0110 +
+3→ 0011 Becomes: -3→ 1101
+3→ 0011
64
SIGNED INTEGERS: ADDITION AND SUBTRACTION
▪ Sign and Magnitude:
▪ Undesired results

▪ 1’s Complement:
▪ The results are not always correct

▪ 2’s Complement:
▪ simplicity of adding and subtracting signed numbers
▪ used in modern computers

65
SIGN EXTENSION
▪ Represent a value given in a certain number of bits by
using a larger number of bits
▪ Positive numbers: zeroes are added to the left
▪ Negative numbers: ones are added to the left

▪ To convert a given (w)-bit, signed integer x to (w+k)-bit

integer with same value
▪ Make k copies of sign bit:
▪ X' = xw–1 ,…, xw–1 , xw–1 , xw–2 ,…, x0

66
SIGN EXTENSION: EXAMPLE

67
OVERFLOW IN INTEGER ARITHMETIC
▪ Arithmetic overflow:
▪ The actual result of an arithmetic operation is outside the representable range

▪ Overflow occurs when

▪ two positive numbers are added which results in a negative number or
▪ two negative numbers are added which results in a positive number

68
OVERFLOW IN INTEGER ARITHMETIC
▪ +7 + (+4)
carry: 0100
+7→ 0111 +
+4→ 0100
-5→ 1011
▪ -4 + (-6)
carry: 1000
-4→ 1100 +
-6→ 1010
+6→ 0110

▪ The value of the carry-out bit from the sign-bit position is not an
indicator of overflow
▪ Overflow occurs when carry-in to the high-order bit does not
equal carry out 69
OVERFLOW IN INTEGER ARITHMETIC
▪ +5 + (+3) ▪ +5 + (+2)
carry: 0111 carry: 0000
+5→ 0101 + +5→ 0101 +
+3→ 0011 +2→ 0010
-8→ 1000 +7→ 0111
Overflow No overflow

▪ -7 + (-2) ▪ -3 + (-5)
carry: 1000 carry: 1111
-7→ 1001 + -3→ 1101 +
-2→ 1110 -5→ 1011
+7→ 0111 -8→ 1000
Overflow No overflow

70
CHARACTER REPRESENTATION
▪ The most common encoding scheme for characters is ASCII
▪ Alphanumeric characters, operators, punctuation symbols, and control characters represented
using 7-bit codes
▪ 8-bit byte is used to represent and store a character
▪ The code occupies the low-order seven bits
▪ The high-order bit is usually set to 0

71
FLOATING-POINT NUMBERS
▪ The basic IEEE format is a 32-bit representation that comprises of
▪ a sign bit,
▪ 23 significant bits, and
▪ 8 bits for a signed exponent of the scale factor

▪ IEEE standard also defines a 64-bit representation to accommodate

▪ more significant bits, and
▪ more bits for the signed exponent, resulting in much higher precision and a much larger range of
values
▪ In general, a binary floating-point number can be represented by (2008 version of IEEE
Standard 754):
▪ a sign for the number
▪ some significant bits
▪ a signed scale factor exponent for an implied base of 2

72
TOPICS COVERED FROM
▪ Textbook 1:
▪ Chapter 1: 1.4.1, 1.4.2, 1.5

73
FLOATING-POINT NUMBERS

▪ A binary floating-point number is represented by (2008 version of IEEE Standard 754):

▪ a sign for the number
▪ some significant bits
▪ a signed scale factor exponent for an implied base of 2

74
IEEE STANDARD FLOATING-POINT FORMATS (32 BIT)
▪ The basic IEEE format is a 32-bit representation that comprises of
▪ a sign bit,
▪ 23 significant bits, and
▪ 8 bits for a signed exponent of the scale factor

75
IEEE STANDARD FLOATING-POINT FORMATS (32 BIT)
▪ Example:
▪ Sign bit: 0, hence +ve number
▪ Mantissa, M: 1.00101000000000000000000
▪ Exponential, E: E’-127, ➔(E’→001010002= 4010)
E: 40-127= -87,
E: 2-87

▪ Actual binary number:

▪ 0.0000000000000000000000000000000000000000000000000000000000000000000000000000000000
0000100101
▪ Corresponding decimal value:
▪ 0.0000000000000000000000000074720904942534238208598929703585511674646113533526659011
8408203125
▪ In the value represented, what about the digit found to the left side of the decimal point?
▪ always be equal to 1
▪ can be left out in IEEE floating-point representation
76
STEPS TO CONVERT 32-BIT REPRESENTATION TO DECIMAL.
1. Obtain the mantissa and rewrite the value as V=1.M
2. To obtain E
i. Convert E’ to its equivalent decimal value
ii. E= E’-127 ➔2E
3. Move point in V towards left or right based on E
i. Move right if +ve
ii. Move left if –ve
iii. Digits before point is the integral part and after is the fractional part.
4. Convert the integral part of binary to decimal equivalent
i. Multiply each digit separately from left side of point till the first digit by 20, 21, 22, … respectively.
ii. Find the sum of all the products obtained in step 1.i.
5. Convert the fractional part of binary to decimal equivalent
i. Divide each digit separately from right side of point till the end by 21, 22, 23, … respectively.
ii. Find the sum of all the products obtained in step 2.i.
6. Add both integral and fractional part to obtain decimal number.
77
32-BIT REPRESENTATION TO DECIMAL: EXAMPLE
▪ IEEE754 32-bit format: 0 10000001 01000110011001100110011
S E’ M
▪ S=0, hence +ve number
▪ E’= 100000012=12910
▪ E = E’-127 =129-127
E=2
▪ Value represented = 1. 01000110011001100110011 × 22
= 101.000110011001100110011
= 5 .1

78
DECIMAL TO 32-BIT REPRESENTATION
▪ 40.15625
▪ S=0, since it is a positive number
▪ Mantissa, M,
▪ 40➔ 1010002 0.15625➔ .001012
▪ =101000.001012 If point moved towards left, then +ve exponent else -ve exponent
▪ =1.0100000101 × 25 Ignore 1 before decimal point
▪ Therefore, M=01000001010000000000000 Fill the remaining positions in the right with zeroes
▪ Exponent, E’, in excess-127 representation:
▪ E’=E+127
▪ =5+127
▪ =132
▪ E’=100001002
▪ 32-bit representation:
▪ 0 10000100 01000001010000000000000

79
STEPS TO CONVERT DECIMAL TO 32-BIT REPRESENTATION
A. Sign bit, S:
i. If positive, the first bit will be a 0
ii. If negative, the first bit will be a 1.
B. Mantissa, M:
i. Divide the integral part by 2 to get its binary equivalent, I (remainder in bottom-up)
ii. Multiply the fractional part by 2 to get its binary equivalent, F (value before point in top-down)
iii. Represent it as I.F
iv. Adjust the point to obtain 1.M
v. M must be 23-bit long. Fill the remaining bits in vector with zeroes

80
STEPS TO CONVERT DECIMAL TO 32-BIT REPRESENTATION
C. Exponent, E’, in “Excess 127 form”:
i. Count the number of places the binary point needs to be moved until a single digit of 1 sits by itself on
the left side of the binary point.
a. Point moved towards left count is positive else it is negative.
ii. Add 127 to your result above.
a. 8-bit binary numbers can range from 0 to 255,
b. exponents in single precision format can range from -126 to +127, that is from 2-126 to 2127 or,
c. approximately, 10-38 to 1038 in size.
d. In “excess 127 form” negative exponents range from 0 to 126, and positive exponents range from 128 to 255.
e. 127 represents a power of zero.
iii. Translate the sum (which will always be a positive value after adding 127) into binary form.
iv. This should be represented using 8 bits, so zeros may be added to the left side to ensure a string length of
8 bits.
v. This 8-bit string represents the exponent.

81
DECIMAL TO 32-BIT REPRESENTATION
▪ Represent -0.09375 in IEEE754 format
▪ S=1, since it is a negative number
▪ Mantissa, M: 0.09375 to binary
▪ 0.09375 x 2 = 0.1875 0 (remember, read downwards)
▪ 0.1875 x 2 = 0.375 0
▪ 0.375 x 2 = 0.75 0
▪ 0.75 x 2 = 1.50 1
▪ 0.50 x 2 = 1.00 1
▪ = 0.000112
▪ =1.1 × 2-4 If point moved towards left, then +ve exponent else -ve exponent. Ignore 1 before point
▪ Therefore, M=10000000000000000000000 Fill the remaining positions in the right with zeroes
▪ Exponent, E’, in excess-127 representation:
▪ E’=E+127
▪ =-4+127
▪ =123
▪ E’=11110112= 01111011
▪ -0.09375 will be represented in IEEE754 format as
▪ 1 01111011 10000000000000000000000
82
IEEE STANDARD FLOATING-POINT FORMATS (64 BIT)
▪ IEEE standard also defines a 64-bit representation to accommodate
▪ more significant bits, and
▪ more bits for the signed exponent, resulting in much higher precision and a much larger range of
values
▪ The 11-bit excess-1023 exponent E’ has the
▪ range 1 ≤ E’ ≤ 2046 for normal values, with 0 and 2047 used to indicate special values,
▪ The actual exponent E is in the range −1022 ≤ E ≤ 1023
▪ providing scale factors of 2−1022 to 21023 (approximately 10±308)

83
SPECIAL VALUES: 32-BIT REPRESENTATION
Sl.No. E’ M Meaning

1. =0 =0 value 0 is represented

2. =255 =0 value ∞ is represented

3. =0 ≠0 denormal numbers are represented. Their value is ±0.M ×2−126.
There is no implied one to the left of the binary point, and M is
any nonzero 23-bit fraction
4. =255 ≠0 the value represented is called Not a Number (NaN).
A NaN represents the result of performing an invalid operation
such as 0/0 or √−1

86
EXCEPTIONS
▪ In conforming to the IEEE Standard, a processor must set exception flags if any of the following
conditions arise when performing operations
▪ underflow,
▪ overflow,
▪ divide by zero,
▪ Inexact: name for a result that requires rounding in order to be represented in one of the normal formats
▪ Invalid: exception occurs if operations such as 0/0 or √−1 are attempted

▪ When an exception occurs, the result is set to one of the special values.

87
ADDITION EXAMPLE- BINARY
▪ A=96.625 + B=12.125
▪ Step i: Convert A to binary representation
▪ 1100000.101 ➔After normalizing we get 1.100000101 X 26
▪ E’= 6+127=133 =10000101
▪ In IEEE 32-bit format: A= 01000010110000010100000…….

▪ Step ii: Convert B to binary representation

▪ 1100.001 ➔After normalizing we get 1.100001 X 23
▪ E’= 3+127=130 = 10000010
▪ In IEEE 32-bit format: B= 01000001010000100000……

▪ Step 1: Choose the number with the smaller exponent and shift its mantissa right a number of steps
equal to the difference in exponents (Shift point to left).
▪ Shift the mantissa of smaller number, B, to the right by 3 bits we get
▪ 1.10000100000 ---Original mantissa (with hidden bit considered)
▪ 0.11000010000 ---shifting by 1 bit
▪ 0.011000010000 ---shifting by 2 bits
▪ 0.001100001000 ---shifting by 3 bits
88
ADDITION EXAMPLE- BINARY
▪ Step 2:
▪ Set the exponent of the result equal to the larger exponent
▪ 10000101 (exponent of A)

▪ Step 3:
▪ Perform addition on the mantissas and determine the sign of the result
1.100000101000000 +
0.001100001000000
1.101100110000000
▪ Step 4:
▪ Normalize the resulting value, if necessary
▪ Result is already normalized

▪ In 32-bit format: 0 10000101 101100110000

▪ which is 108.75 in decimal

89
ADD/SUBTRACT RULE
1. Choose the number with the smaller exponent
2. Shift its mantissa right to the number of steps equal to the difference in exponents. (Shift point to
left)
3. Set the exponent of the result equal to the larger exponent.
4. Perform addition/subtraction on the mantissas and determine the sign of the result.
5. Normalize the resulting value, if necessary.

90
ADDITION EXAMPLE- BINARY
▪ 0.25 = 0 01111101 00000000000000000000000 + 100 = 0 10000101 10010000000000000000000
▪ Step 1: align radix points
▪ shifting the mantissa LEFT by 1 bit DECREASES THE EXPONENT by 1 and RIGHT by 1 INCREASES THE
EXPONENT by 1
▪ we want to shift the mantissa right, because the bits that fall off the end should come from the least significant end
of the mantissa
▪ choose to shift the .25, since we want to increase it's exponent.
▪ shift by 10000101
-01111101
00001000 (8) places.
00000000000000000000000 (original value)
10000000000000000000000 (shifted 1 place) (note that hidden bit is shifted into msb of mantissa)
01000000000000000000000 (shifted 2 places)
00100000000000000000000 (shifted 3 places)
0010000000000000000000 (shifted 4 places)
00001000000000000000000 (shifted 5 places)
00000100000000000000000 (shifted 6 places)
00000010000000000000000 (shifted 7 places)
00000001000000000000000 (shifted 8 places)
91
ADDITION EXAMPLE- BINARY
▪ Step 2: add (don't forget the hidden bit for the 100)
1.10010000000000000000000 (100) +
0.00000001000000000000000 (.25)
1.10010001000000000000000
▪ Step 3: normalize the result (get the "hidden bit" to be a 1)
▪ Result is already normalized

▪ In 32-bit format: 0 10000101 10010001000000000000000

92
SUBTRACTION EXAMPLE- BINARY
▪ A=96.625 - B=12.125
▪ Convert A to binary representation
▪ 1100000.101 ➔After normalizing we get 1.100000101 X 26
▪ E’= 6+127=133 =10000101
▪ In IEEE 32-bit format: 01000010110000010100000…….

▪ Convert B to binary representation

▪ 1100.001 ➔After normalizing we get 1.100001 X 23
▪ E’= 3+127=130 = 10000010
▪ In IEEE 32-bit format: 01000001010000100000……

▪ Step 1:
▪ Choose the number with the smaller exponent and shift its mantissa right a number of steps equal to the
difference in exponents.
▪ A=0 10000101 10000010100000……. B=0 10000010 10000100000……
▪ Shift the mantissa of smaller number, B, to the right by 3 bits we get
▪ 1.10000100000 ---Original mantissa (with hidden bit considered)
▪ 0.11000010000 ---shifting by 1 bit
▪ 0.011000010000 ---shifting by 2 bits
▪ 0.001100001000 ---shifting by 3 bits
93
SUBTRACTION EXAMPLE- BINARY
▪ Step 2:
▪ Set the exponent of the result equal to the larger exponent
▪ 10000101 (exponent of A)

▪ Step 3:
▪ Perform subtraction on the mantissas and determine the sign of the result
1.10000010100000 -
0.00110000100000
1.01010010000000
▪ Step 4:
▪ Normalize the resulting value, if necessary
▪ Result is already normalized

▪ In 32-bit format: 0 10000101 010100100000000

▪ which is 84.5 in decimal

94
SUBTRACTION EXAMPLE- BINARY
▪ 0.25 = 0 01111101 00000000000000000000000 + 100 = 0 10000101 10010000000000000000000
▪ Step 1: align radix points
▪ shifting the mantissa LEFT by 1 bit DECREASES THE EXPONENT by 1 and RIGHT by 1 INCREASES THE
EXPONENT by 1
▪ we want to shift the mantissa right, because the bits that fall off the end should come from the least significant end
of the mantissa
▪ choose to shift the .25, since we want to increase it's exponent.
▪ shift by 10000101
-01111101
00001000 (8) places.
00000000000000000000000 (original value)
10000000000000000000000 (shifted 1 place) (note that hidden bit is shifted into msb of mantissa)
01000000000000000000000 (shifted 2 places)
00100000000000000000000 (shifted 3 places)
0010000000000000000000 (shifted 4 places)
00001000000000000000000 (shifted 5 places)
00000100000000000000000 (shifted 6 places)
00000010000000000000000 (shifted 7 places)
00000001000000000000000 (shifted 8 places)
95
SUBTRACTION EXAMPLE- BINARY
▪ Step 2: add (don't forget the hidden bit for the 100)
1.10010000000000000000000 (100) -
0.00000001000000000000000 (.25)
1.10001111000000000000000
▪ Step 3: normalize the result (get the "hidden bit" to be a 1)
▪ Result is already normalized

▪ In 32-bit format: 0 10000101 10001111000000000000000

133 1.10001111000000000000000
133-127=6
=1.10001111000000000000000 X 26
=1100011.11000000000000000
= 99.75
96
MULTIPLY AND DIVIDE RULE
▪ Multiply Rule
A. Add the exponents and subtract 127 to maintain the excess-127 representation.
B. Multiply the mantissas and determine the sign of the result.
C. Normalize the resulting value, if necessary.

▪ Divide Rule
A. Subtract the exponents and add 127 to maintain the excess-127 representation.
B. Divide the mantissas and determine the sign of the result.
C. Normalize the resulting value, if necessary.

97
TOPICS COVERED FROM
▪ Textbook 1:
▪ Chapter 1: 1.4.2,
▪ Chapter 9: 9.7, 9.7.1

98
ADDITION EXAMPLE- BINARY
▪ A=15.5 + B=15.5
▪ Step i: Convert A to binary representation
▪ 1111.1 ➔After normalizing we get 1.1111 X 23
▪ E’= 3+127=130 =10000010
▪ In IEEE 32-bit format: A= 01000001011110000000000000000000

▪ Step ii: Convert B to binary representation

▪ 1111.1 ➔After normalizing we get 1.1111 X 23
▪ E’= 3+127=130 =10000010
▪ In IEEE 32-bit format: B= 01000001011110000000000000000000

▪ Step 1: Choose the number with the smaller exponent and shift its mantissa right a number of steps
equal to the difference in exponents.
▪ Both are of equal exponent. Hence no shift

▪ Step 2:
▪ Set the exponent of the result equal to the larger exponent
▪ 10000010 (exponent of A or B) 99
ADDITION EXAMPLE- BINARY
▪ Step 3:
▪ Perform addition on the mantissas and determine the sign of the result
1.11110000000000000000000 +
1.11110000000000000000000
11.11100000000000000000000
▪ Step 4:
▪ Normalize the resulting value, if necessary
▪ 1.111100000000000000000000 × 21
▪ Adjust resultant exponent E’ by adding exponent from the normalized resultant mantissa
10000010 + (if the exponent is –ve, subtract it from resultant E’)
00000001
10000011
▪ In 32-bit format: 0 10000011 111100000000000000000000
▪ which is 31.0 in decimal
100
MULTIPLY AND DIVIDE RULE
▪ Multiply Rule
A. Add the exponents and subtract 127 to maintain the excess-127 representation.
B. Multiply the mantissas and determine the sign of the result.
C. Normalize the resulting value, if necessary.

▪ Divide Rule
A. Subtract the exponents and add 127 to maintain the excess-127 representation.
B. Divide the mantissas and determine the sign of the result.
C. Normalize the resulting value, if necessary.

101
MULTIPLICATION EXAMPLE- BINARY
▪ A= 0 10000100 0100 × B= 1 00111100 1100

▪ Step 1: add exponents and subtract 127

▪ 132+60-127=65. and unsigned representation for 65 is 01000001.
▪ Step 2: Multiply the mantissa. Don't forget hidden bit
1.0100 x 1.1100
00000
00000
10100
10100
10100
1000110000 becomes 10.00110000
normalize the result:
1.000110000 X 21
Step 3: Adjust the exponent : 65+1=66 = 01000010

1 01000010 000110000
102
MULTIPLICATION EXAMPLE- BINARY
▪ A=96.625 × B=12.125 1.100000101 x 1.100001
▪ Step i: Convert A to binary representation 1100000101
▪ 1100000.101 ➔After normalizing 1.100000101 X 26
0000000000
0000000000
▪ E’= 6+127=133 =10000101
0000000000
▪ In IEEE 32-bit format: A= 0 10000101 10000010100000…….
0000000000
▪ Step ii: Convert B to binary representation 1100000101
▪ 1100.001 ➔After normalizing 1.100001 X 23 1100000101 ,
▪ E’= 3+127=130 = 10000010 10010010011100101
▪ In IEEE 32-bit format: B= 0 10000010 10000100000……
➔10.010010011100101
▪ Step 1: add exponents and subtract 127
▪ 133+130-127=136 ➔ 10001000 (unsigned representation) ▪ Step 3: Adjust the exponent:
▪ 136+1=137➔ 10001001

▪ Step 2: Multiply the mantissa ▪ 32-bit representation:

▪ 0 10001001 0010010011100101
1.100000101 x 1.100001= 10.010010011100101
▪ = 1.0010010011100101 X 210
▪ =10010010011.100101
After normalizing 1.0010010011100101 X 21
▪ =1024+128+16+2+1+ 0.5+.0625+.015625
▪ =1171.578125 103
DIVISION EXAMPLE- BINARY
▪ A= 127.03125 ÷ B= 16.9375 1.1 1 1____________
▪ Step i: Convert A to binary representation 1.00001111| 1.1 1 1 1 1 1 0 0 0 0 1
▪ 1111111.00001 ➔After normalizing 1.11111100001 X 26
▪ E’= 6+127=133 =10000101
1.0 0 0 0 1 1 1 1
▪ In IEEE 32-bit format: A= 0 10000101 11111100001…… 0111011010
▪ Step ii: Convert B to binary representation 100001111
▪ 10000.1111 ➔After normalizing 1.00001111 X 24 0110010110
▪ E’= 4+127=131 = 10000011 100001111
▪ In IEEE 32-bit format: B= 0 10000011 00001111000……
0100001111
▪ Step 1: subtract exponents and add 127 100001111
▪ 133-131+127=129 ➔ 10000001 (unsigned representation) 000000000
▪ Step 2: Divide the mantissa
1.11111100001 ÷ 1.00001111= 1.111
The result is already normalized.
▪ The result in IEEE 32-bit format:
0 10000001 11100000000…….
104
DIVISION EXAMPLE- BINARY
▪ A= 97.0 ÷ B= 12.125 1.0______
▪ Step i: Convert A to binary representation 1.100001 | 1.100001
▪ 1100001.0 ➔After normalizing 1.100001 X 26
▪ E’= 6+127=133 =10000101
1.100001
▪ In IEEE 32-bit format: A= 0 10000101 10000100…… 0000000
▪ Step ii: Convert B to binary representation
▪ 1100.001 ➔After normalizing 1.100001 X 23
▪ E’= 3+127=130 = 10000010
▪ In IEEE 32-bit format: B= 0 10000010 10000100000……

▪ Step 1: subtract exponents and add 127

▪ 133-130+127=130 ➔ 10000010 (unsigned representation)

▪ Step 2: Divide the mantissa: 1.100001 ÷ 1.100001= 1.0

The result is already normalized.

▪ The result in IEEE 32-bit format:
0 10000010 00000000000…….
i.e.,1.0 X23 = 1000 =8 in decimal 105
GUARD BITS AND TRUNCATION
▪ Mantissas of initial operands and final results are limited to 24 bits, including the

implicit leading 1
▪ To attain maximum accuracy in the final results it is important to retain extra bits,

often called guard bits, during the intermediate steps.

▪ Removing guard bits in generating a final result requires that the extended

mantissa be truncated to create a 24-bit number that approximates the longer

version.

106
WAYS OF TRUNCATION: CHOPPING
▪ Remove the guard bits and make no changes in the retained bits
▪ e.g. To truncate from 6 bits to 3 bits:

▪ 0.b−1b−2b−3000 to 0.b−1b−2b−3111 are truncated to 0.b−1b−2b−3

▪ The error in the 3-bit result ranges from 0 to 0.000111

▪ The error in chopping, ranges from 0 to almost 1 in the least significant position of

the retained bits.

▪ In the example above, it is b−3 position. The result of chopping is a biased

approximation because the error range is not symmetrical about 0

107
WAYS OF TRUNCATION: VON NEUMANN ROUNDING
▪ If the bits to be removed are all 0s,
▪ they are simply dropped, with no changes to the retained bits.

▪ If any of the bits to be removed are 1,

▪ the least significant bit of the retained bits is set to 1

▪ All 6-bit fractions where b−4b−5b−6 ≠ 000 are truncated to 0.b−1b−21

▪ The error in this truncation method ranges between −1 and +1 in the LSB position

of the retained bits

▪ approximation is unbiased because the error range is symmetrical about 0.

▪ When three guard bits are used, the value 0.001100 is truncated to 0.001

108
WAYS OF TRUNCATION: VON NEUMANN ROUNDING
▪ 0.001 00000 → 0.001 (truncate. 0 error)

▪ 0.001 11111 → 0.001 (but the value is near 0.010, hence -1 error at LSB position of retaining bits)

▪ 0.010 11111 → 0.011 (almost nearest value. Almost 0 error)

▪ 0.010 00001 → 0.011 (+1 error)

109
WAYS OF TRUNCATION: ROUNDING
▪ Achieves the closest approximation to the number being truncated and is an unbiased
technique.
▪ A 1 is added to the LSB position of the bits to be retained if there is a 1 in the MSB position of
the bits being removed. Thus,
▪ 0.b−1b−2b−31. . . is rounded to 0.b−1b−2b−3 + 0.001
▪ 0.b−1b−2b−30. . . is rounded to 0.b−1b−2b−3.

▪ Except for the case in which the bits to be removed are 10 . . . 0.

▪ This is a tie situation; the longer value is halfway between the two closest truncated representations.

▪ To break the tie

▪ choose the retained bits to be the nearest even number
▪ the value 0.b−1b−20100 is truncated to 0.b−1b−20
▪ the value 0.b−1b−21100 is truncated to 0.b−1b−21 + 0.001.

▪ Also termed as “round to the nearest number or nearest even number in case of a tie”
▪ The error range is approximately −1/2 to +1/2 in the LSB position of the retained bits. 110
WAYS OF TRUNCATION: ROUNDING
▪ Best method
▪ But most difficult to implement because it requires an addition operation and a possible
renormalization.
▪ This rounding technique is the default mode for truncation specified in the IEEE floating-point
standard
▪ When three guard bits are used, using Rounding procedure, the value 0.001100 is truncated to
0.010
▪ Similarly,
i. 0.111 011=0.111
ii. 0.110 011=0.110
iii. 0.111 101=0.111+0.001=1.000
iv. 0.111 100=0.111+0.001=1.000
v. 0.110 100=0.110
111
vi. 0.101 100=0.101+0.001=0.110
IMPLEMENTING ROUNDING
▪ Requires only three guard bits to be carried along during the intermediate steps in performing
an operation.
▪ The first two of these bits are the two most significant bits of the section of the mantissa to be
removed.
▪ The third bit is the logical OR of all bits beyond these first two bits in the full representation of
the mantissa.
▪ It should be initialized to 0.
▪ If a 1 is shifted out through this position while aligning mantissas, the bit becomes 1 and retains
that value; hence, it is usually called the sticky bit.

112
TOPICS COVERED FROM
▪ Textbook 1:
▪ Chapter 9: 9.7.1, 9.7.2

113