ITCS 321 Test TWO DEC 2018 KEY
ITCS 321 Test TWO DEC 2018 KEY
ITCS 321 Test TWO DEC 2018 KEY
QUESTION # 1 2 3 4 5 TOTAL
MAX POINTS 14 15 16 16 12 73
POINTS EARNED
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UNIVERSITY OF BAHRAIN COLLEGE OF INFORMATION TECHNOLOGY
DEPARTMENT OF COMPUTER SCIENCE
ITCS 321: COMPUTER ORGAIZATION AND ASSEMBLY LANGUAGE
SECOND TEST FIRST SEMESTER 2018/2019 DATE: DEC 25, 2018
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QUESTION ONE {14 pts}
1) In returning from a function, the callee performs the two following actions:
Puts the results in a place that can be accessed by the caller
Transfers control to the caller, to the instruction immediately
following the call.
2) The MIPS instruction jalr $t2, $t4 performs the two following actions:
Saves the address of the next instruction in $t2 = PC+4
Calls the function whose address is in $t4
Carefully study the following MIPS code and answer all questions below.
Address MIPS Instructions Assembly Language
1) 00400040 lui $1, 0x1001 la $a0, arr
2) 00400044 ori $4, $1, 0
3) 00400048 ori $5, $0, 20 ori $a1,$0,10
4) 0040004C jal 0x10001a jal wyst
5) 00400040 . . .
6) wyst:
7) 00400068 sll $8, $5, 2 sll $t0, $a1, 2
8) 0040006C add $8, $8, $4 add $t0, $t0, $a0
9) 00400070 lw $9, 0($8) lw $t1, 0($t0)
10) 00400074 lw $10,4($8) lw $t2, 4($t0)
11) 00400078 sw $10,0($8) sw $t2, 0($t0)
12) 0040007C sw $9, 4($8) sw $t1, 4($t0)
13) 00400080 jr $31 jr $ra
a) Briefly explain (write one sentence only) what the function wyst do.
It swaps element #20 with element #21 in the array named arr
b) What will be in PC register after the instruction at line #4 is fetched (not executed yet)?
PC = 0x00400040
c) Executing the instruction at line #4 changes the value of $ra to 0x00400040
d) What will be in PC register after executing the instruction at line #4? PC = 0x00400068
e) What will be in PC register after executing the instruction at line #13? PC = 0x00400040
2) Briefly explain (write one sentence only) when the stack frame is created and when is deleted.
A stack frame is created whenever a function is called and deleted
whenever a function is exited.
3) What is the RTL description of the BEQ instruction?
if (Reg(rs) == Reg(rt)) PC ← PC + 4 + 4 × sign_ext(offset16)
else PC ← PC + 4
4) Suppose that floating-point square root FSQRT is responsible for 30% of the execution time of some
application and all floating-point FP instructions (ALLFP) are responsible for 72%. To improve the
performance of this application, the developers asked you to help them select the best of the following
two choices:
a) First choice is to speedup FSQRT by a factor of 12
b) Second choice: execute ALLFP instructions 2x faster.
5) A new compiler is being tested a 3 GHz machine with three different classes of instructions: class A
requires 2 cycles, class B requires 3 cycles, and class C requires 1 cycle. For a benchmark program the
compiler produces 4 billion class A instructions, 2 billion class B instructions, and 3 billion class C
instructions. Calculate the MIPS of the new compiler.
Given a static array arr .word 10, 20, ... consisting of 80 values. Write a
complete MIPS program that defines and calls a recursive function rec_sum to
calculate the sum of arr elements, and then prints the calculated sum with proper
message: The sum of array elements = xxxx.
int rec_sum (int A[], int n)
.data {
arr: .word 10,20,30,40,50,60,-90,-60, … if (n == 0) return 0;
mes: .asciiz "The sum of array = " if (n == 1) return A[0];
.text int sum = rec_sum (&A[0], n);
.globl main return sum;
main: li $v0, 4 # print string }
la $a0, mes
syscall
la $a0, arr
li $a1, 80 # array size n = 80
jal rec_sum
li $v0, 10 # exit
syscall
lw $t1, 0($s0)
add $v0, $v0, $t1 # $v0 = $v0 + A[i]
lw $ra, 0($sp) # restore $ra
lw $s0, 4($sp) # restore $s0
lw $s1, 8($sp) # restore $s1
addiu $sp, $sp, 12 # free stack frame
jr $ra # return to caller
Given a datapath with the following delay times: instruction memory access time = 500 ps, data
memory access time = 500 ps, instruction decode and register read = 300 ps, register write = 200 ps,
ALU delay = 300 ps. Ignore the other delays in the multiplexers, wires, etc. Assume the following
instruction mix: 35% ALU, 20% load, 10% store, 25% branch, and 10% jump.
a) [5 pts] Use the following table to compute the length (delay) for each instruction class for the
single-cycle datapath.
Instruction Instruction Decode & Data Write Total
ALU
Class Memory Reg Read Memory Back Delay
ALU 500 300 300 200 1300
Load 500 300 300 500 200 1800
Store 500 300 300 500 1600
e) [2 pts] What is the speedup factor of the multi-cycle over the single-cycle processor?
(Multi-cycle is slower)
f) [2 pts] What is the speedup factor of the pipelined over the single-cycle processor?
Write the if statement that defines the value of the PCSrc controlling the PC MUX and draw the
logic diagram for the PC register control logic.
if (Op == J)
PCSrc = 1;
else
if ( (Op == BEQ && Zero == 1) || (Op == BNE && Zero == 0) )
PCSrc = 2;
else
PCSrc = 0;
Op
Decoder
BEQ BNE
Zero J
Branch Jump
.. Upper
16 bits
.
ExtOp
.. Lower
Imm16
16 bits
.
Exit Program 10
Print Char 11 $a0 = character to print
Read Char 12 Return character read in $v0