Generating ASIC Test Vectors with Verilog

Clifford E. Cummings

Tcktronix, Inc., P.O. Box 500, MS/47-623 Beaverton, OR 97077

,4bst ract 2. Test vectors with relative timing

Compiling a design verification test suite is a non-trivi- Generation of test vectors with relative timing is gener-
a1 task. Creating that test suite to satisfy an ASIC vendor ally well understood by most users of the Verilog language.
can be even more diSJicurt.An awareness of existing Verilog This is perhaps the most commonly taught stimulus genera-
HDL capabilities may assist design engineers in the cre- tion method in Verilog classes.
ation of ASIC test vectors to satis& ASIC-vendor vector This method employs one or more initial procedural
requirements. This paper outlines simple Verilog tech- blocks with sequential lists of constant-delay vectors sur-
niques which demonstrate Verilog’spower not only for de- rounded by begin - end key words.
scribing hardware, but for creating ASIC test vectors.
3. Test vectors with absolute timing

1. Introduction In some cases it may be easier to create certain test

conditions by using test vectors with absolute timing. This
Experienced Design Engineers are accustomed to writ- is just as easy to do, but may not be as well known.
ing 1’s & 0’spatterns to meet vendor requirements for test- This method employs one or more initial procedural
ing ASIC designs. It is not unusual to spend almost as much blocks with vectors surrounded by fork -join key words,
time generating and checking test patterns as it is to do the each vector is preceded with an absolute delay number,
actual ASIC logic design 111. specifying the time at which the vector should be executed.
To alleviate the tedious and error prone task of generat- These two methods for generating test vectors are the
ing large files of binary test vectors, engineers have devel- most simplistic in nature, and offer only a minimal advan-
oped programs to help automate and document the test vec- tage over the usual generation of 1’s & 0’sby any other sim-
tor generation process [2][3]. ulation language; the advantage is that they are written in
Verilog vendors may be neglecting to inform design en- the same language used to describe the design hardware,
gineers of a strong motivation for using Verilog HDI,; that Verilog.
motivation is that the same language engineers are accus- Note: With Verilog, it is possible to mix relative-timed
tomed to using for doing hardware designs, is also a power- (begin-end) and absolute-timed (fork-join) vectors in the
ful tool for test vector generation. same, or in parallel initial blocks; thus, triggering a critical
Verilog training tends to focus on simple initial-block, signal at an absolute time does not preclude the use of rela-
relativetiming-pattem test generation without exposing tively-timed vectors for the rest of a testcase.
the student-cngineer to advanced test generation possibili- A simple Data Acquisition ASIC behavioral model with
ties available by using Verilog HDL. behavioral test and ASIC vector-file generation code is in-
As a stand-alone language, Verilog HDL is a powerful cluded on the last six pages of this paper (acqasic.v: Fig-
test vector generation tool. This paper will outline a few ures 5-10). This simple ASIC is a working model and will
simple techniques for creating test vectors, including a be referenced in the next two sections to point out more ad-
semi-automated procedure for generating ASIC vendor vanced ASIC test vector generation techniques using Veri-
compliant test vector files. log.

63
0-8186-5455-7194 $03.000 1994 IEEE
4. Print-on-change value comparison”[l 1. The Verilog $fstrobe command can
be executed at two separate, but fixed intervals to generate
Some ASIC Vendors require hard copy ”Print-On- both of these files.
Change” output, for specific tests[4]. The sequence of commands in Figure8 (starting at label
The Verilog $monitor command provides a ”Print-On- L) call functions and tasks to create the ”Strobed-Input”
Change” output, while the $fmonitor command will send file. ‘The code starts by calling the OpenFile function from
”Print-Onxhange” output to an ASCII tile. Figure9 (label N) to open a file called ”input.vec”, uses the
The code in Figures 8-10 (starting at label J) becomes predefined, ASIC-vendor specific header from the
Printf-header task, case lYPE=O (label 0), to print the
active whenever +define+tekasic is added to the Verilog
vector-column header, calls the Printf-vector, case
command line.
The sequence of commands in Figure 8 (starting at label TYPE=O (Figure 10 - label Q) task to strobe the input state
K) create the ”Print-On-Change” file. The code starts by
at time 0, then uses a forever ... Printf-vector call to strobe
calling the OpenFile function from Figure 9 (label N) to the ASIC input state at fixed intervals #(‘cycle) (every
open a file called ”change.vec”, uses the predefined,
-
lOOns in this example, Figure 5 label A) to the ”in-
ASIC-vendor specific header from the Printf-header put.vec” vector file.
task, case TYPE=l (label 0), to print the vector-column
header, then monitors the ASIC I/O signals to produce an The ”input.vec” output for multiple writes to the sample
AS IC-style ”Print-On-Change” file. ASIC are shown below in Figure 3.
The ”change.vec” output for multiple writes to the sam-
ple ASIC are shown below in Figure 2.
AAAAAAAAAAAAAAADDDDDDDDADR
AAAAAAAAAAAAAAADDDDDDDDADR CCCCCCCCCDDDDDDAAAALUASS-
CCCCCCCCCDDDDDDAAAAAAAASS_ QQQQQQQQQDDDDDDTTTTTTTT W
QQQQQQQQQDDDDDDTTTTTTTT W RRRRRRAAAALUA N
RRRRRRAAAAAAAA N DDDDDDDDCBBBBBBBBBBBBBB
DDDDDDDDCBBBBBBBBBBBBBB MAAAAAAIJ-
A A A A A A A A L W - TTTTTTTTKSSSSSSSSSSSSSS
TTTTTTTTKSSSSSSSSSSSSSS AAAAAAAA
AAAAAAAA 76543210 54321076543210
76543210 54321076543210 Ons oooooooooxxxxxxxxxxxxxxxxx
Ons OOOOOOOOOxxxxxxxxxxxxxxxxx 10Ons 00000000010000000000001010
50ns 00000000110000000000001000 20011s 00000001010000000000010010
lOOns 00000000010000000000001010 300ns 00000010022222222222222111
12511s OOOOOOOOOzzzzzzzzzzzzzzlll 400ns 0000001102z222222222222111
150x1s 00000000110000000000010000 50Ons 0000010002222222z222222111
200x1s 00000001010000000000010010 ...
...
Figure 3. “input.vec” file
Figure 2. “change.vec” file

The sequence of commands in Figure9 (starting at label

5. Strobed vectors at fixed intervals M) call functions and tasks to create the ”Strobed-I/O’ file.
The code starts by calling the OpenFile function (label N)
It is not unusual for an ASIC vendor[4] to ask for two to open a file called ”io.vec”, uses the predefined, ASIC-
additional sets of test vectors: vendor specific header from the Printf-header task, case
(1) 1’s & 0’s input patterns (“Strobed-Input” file). TYPE=l (label 0),to print the vector-column header, calls
the Printf-vector, case TYPE=I (Figure 10 -label Q) task
(2) 1’s & 0’s inputs, outputs, and enable signals for bi- to strobe the I/O state at time #(‘cycle - 1) (9911sin the ex-
directional I/O’s, strobed, just before the next ac- ample), then uses a forever ... Printf-vector call to strobe
tive clock edge (“Strobed-I/O’ file). the ASIC I/O state at fixed intervals #(‘cycle) (every 10011s
Comparing expected circuit outputs to the contents of a in this example, Figure 5 - label A) to the ”io.vec” vector
”Strobed-I/O file” is also referred to as ”cycle-by-cycle file.

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 The ”io.vec” output for multiple writes to the ASIC are 6. Conclusions
shown below in Figure 4.
A single language for behavioral modeling, circuit de-
sign, behavioral testing, ASIC test vector generation, de-
AkAAAAAAAAAAAAADDDDDDDDADR
sign debug, as well as synthesis of FPGAs, ASICs and
CCCCCCCCCDDDDDDAAAAAAAASS_
board designs is highly desirable, and the ability to use a
QQQQQQQQQDDDDDDTTTTTTTT W
common syntax for all of these activities promotes tool-
~- RRRRRRAAAAAAkA N usage expertise. Instead of using and forgetting new vector
DDDDDDDDCBBBBBBBBBBBBBB generation languages or vendor-dependent waveform
AAAAAAAALUtTUUUUlTUUUUUUU stimulus-sketching tools during the development process,
TTTTTTTTKSSSSSSSSSSSSSS design engineers could master a single language; thereby
AAAAAAAA developing greater efficiency and productivity with the
76543210 54321076543210 chosen tool set. Verilog HDI, is just such a language.
99ns 00000000110000000000001000
199ns 00000000110000000000010000 7. References
29911s 00000001122222222222222111
399ns 00000010122222222222222111
[ l ] L. Saunders and Y. Trivedi, ”Beyond Modeling...,”
499x1s 000000111222zz222222zzz111
ASIC & EDA, September 1993, pp. 28-33.
599ns 0000010012222222222z2zz111
. . . [2] W. R. Huttel, ”MTV (Macro Test Vector) Processor
Definition,” Technical Report No. 4, Computer Aided
Figure 4. “io.vec” file
Test Group, CAE Systems Division, Tektronix, Inc.,
January 21,1988.
131 D. McKinney, ”VGP, A language to aid in the creation
Once the ASIC file vector generation code is complete, and documentation of test vectors,” Advance Devel-
multiple tasks to define complex series of signal transitions opment Group Instrument Division, July 20, 1988.
can be written, to allow efficient, simple, easy to under-
stand test cases (Figure 6 - labels G, H & I, and Figure 5 - [ 41 ”MacroMatrix Design Manual, Volume 11”, Applied
label B). Micro Circuits Corporation, 1990, Section 4:Simula-
While these vector generation tasks are being executed, tion Rules, Vector Submission Rules and Guidelines.
if the +define+tekasic Verilog command switch is in-
[5] C.E. Cummings, ”Synthesizing ASIC Vectors with
voked, a binary pattem of 1’s and 0’s will automatically be
Verilog”, International Cadence User Group Confer-
written to three separate files: the ”Print-On-Change”,
ence Proceedings, August 1993, pp. SD22-SD30.
”Strobed-Input” and ”Strobed-I/O” files. Whenever the
+define+tekasic switch is not used, simulation runs faster
by ignoring the file I/O operations.
/I This File: acqasic.v
‘timescale 1ns / 1ns
‘define cycle 100 Global clock cycle definition I
‘define STOP-ACQ wr-reg(8’hO)
‘define RESET-ALL w r-reg(8’h 1)
‘define START-ACQ wr_reg(8’h2) Test command name definitions
‘define ACQUIRE.-DATA-CYCLE B(posedge acq-clk)
‘define READ-ACQ-MEMO RY rd-mem
module test;
reg [7:0] acq-data, datareg, i;
reg [5:0] addrbus;
reg acq-clk, as, ds, r-wn;
Figure 5. File: acqasic.v - Test Code: Test Definitions
wire [7:0] databus = (r-wn ? 8’bz : datareg );

65
always begin @ I/ acq-data triangle wave input

endtask
Figure 6. File: acqasic.v (cont.) - Test Code: Register Write
endmodule
and Acquisition Memory Read Tasks

66
// DATA ACQUISITION ASIC
module acqasic(acq-data, acq-clk, addrbus, databus, as, ds, r-wn);
input [7:0] acq-data; /I external acquisition data
input acq-clk; /I free-running ext acquisition clk
input [5:0] addrbus; // lxxxxx reg / Oxxxxx acqmem
inout [7:0] databus; // Processor data bus
input as, ds, r.-wn; I/ addr strb, data strb, rd(H)/wr(L)
reg [31:O] fanout, pipe; N acquisition fanout and pipe regs
reg [31:O] acqmem [0:7]; /I slower acquisition RAM
reg [3:0] fo-clk; N fanout clk (johnson counter)
integer memaddr; /I acquisition RAM addr
reg reset, acqen; N Reset and Acquisition Enable FF‘s
reg [3:0] addr-.reg; /I ASIC Address register
wire rdRAM;
reg [31 :O] ramdata; /I temporary readback register
reg [7:0] muxdata; /I sliced readback register

always @(reset)begin // Reset Block

case (reset)
l ’ b l : begin
assign pipe = 32’bO;
assign fo-clk = 4’blOOO;
assign fanout = 32’bO;
assign memaddr = 0;
end
1’bo : begin
deassign pipe;
deassign fo-clk;
deassign fanout;
deassign memaddr;
end
endcase
end

always Q(posedge acq-clk) if (acqen) .J-Clk = {fo_clk[2:(

always @(fo-clk) begin // Data Acquisition Pipeline

case (fo-clk)
4’bOOOl : begin
acqmem[memaddr] = pipe;
pipe = fanout;
fanout[31:24] = acq-data;
memaddr = (memaddr + 1) % 8; // Counts 0-7
end
4’bOOlO : fanout[23:16] = acq-data;
4’bOlOO : fanout[l5: 81 = acq-data;
4’blOOO : fanout[ 7: 01 = acq-data;
endcase
end

Figure 7. File: acqasic.v (cont.) - Data Acquisition ASIC Behavioral Model

67
always Q(negedge as) begin // Latch Address
addr-reg = addrbus;
end

always 8 (acqmem[addrbus[4:2]]) begin //to split 32-bit data

ramdata = acqmem[addrbus[4:2]];
if (rdRAM) case (addrbus[l:O])
2’bOO : muxdata = ramdata[31:24];
2’bOl : muxdata = ramdata[23:16];
2’blO : muxdata = ramdata[l5:81;
default: muxdata = ramdata[7:0];
endcase
end

assign rdRAM = (!addrbus[5] && !as && r-wn); // Read RAM Qualifier
assign databus = (rdRAM ? muxdata : 8’bz); // Bi-Dir Data Bus

always Q (posedge ds) // Strobe Data Control Bits

if (!r-wn && addrbus[5]) begin
reset = databus[O];
acqen = databus[l];
end // end of DATA ACQUISITION ASIC code

integer input-f, and run when the +define+tekasic Verilog

Figure 8. File: acqasic.v (cont.) - Data Acquisition ASIC Behavioral Model (cont.)
and ASIC Vector File Code

68
 @I I
~~

initial begin // PRINT-VO-VECTORS COMMANDS

io-f = OpenFile(”io.vec”); I/ Open Vector File
Printf-header(i0-f,l ); // Print U 0 Header
#(‘cycle - 1) // 1st I/O Vector Delay
Prinff-vector( io-f,l ); // Print 1st Vector
forever #(‘cycle)
Printf-vect or(io-f ,1); // Print other Vectors
end
function integer OpenFile; +0I // ODen files / reDort errors
input [256:0] FileName; // [256:0] - 32 ASCII chars
begin
OpenFile = $fopen(FileName);
if(OpenFile==O) begin
$display(”\n*** Could not open %Os file ***\n”, FileName);
$finish;
end
end
endfunction
task Printf-header; *- @I // Print ASIC vector-file headers 1
Input [31:O] MCD; // 32-bit Multi-Channel Descriptor
input [31:O] TYPE;
case (TYPE)
0: begin // inputs & inouts only
$fdisplay(MCD,” AAAAAAAAAAAAAAADDDDDDDDADR”);
$fdisplay(MCD,” CCCCCCCCCDDDDDDAAAAAAAASS-’I);
$fdisplay( MCD,” QQQQQQQQQDDDDDDTTTTTTTT W ) ;
$fdisplay(MCD,” RRR RR R AAAAAAAA N”);
$fdisplay( MCD,” DDDDDDDDCBBBBBBBBBBBBBB ”);
$fdisplay(MCD,” AAAAAAAALU UUUUUUUUUUUUU ”);
$fdisplay(MCD,” TlTTTTTTKSSSSSSSSSSSSSS ”);
$fdisplay(MCD,” AAAAAAAA - ’7;
$fdisplay(MCD,” 7654321 0 5432107654321 0 ”); In this example, the case
end I header is identical to
1: begin I/ all I/O / case 0 header because
$fdisplay(MCD,” AAAAAAAAAAAAAAADDDDDDDDADR”); there are no dedicated
$fdisplay(MCD,” CCCCCCCCCDDDDDDAAAAAAAASS-”); output pins on this ASIC.
$fdisplay(MCD,” QQQQQQQQQDDDDDDTTTTTTTT W ) : Typically these headers
$fdisplay(MCD,” R R R RRRAAAAAAAA N”); are slightly different
$fdisplay(MCD,” DDDDDDDDCBBBBBBBBBBBBBB ”);
$fdisplay(MCD,” AAAAAAAALUUUUUUUUUUUUUU ”);
$fdisplay(MCD,” TTTTTTTTKSSSSSSSSSSSSSS ”);
$fdisplay(MCD,” AAAAAAAA ”1;
$fdisplay(MCD,” 7654321 0 54321 07654321 0 ”);
end
default: begin
$display(”lnvalid Printf-header TYPE - %d”, TYPE);
$finish;
end
endcase
endtask Figure 9. File: acqasic.v (cont.) - ASIC Vector File Code (cont.)

69
task Printf-vector; @I // Print ASIC vectors I
input [31:O] MCD; // 32-bit Multi-Channel Descriptor
input [31:O] TYPE;
case (TYPE)
0: begin // Print input vector
$fstrobe(MCD,””/ot”,$time,,
acq_data[7], acq_data[6], acq_data[5], acq_data[4],
acq_data[3], acq_data[2], acq-data[ 11, acq-data[O],
acq-clk,
addrbus[5], addrbus[4], addrbus[3],
addrbus[2], addrbus[l 1, addrbus[O],
databus[7], databus[6], databus[5], databus[4],
databus[3], databus[2], databus[l], databus[O],
as, ds, r-wn);
end
1: begin // Print VO vector
$fstrobe(MCD,”%t”,$time,,
acq_data[7], acq_data[6], acq_data[5], acq_data[4],
acq_data[3], acq_data[2], acq-data[ 11, acq-data[O], vector list is identical to
acq-c Ik, case 0 vector list because
addrbus[5], addrbus[4], addrbus[3], there are no dedicated
addrbus[2], addrbus[l], addrbus[O], output pins on this ASIC.
databus[7], databus[6], databus[5], databus[4], Typically these lists are
databus[3], databus[2], databus[l], databus[O],
as, ds, r-wn);
end
default: begin
$display(”lnvalid Printf-vector TYPE - %d”, TYPE);
$finish;
end
endcase
endtask
‘endif
endmodule

Figure 10. File: acqasic.v (cont.) - ASIC Vector File Code (cont.)

70