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Ee271 #HW2-2

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7 views2 pages

Ee271 #HW2-2

Uploaded by

yatish vemulapalli
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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HW #2 (Due 27th October)

Access the lab and use Synopsys tools for the HW problems and submit the screenshots
of your work. Your SJSU ID must be shown in the screenshots.
1) (10 points) Explain with example the difference between Mealy and Moore Machine.

2) (20 Points) Draw state diagram of “1010” pattern using Overlapping Moore
Sequence Detector. Also write Verilog code for the same.

3) (30 points) Design a Moore FSM which has a single input IN and a single output
OUT to detect the falling edge of the input IN. The output OUT is asserted (high) for
one clock cycle whenever the input changes from 1 to 0. The example waveforms
below would help you to understand how the output OUT behaves. Assume IN = 0
initially.

(i) Draw the state diagram of the FSM.


(ii) Construct the state transition and output table of the FSM.
(iii) Determine the output and the next state functions using k-map.
(iv) Draw the circuit implementation of the FSM.

4) (10 points) Given the circuit shown below:


(i) Write the behavioural Verilog Module
(ii) Write the structural Verilog Module
5) (20 points) An FSM is described by the following state diagram:

(i) Write the Verilog code for this FSM. The FSM should be reset asynchronously by
an active high reset signal. The states can be binary or one-hot encoded.
(ii) Write a testbench for your FSM Verilog module.
(iii) Run VCS for your FSM and obtain the waveforms.

6) (10 point) Given the following Verilog code, what value of "a" is displayed?
always @ (posedge clk) begin
a = 0;
a <= 1;
$display(a);
end

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