EE3XX COMPUTER ORGANIZATION

Course Project

A RISC CPU is to be designed in the VHDL/Verilog HDL modeling language, verified via Mentor
Graphics "ModelSim" simulator and implemented on the Xilinx FPGA board.

The Instruction set architecture of the processor is described as below:

1. The ISA may contain no more than 16 unique instructions. However, you may have multiple
formats for a given type of instruction, if necessary.
2. Of the 16 instructions, at least one instruction should make your processor HALT.
3. Since it’s a small processor, you need not use the pointers like stack pointer, global pointer, etc.
4. The ISA is to support 16-bit data words only. (No byte operands.)
a. All operands are to be 16-bit signed integers (2’s complement).
b. Each instruction must be encoded using one 16-bit word.
5. The ISA is to support linear addressing of 8K, 16-bit words memory. The memory is to be word-
addressable only - not byte-addressable.
6. The ISA should contain appropriate numbers and types of user-programmable registers to support
it.
7. The ISA must “support” the following C Programming Language constructs:

* Assignment operator: variable = expression;

Expressions must support only two arithmetic operators:
add (+) and subtract (-). Multiply(*) and divide(/) not necessary to implement.
Expressions must support Logical operators: NOT (unary operation), AND and
OR.
Data are limited to:
- 16-bit two’s-complement integers (Example: int a;)
- One-dimensional integer arrays (Example: int a[10];)
* Control flow structures: “if-else” structures, “while” loops, “for” loops
These should support the six standard relational operators:
==, !=, >, <=, <, >=
* Functions (call and return), with parameters able to be passed by value
or by reference.

The data-path must have three 16-bit external “ports” to connect the CPU to the memory: a Read data bus,
A Write data bus and an address bus. The datapath must also have the various control and status signals as
external “ports”. Apart from those the datapath also needs to have the input “inr” used as a multiplexor to
decide the register number and the output “outvalue” which is used to display the contents of that register.

Report:
Students can submit one report per group. However, the report should clearly spell out the contribution of
each member of the group. It is expected that all members should have a reasonable equality in terms of
sharing the workload. The report should touch upon the following points:

A. Instruction Set Architecture:

Provide the following information about your ISA:
1) - List and describe the user-programmable registers.
2) - List and describe the different instruction formats used.
3) - For each instruction in your instruction set, list the following:
 o Assembly language for each form of the instruction - mnemonic and
operands
o Machine language for each form of the instruction:
- instruction code format, op-code, and operand encoding
o Justification for including each form of the instruction in your ISA
- For each C construct, provide an example showing how the construct would be “compiled”, i.e.
implemented with your instruction set, by writing an example of the C construct and the
corresponding assembly language (AL) implementation.

B. Data-path Architecture:
In this part, you are to design the datapath of a CPU that will realize the instruction set architecture (ISA)
designed in the previous assignment (including any “adjustments” made to the ISA). Include the
following in your submission.
1. A block diagram (register level) of the datapath, with all components and control signals clearly
labeled.
2. A description of the function of each component in the datapath.
3. For each instruction of your ISA, list the register transfers, or sequence of register transfers,
required to fetch and execute the instruction. Register names should correspond to components in
your datapath diagram.
4. A discussion of the tradeoffs and other design decisions made in developing your datapath. This
should include:
- Cost vs. speed tradeoffs that you considered.
- Why you chose a single-cycle or multi-cycle design.
- Decisions related to “shared” and/or “dedicated” components.
- Selection of edge-triggered vs. latching registers.
- Other decisions that were considered.

C. Data-path Verification:
Develop and verify a VHDL/Verilog model of the data-path of your CPU. The CPU must be
capable of working with a single memory outside the CPU (you might need another instance of
the memory if your datapath has a separate data and instruction memory).

1. The top-level design should contain only component instantiations, matching your block
diagram (changes may be made to the diagram as necessary).
2. Design and test VHDL/verilog models of each unique component used in your datapath.
3. Create a table listing all control signals and the values of each control signal required for the
different clock cycles like fetch, decode, execute, etc.
4. You will have to submit the control signal table, the VHDL/verilog code and Simulation List
of all the components in the datapath as well as the VHDL/verilog code the complete top
level Datapath.

Major Datapath Components Likely to be needed:

ALU: The ALU must provide all arithmetic and logic functions required to support your instruction
set. It should not provide unnecessary functions.
Register file: Design as a multi-port “memory array”. DO NOT instantiate individual registers.
Sign/zero extension logic, as appropriate, for ALU inputs.
Program counter (PC).
Instruction register (IR) (if required).
Assorted multiplexers for data paths and register address inputs.
D. Controller Design:
1. Design and test a VHDL/Verilog “behavioral” model of the control unit to realize the behavior
described in your Control Signal Table from the previous part of the project. Submit the
VHDL/verilog code and simulation results of the Control Unit.
2. Simulate the datapath component, verifying all required register transfers, by applying control
signals through the control unit created above and show in the simulation where you verified
each required register transfer for the CPU. (If some register transfers are common to multiple
instructions, you do not need to show them separately for every instruction – but it might be a
good idea to do so anyway.) Choose a test program. Force the inputs of control unit(which are
otherwise fetched from the program memory)as per the program so as to mimic the normal
operation and test all the stages of operation.
3. Create a CPU component by instantiating and connecting your control unit and datapath
components. CPU I/O ports should be limited to a clock, reset, inr as the input ports and outvalue
as the output port.
4. For the final simulation of the test program, to minimize the size of the listing, display only
one line per clock transition (i.e., trigger only on clock signal transitions). Show a sufficient set
of control signals to demonstrate correct operation of each instruction (control unit state, address
bus, data bus, ALU output, register file outputs, register file input, memory control signals, etc.)
On the simulation listing, annotate by writing the corresponding assembly language instruction
next to each execute cycle and highlighting the “significant” result register or bus value.

E. FPGA based hardware implementation of CPU:

You will have to show the implemented design on your Xilinx FPGA Board. You will be
conducting a demo as follows:
(a) Briefly describe what is implemented, what program you will run and what result is
expected.
(b) Run the program pointing to the functions of the buttons you press. Let the viewer
examine the result.
(c) Offer to make a change to some parameter to a viewer selected value and rerun the demo.
(d) Total duration of demo: FIVE MINUTES.

F. Remarks:
The remarks section of the report must be a three-page reply to four questions:
(a) What did you learn from this project?
(b) How can you possibly improve the performance of the deigned processor?
(c) What would you do differently next time?
(d) What is your advice to someone who is going to work on a similar project?