L3G4200D

MEMS motion sensor: three-axis

digital output gyroscope
Preliminary data

Features
■ Three selectable full scales (250/500/2000
dps)
■ I2C/SPI digital output interface
■ 16 bit-rate value data output
■ 8-bit temperature data output LGA-16 (4x4x1.1 mm)
■ Two digital output lines (interrupt and data
ready)
■ Integrated low- and high-pass filters with user- Description
selectable bandwidth
■ Embedded self-test The L3G4200D is a low-power three-axis angular
rate sensor.
■ Wide supply voltage: 2.4 V to 3.6 V
■ Low voltage-compatible IOs (1.8 V) It includes a sensing element and an IC interface
capable of providing the measured angular rate to
■ Embedded power-down and sleep mode the external world through a digital interface
■ Embedded temperature sensor (I2C/SPI).
■ 96 levels of 16-bit data output (FIFO) The sensing element is manufactured using a
■ High shock survivability dedicated micro-machining process developed by
STMicroelectronics to produce inertial sensors
■ Extended operating temperature range (-40 °C
and actuators on silicon wafers.
to +85 °C)
■ ECOPACK® RoHS and “Green” compliant The IC interface is manufactured using a CMOS
process that allows a high level of integration to
design a dedicated circuit which is trimmed to
Applications better match the sensing element characteristics.
■ Gaming and virtual reality input devices The L3G4200D has a full scale of ±250/±500/
■ Motion control with MMI (man-machine ±2000 dps and is capable of measuring rates with
interface) a user-selectable bandwidth.
■ GPS navigation systems The L3G4200D is available in a plastic land grid
array (LGA) package and can operate within a
■ Appliances and robotics
temperature range of -40 °C to +85 °C.

Table 1. Device summary

Order code Temperature range (°C) Package Packing

L3G4200D -40 to +85 LGA-16 (4x4x1.1 mm) Tray

L3G4200DTR -40 to +85 LGA-16 (4x4x1.1 mm) Tape and reel

September 2010 Doc ID 17116 Rev 2 1/29

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to www.st.com 29
change without notice.
Contents L3G4200D

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Mechanical and electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4.1 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4.2 I2C - inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.6 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6.1 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6.2 Zero-rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6.3 Self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.7 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Main digital blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.1 Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.2 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.3 Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.4 Bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2.5 Stream-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.6 Retrieve data from FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1.1 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

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L3G4200D Contents

5.2.1 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.2.2 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2.3 SPI read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Doc ID 17116 Rev 2 3/29

List of tables L3G4200D

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Filter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Mechanical characteristics @ Vdd = 3.0 V, T = 25 °C, unless otherwise noted . . . . . . . . . . 9
Table 5. Electrical characteristics @ Vdd =3.0 V, T=25 °C, unless otherwise noted . . . . . . . . . . . . 10
Table 6. Temp. sensor characteristics @ Vdd =3.0 V, T=25 °C, unless otherwise noted . . . . . . . . 10
Table 7. SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 8. I2C slave timing values (TBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 9. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 10. PLL low-pass filter component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 11. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 12. I2C terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 13. SAD+read/write patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 14. Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 15. Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 16. Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 22
Table 17. Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 22
Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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L3G4200D List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. L3G4200D external low-pass filter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. I2C slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. Bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. Trigger stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. L3G4200D electrical connections and external component values . . . . . . . . . . . . . . . . . . 19
Figure 13. Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 14. SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 15. Multiple byte SPI read protocol (2-byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 16. SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 17. Multiple byte SPI write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 18. SPI read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 19. LGA-16: mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Doc ID 17116 Rev 2 5/29

Block diagram and pin description L3G4200D

1 Block diagram and pin description

Figure 1. Block diagram

+Ω
x,y,z
X+
CHARGE MIXER LOW-PASS
Y+
AMP FILTER F
Z+ D
I I
L CS
M A G
D T I2C SCL/SPC
U I
X C E SPI SDA/SDO/SDI
Z- T SDO
1 A R
Y- I
L N
X- G

T
E
M
S
P
E E A
N D
DRIVING MASS R
S C
A
O 2
T
R
U
Feedback loop R
E

CLOCK CONTROL LOGIC INT1

TRIMMING
REFERENCE FIFO & &
CIRCUITS PHASE GENERATOR DRDY/INT2
INTERRUPT GEN.

AM07225v1

The vibration of the structure is maintained by drive circuitry in a feedback loop. The sensing
signal is filtered and appears as a digital signal at the output.

1.1 Pin description

Figure 2. Pin connection
PLLFILT

+Ω
Z
GND

RES
Vdd

1
X 13 16
+Ω
Y RES 12 1 Vdd_IO
RES BOTTOM SCL/SPC
VIEW
RES SDA/SDI/SDO
+Ω RES 9 4 SDO/SA0
X 8 5
RES
INT
DRDY/INT2
CS

(TOP VIEW)
DIRECTIONS OF THE
DETECTABLE
ANGULAR RATES
AM07226v1

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L3G4200D Block diagram and pin description

Table 2. Pin description

Pin# Name Function

1 Vdd_IO Power supply for I/O pins

SCL I2C serial clock (SCL)
2
SPC SPI serial port clock (SPC)
SDA I2C serial data (SDA)
3 SDI SPI serial data input (SDI)
SDO 3-wire interface serial data output (SDO)
SDO SPI serial data output (SDO)
4
SA0 I2C least significant bit of the device address (SA0)
SPI enable
5 CS
I2C/SPI mode selection (1:I2C mode; 0: SPI enabled)
6 DRDY/INT2 Data ready/FIFO interrupt
7 INT1 Programmable interrupt
8 Reserved Connect to GND
9 Reserved Connect to GND
10 Reserved Connect to GND
11 Reserved Connect to GND
12 Reserved Connect to GND
13 GND 0 V supply
14 PLLFILT Phase-locked loop filter (see Figure 3)
15 Reserved Connect to Vdd
16 Vdd Power supply

Figure 3. L3G4200D external low-pass filter values (a)

%CRCEKVQTHQT
.QYRCUUHKNVGT

VQRKP %

% 4

)0&
#/X

a. Pin 14 PLLFILT maximum voltage level is equal to Vdd.

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Block diagram and pin description L3G4200D

Table 3. Filter values

Parameter Typical value

C1 10 nF
C2 470 nF
R2 10 kΩ

8/29 Doc ID 17116 Rev 2

L3G4200D Mechanical and electrical characteristics

2 Mechanical and electrical characteristics

2.1 Mechanical characteristics

Table 4. Mechanical characteristics @ Vdd = 3.0 V, T = 25 °C, unless otherwise noted(1)
Symbol Parameter Test condition Min. Typ.(2) Max. Unit
±250
FS Measurement range User-selectable ±500 dps
±2000
FS = 250 dps 8.75
So Sensitivity FS = 500 dps 17.50 mdps/digit
FS = 2000 dps 70
Sensitivity change vs.
SoDr From -40 °C to +85 °C ±2 %
temperature
FS = 250 dps ±10
DVoff Digital zero-rate level FS = 500 dps ±15 dps
FS = 2000 dps ±75

Zero-rate level change FS = 250 dps ±0.03 dps/°C

OffDr
vs. temperature(3) FS = 2000 dps ±0.04 dps/°C
(4)
NL Non linearity Best fit straight line 0.2 % FS
FS = 250 dps 130
DST Self-test output change FS = 500 dps 200 dps
FS = 2000 dps 530
Rn Rate noise density BW = 40 Hz 0.03 dps/
100/200/
ODR Digital output data rate Hz
400/800
Operating temperature
Top -40 +85 °C
range
1. The product is factory calibrated at 3.0 V. The operational power supply range is specified in Table 5.
2. Typical specifications are not guaranteed.
3. Min/max values have been estimated based on the measurements of the current gyros in production.
4. Guaranteed by design.

Doc ID 17116 Rev 2 9/29

Mechanical and electrical characteristics L3G4200D

2.2 Electrical characteristics

Table 5. Electrical characteristics @ Vdd =3.0 V, T=25 °C, unless otherwise noted(1)
Symbol Parameter Test condition Min. Typ.(2) Max. Unit

Vdd Supply voltage 2.4 3.0 3.6 V

(3)
Vdd_IO I/O pins supply voltage 1.71 Vdd+0.1 V
Idd Supply current 6.1 mA

Supply current Selectable by digital

IddSL 1.5 mA
in sleep mode(4) interface

Supply current in Selectable by digital

IddPdn 5 µA
power-down mode interface
Operating temperature
Top -40 +85 °C
range
1. The product is factory calibrated at 3.0 V.
2. Typical specifications are not guaranteed.
3. It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the
measurement chain is powered off.
4. Sleep mode introduces a faster turn-on time compared to power-down mode.

2.3 Temperature sensor characteristics

Table 6. Temp. sensor characteristics @ Vdd =3.0 V, T=25 °C, unless otherwise noted(1)
Symbol Parameter Test condition Min. Typ.(2) Max. Unit

Temperature sensor
TSDr output change vs. -1 °C/digit
temperature
TODR Temperature refresh rate 1 Hz
Operating temperature
Top -40 +85 °C
range
1. The product is factory calibrated at 3.0 V.
2. Typical specifications are not guaranteed.

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L3G4200D Mechanical and electrical characteristics

2.4 Communication interface characteristics

2.4.1 SPI - serial peripheral interface

Subject to general operating conditions for Vdd and Top.

Table 7. SPI slave timing values

Value(1)
Symbol Parameter Unit
Min. Max.

tc(SPC) SPI clock cycle 100 ns

fc(SPC) SPI clock frequency 10 MHz
tsu(CS) CS setup time 5
th(CS) CS hold time 8
tsu(SI) SDI input setup time 5
th(SI) SDI input hold time 15 ns
tv(SO) SDO valid output time 50
th(SO) SDO output hold time 6
tdis(SO) SDO output disable time 50
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results; not
tested in production.

Figure 4. SPI slave timing diagram(b)

&6  

WVX &6 WF 63& WK &6

63&  

WVX 6, WK 6,

6',  06%,1 /6%,1 

WY 62 WK 62 WGLV 62

6'2  06%287 /6%287 

!-V

b. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports.

Doc ID 17116 Rev 2 11/29

Mechanical and electrical characteristics L3G4200D

2.4.2 I2C - inter IC control interface

Subject to general operating conditions for Vdd and Top.

Table 8. I2C slave timing values (TBC)

I2C standard mode(1) I2C fast mode (1)
Symbol Parameter Unit
Min Max Min Max
f(SCL) SCL clock frequency 0 100 0 400 kHz
tw(SCLL) SCL clock low time 4.7 1.3
µs
tw(SCLH) SCL clock high time 4.0 0.6
tsu(SDA) SDA setup time 250 100 ns
th(SDA) SDA data hold time 0 3.45 0 0.9 µs

tr(SDA) tr(SCL) SDA and SCL rise time 1000 20 + 0.1Cb (2) 300
ns
tf(SDA) tf(SCL) SDA and SCL fall time 300 20 + 0.1Cb (2) 300

th(ST) START condition hold time 4 0.6

Repeated START condition
tsu(SR) 4.7 0.6
setup time
µs
tsu(SP) STOP condition setup time 4 0.6
Bus free time between STOP
tw(SP:SR) 4.7 1.3
and START condition
1. Data based on standard I2C protocol requirement; not tested in production.
2. Cb = total capacitance of one bus line, in pF.

Figure 5. I2C slave timing diagram (c)

5(3($7('
67$57
67$57

WVX 65
WZ 6365 67$57
6'$

WI 6'$ WU 6'$ WVX 6'$ WK 6'$

WVX 63 6723

6&/

WK 67 WZ 6&// WZ 6&/+ WU 6&/ WI 6&/ !-V

c. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.

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L3G4200D Mechanical and electrical characteristics

2.5 Absolute maximum ratings

Any stress above that listed as “Absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.

Table 9. Absolute maximum ratings

Symbol Ratings Maximum value Unit

Vdd Supply voltage -0.3 to 4.8 V

TSTG Storage temperature range -40 to +125 °C
Sg Acceleration g for 0.1 ms 10,000 g
ESD Electrostatic discharge protection 2 (HBM) kV

This is a mechanical shock sensitive device, improper handling can cause permanent
damage to the part
This is an ESD sensitive device, improper handling can cause permanent damage to
the part

Doc ID 17116 Rev 2 13/29

Mechanical and electrical characteristics L3G4200D

2.6 Terminology

2.6.1 Sensitivity
An angular rate gyroscope is a device that produces a positive-going digital output for
counterclockwise rotation around the sensitive axis considered. Sensitivity describes the
gain of the sensor and can be determined by applying a defined angular velocity to it. This
value changes very little over temperature and time.

2.6.2 Zero-rate level

Zero-rate level describes the actual output signal if there is no angular rate present. The
zero-rate level of precise MEMS sensors is, to some extent, a result of stress to the sensor
and, therefore, the zero-rate level can slightly change after mounting the sensor onto a
printed circuit board or after exposing it to extensive mechanical stress. This value changes
very little over temperature and time.

2.6.3 Self-test
Self-test allows testing of the mechanical and electric part of the sensor, allowing the
seismic mass to be moved by means of an electrostatic test-force. When self-test is
activated by the IC, an actuation force is applied to the sensor, emulating a definite Coriolis
force. In this case the sensor output exhibits an output change.
When ST (self-test) is active, the device output level is given by the algebraic sum of the
signals produced by the velocity acting on the sensor and by the electrostatic test-force.

2.7 Soldering information

The LGA package is compliant with the ECOPACK®, RoHS and “Green” standard.
It is qualified for soldering heat resistance according to JEDEC J-STD-020.
Leave “pin 1 Indicator” unconnected during soldering.
Land pattern and soldering recommendations are available at www.st.com/.

14/29 Doc ID 17116 Rev 2

L3G4200D Main digital blocks

3 Main digital blocks

3.1 Block diagram

Figure 6. Block diagram
/UT?3EL


 $ATA2EG


&)&/
,0&  XX

!$# ,0& (0&  )#
30)
(0EN ).4?3EL



)NTERRUPT
 GENERATOR


3#2 2%'

#/.& 2%'

).4

!-V

3.2 FIFO
The L3G4200D embeds a 32-slot, 16-bit data FIFO for each of the three output channels:
yaw, pitch, and roll. This allows consistent power saving for the system, as the host
processor does not need to continuously poll data from the sensor. Instead, it can wake up
only when needed and burst the significant data out from the FIFO. This buffer can work in
five different modes. Each mode is selected by the FIFO_MODE bits in the
FIFO_CTRL_REG. Programmable watermark level, FIFO_empty or FIFO_Full events can
be enabled to generate dedicated interrupts on the DRDY/INT2 pin (configured through
CTRL_REG3), and event detection information is available in FIFO_SRC_REG. The
watermark level can be configured to WTM4:0 in FIFO_CTRL_REG.

3.2.1 Bypass mode

In bypass mode, the FIFO is not operational and for this reason it remains empty. As
illustrated in Figure 7, only the first address is used for each channel. The remaining FIFO
slots are empty. When new data is available, the old data is overwritten.

Doc ID 17116 Rev 2 15/29

Main digital blocks L3G4200D

Figure 7. Bypass mode

XI YI ZI
X Y I Z

X Y Z

X Y Z
EMPTY

X  Y  Z

!-V

3.2.2 FIFO mode

In FIFO mode, data from the yaw, pitch, and roll channels are stored in the FIFO. A
watermark interrupt can be enabled (I2_WMK bit in CTRL_REG3), which is triggered when
the FIFO is filled to the level specified in the WTM 4:0 bits of FIFO_CTRL_REG. The FIFO
continues filling until it is full (32 slots of 16-bit data for yaw, pitch, and roll). When full, the
FIFO stops collecting data from the input channels. To restart data collection, it is necessary
to write FIFO_CTRL_REG back to bypass mode.
FIFO mode is represented in Figure 8.

Figure 8. FIFO mode

XI YI ZI
X Y I Z

X Y Z

X Y Z

X  Y  Z

!-V

3.2.3 Stream mode

In stream mode, data from yaw, pitch, and roll measurements are stored in the FIFO. A
watermark interrupt can be enabled and set as in FIFO mode. The FIFO continues filling
until full (32 slots of 16-bit data for yaw, pitch, and roll). When full, the FIFO discards the

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L3G4200D Main digital blocks

older data as the new data arrives. Programmable watermark level events can be enabled to
generate dedicated interrupts on the DRDY/INT2 pin (configured through CTRL_REG3).
Stream mode is represented in Figure 9.

Figure 9. Stream mode

XI YI ZI
X Y Z

X Y Z

X Y Z

X  Y  Z

X  Y  Z

!-V

3.2.4 Bypass-to-stream mode

In bypass-to-stream mode, the FIFO starts operating in bypass mode, and once a trigger
event occurs (related to INT1_CFG register events), the FIFO starts operating in stream
mode (see Figure 10).

Figure 10. Bypass-to-stream mode

XI YI ZI XI YI ZI
X Y I Z X Y Z

X Y Z
X Y Z
X Y Z
X Y Z
%MPTY
X  Y  Z

X  Y  Z
X  Y  Z

"YPASS MODE 3TREAM MODE

4RIGGER EVENT !-V

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Main digital blocks L3G4200D

3.2.5 Stream-to-FIFO mode

In stream-to-FIFO mode, data from yaw, pitch, and roll measurements are stored in the
FIFO. A watermark interrupt can be enabled on pin DRDY/INT2, setting the I2_WTM bit in
CTRL_REG3, which is triggered when the FIFO is filled to the level specified in the WTM4:0
bits of FIFO_CTRL_REG. The FIFO continues filling until full (32 slots of 16-bit data for yaw,
pitch, and roll). When full, the FIFO discards the older data as the new data arrives. Once a
trigger event occurs (related to INT1_CFG register events), the FIFO starts operating in
FIFO mode (see Figure 11).

Figure 11. Trigger stream mode

XI YI ZI XI YI ZI
X Y Z
X Y I Z

X Y Z
X Y Z
X Y Z
X Y Z
X  Y  Z

X  Y  Z
X  Y  Z

3TREAM -ODE &)&/ -ODE

4RIGGER EVENT
!-V

3.2.6 Retrieve data from FIFO

FIFO data is read through the OUT_X, OUT_Y and OUT_Z registers. When the FIFO is in
stream, trigger or FIFO mode, a read operation to the OUT_X, OUT_Y or OUT_Z registers
provides the data stored in the FIFO. Each time data is read from the FIFO, the oldest pitch,
roll, and yaw data are placed in the OUT_X, OUT_Y and OUT_Z registers and both single
read and read_burst (X,Y & Z with auto-incremental address) operations can be used. In
read_burst mode, when data included in OUT_Z_H is read, the system again starts to read
information from addr OUT_X_L.

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L3G4200D Application hints

4 Application hints

Figure 12. L3G4200D electrical connections and external component values

Vdd GND GND
+Ω
Z

100 nF 10 µF
1
X
+Ω

PLLFILT
Y

Vdd
16 13
+Ω Vdd_IO
X 1 12

(TOP VIEW) SCL/SPC TOP

DIRECTIONS OF THE VIEW
DETECTABLE SDA_SDI_SDO
ANGULAR RATES
SDO/SA0 4 9
5 8
10nF C1

GND
10kOhm 470nF
CS DR INT

R2 C2
Vdd I2C bus

Rpu Rpu = 10kOhm

PLLFILT
GND

SCL/SPC
SDA_SDI_SDO
Pull-up to be added when I2C interface is used
AM07949V1

Power supply decoupling capacitors (100 nF ceramic or polyester +10 µF) should be placed
as near as possible to the device (common design practice).
If Vdd and Vdd_IO are not connected together, power supply decoupling capacitors
(100 nF and 10 µF between Vdd and common ground, 100 nF between Vdd_IO and
common ground) should be placed as near as possible to the device (common design
practice).
The L3G4200D IC includes a PLL (phase locked loop) circuit to synchronize driving and
sensing interfaces. Capacitors and resistors must be added at the PLLFILT pin (as shown in
Figure 12) to implement a second-order low-pass filter. Table 10 summarizes the PLL low-
pass filter component values.

Table 10. PLL low-pass filter component values

Component Value

C1 10 nF ± 10 %
C2 470 nF ± 10 %
R2 10 kΩ ± 10 %

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Digital interfaces L3G4200D

5 Digital interfaces

The registers embedded in the L3G4200DH may be accessed through both the I2C and SPI
serial interfaces. The latter may be software-configured to operate either in 3-wire or 4-wire
interface mode.
The serial interfaces are mapped onto the same pins. To select/exploit the I2C interface, the
CS line must be tied high (i.e., connected to Vdd_IO).

Table 11. Serial interface pin description

Pin name Pin description

SPI enable
CS
I2C/SPI mode selection (1: I2C mode; 0: SPI enabled)
I2C serial clock (SCL)
SCL/SPC
SPI serial port clock (SPC)
I2C serial data (SDA)
SDA/SDI/SDO SPI serial data input (SDI)
3-wire interface serial data output (SDO)
SPI serial data output (SDO)
SDO
I2C least significant bit of the device address

5.1 I2C serial interface

The L3G4200DH I2C is a bus slave. The I2C is employed to write data to registers whose
content can also be read back.
The relevant I2C terminology is given in the table below.

Table 12. I2C terminology

Term Description

Transmitter The device which sends data to the bus

Receiver The device which receives data from the bus
The device which initiates a transfer, generates clock signals and terminates a
Master
transfer
Slave The device addressed by the master

There are two signals associated with the I2C bus: the serial clock line (SCL) and the serial
data line (SDA). The latter is a bidirectional line used for sending and receiving the data
to/from the interface. Both lines must be connected to Vdd_IO through an external pull-up
resistor. When the bus is free both the lines are high.
The I2C interface is compliant with fast mode (400 kHz) I2C standards as well as with normal
mode.

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L3G4200D Digital interfaces

5.1.1 I2C operation

The transaction on the bus is started through a START (ST) signal. A START condition is
defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and
the eighth bit tells whether the master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first 7 bits after
a start condition with its address. If they match, the device considers itself addressed by the
master.
The slave address (SAD) associated with the L3G4200DH is 110100xb. The SDO pin can
be used to modify the least significant bit (LSb) of the device address. If the SDO pin is
connected to the voltage supply, LSb is ‘1’ (address 1101001b). Otherwise, if the SDO pin is
connected to ground, the LSb value is ‘0’ (address 1101000b). This solution permits the
connection and addressing of two different gyroscopes to the same I2C bus.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which
has been addressed is obliged to generate an acknowledge after each byte of data
received.
The I2C embedded in the L3G4200DH behaves like a slave device, and the following
protocol must be adhered to. After the START (ST) condition, a slave address is sent. Once
a slave acknowledge (SAK) has been returned, an 8-bit sub-address is transmitted. The 7
LSb represent the actual register address while the MSB enables address auto-increment. If
the MSb of the SUB field is 1, the SUB (register address) is automatically incremented to
allow multiple data read/write.
The slave address is completed with a read/write bit. If the bit is ‘1’ (read), a REPEATED
START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (write)
the master transmits to the slave with the direction unchanged. Table 13 describes how the
SAD+read/write bit pattern is composed, listing all the possible configurations.

Table 13. SAD+read/write patterns

Command SAD[6:1] SAD[0] = SDO R/W SAD+R/W

Read 110100 0 1 11010001 (D1h)

Write 110100 0 0 11010000 (D0h)
Read 110100 1 1 11010011 (D3h)
Write 110100 1 0 11010010 (D2h)

Table 14. Transfer when master is writing one byte to slave

Master ST SAD + W SUB DATA SP
Slave SAK SAK SAK

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Digital interfaces L3G4200D

Table 15. Transfer when master is writing multiple bytes to slave

Master ST SAD + W SUB DATA DATA SP
Slave SAK SAK SAK SAK

Table 16. Transfer when master is receiving (reading) one byte of data from slave
Master ST SAD + W SUB SR SAD + R NMAK SP
Slave SAK SAK SAK DATA

Table 17. Transfer when master is receiving (reading) multiple bytes of data from slave
Master ST SAD+W SUB SR SAD+R MAK MAK NMAK SP
Slave SAK SAK SAK DATA DATA DATA

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number
of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit
(MSb) first. If a receiver cannot receive another complete byte of data until it has performed
some other function, it can hold the clock line SCL LOW to force the transmitter into a wait
state. Data transfer only continues when the receiver is ready for another byte and releases
the data line. If a slave receiver does not acknowledge the slave address (i.e., it is not able
to receive because it is performing some real-time function) the data line must be left HIGH
by the slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA
line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
In order to read multiple bytes, it is necessary to assert the most significant bit of the sub-
address field. In other words, SUB(7) must be equal to 1, while SUB(6-0) represents the
address of the first register to be read.
In the presented communication format, MAK is “master acknowledge” and NMAK is “no
master acknowledge”.

5.2 SPI bus interface

The SPI is a bus slave. The SPI allows writing and reading of the device registers. The serial
interface interacts with the external world through 4 wires: CS, SPC, SDI, and SDO.

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L3G4200D Digital interfaces

Figure 13. Read and write protocol

CS

SPC

SDI
RW DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
MS AD5 AD4 AD3 AD2 AD1 AD0

SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

CS is the serial port enable and is controlled by the SPI master. It goes low at the start of the
transmission and returns to high at the end. SPC is the serial port clock and is controlled by
the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are,
respectively, the serial port data input and output. These lines are driven at the falling edge
of SPC and should be captured at the rising edge of SPC.
Both the read register and write register commands are completed in 16 clock pulses, or in
multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling
edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge
of CS while the last bit (bit 15, bit 23, etc.) starts at the last falling edge of SPC just before
the rising edge of CS.
Bit 0: RW bit. When 0, the data DI(7:0) is written to the device. When 1, the data DO(7:0)
from the device is read. In the latter case, the chip drives SDO at the start of bit 8.
Bit 1: MS bit. When 0, the address remains unchanged in multiple read/write commands.
When 1, the address is auto-incremented in multiple read/write commands.
Bit 2-7: address AD(5:0). This is the address field of the indexed register.
Bit 8-15: data DI(7:0) (write mode). This is the data that is written to the device (MSb first).
Bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
In multiple read/write commands, further blocks of 8 clock periods are added. When the MS
bit is 0, the address used to read/write data remains the same for every block. When the MS
bit is 1, the address used to read/write data is incremented at every block.
The function and the behavior of SDI and SDO remain unchanged.

5.2.1 SPI read

Figure 14. SPI read protocol

CS

SPC

SDI
RW
MS AD5 AD4 AD3 AD2 AD1 AD0

SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

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Digital interfaces L3G4200D

The SPI read command is performed with 16 clock pulses. A multiple byte read command is
performed by adding blocks of 8 clock pulses to the previous one.
Bit 0: READ bit. The value is 1.
Bit 1: MS bit. When 0, do not increment address; when 1, increment address in multiple
reading.
Bit 2-7: address AD(5:0). This is the address field of the indexed register.
Bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
Bit 16-... : data DO(...-8). Further data in multiple byte reading.

Figure 15. Multiple byte SPI read protocol (2-byte example)

CS

SPC

SDI
RW
MS AD5 AD4 AD3 AD2 AD1 AD0

SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15DO14DO13DO12DO11DO10DO9 DO8

5.2.2 SPI write

Figure 16. SPI write protocol

CS

SPC

SDI
RW DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
MS AD5 AD4 AD3 AD2 AD1 AD0

The SPI write command is performed with 16 clock pulses. A multiple byte write command is
performed by adding blocks of 8 clock pulses to the previous one.
Bit 0: WRITE bit. The value is 0.
Bit 1: MS bit. When 0, do not increment address; when 1, increment address in multiple
writing.
Bit 2 -7: address AD(5:0). This is the address field of the indexed register.
Bit 8-15: data DI(7:0) (write mode). This is the data that is written to the device (MSb first).
Bit 16-... : data DI(...-8). Further data in multiple byte writing.

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L3G4200D Digital interfaces

Figure 17. Multiple byte SPI write protocol (2-byte example)

CS

SPC

SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8
RW
MS AD5 AD4 AD3 AD2 AD1 AD0

5.2.3 SPI read in 3-wire mode

3-wire mode is entered by setting the SIM (SPI serial interface mode selection) bit to 1 in
CTRL_REG2.

Figure 18. SPI read protocol in 3-wire mode

CS

SPC

SDI/O
RW DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
MS AD5 AD4 AD3 AD2 AD1 AD0

The SPI read command is performed with 16 clock pulses:

Bit 0: READ bit. The value is 1.
Bit 1: MS bit. When 0, do not increment address; when 1, increment address in multiple
reading.
Bit 2-7: address AD(5:0). This is the address field of the indexed register.
Bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
The multiple read command is also available in 3-wire mode.

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Package information L3G4200D

6 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at www.st.com.
ECOPACK is an ST trademark.

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L3G4200D Package information

Figure 19. LGA-16: mechanical data and package dimensions

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Revision history L3G4200D

7 Revision history

Table 18. Document revision history

Date Revision Changes

01-Apr-2010 1 Initial release.

03-Sep-2010 2 Complete datasheet review.

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L3G4200D

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