2014 International Conference on Advances in Electronics, Computers and Communications (ICAECC)

Comparative analysis of different optimization

technique for Sobel edge detection on FPGA
Lavanya K B1, K. V Ramana Reddy 2, Siva S Yellampalli 3
1
VLSI Design and Embedded Systems, VTU Extension Centre, UTL Technologies Bangalore – 22,
Karnataka, India.
2
Asst. Professor, VTU Extension Centre, UTL Technologies Bangalore - 22, Karnataka, India.
3
Professor, VTU Extension Centre, UTL Technologies Bangalore - 22, Karnataka, India.

Abstract: In this paper we preset implementation of an optimized In this paper we discuss an optimized Sobel operator, it needs
Sobel edge detection algorithm on FPGA. The optimized gradient less FPGA resources and also reduces delay compared to
based edge detection method reduces the area up to 48.76% reference [3] and reference [4].
compared to existing gradient calculation unit, and also reduces
propagation delay up to 51% compared to the area optimized
architecture. The entire project is implemented on Spatran-3E
II. SOBEL EDGE DETECTION ALGORITHM
FPGA board. VGA interface is used to display the edge detection
image on the monitor. In edge detection the Sobel operator is used commonly [1].
The Sobel operator is a classic first order edge detection
Keywords : Sobel edge detector, FPGA, Block Memory. operator, computing an approximation of the gradient of the
image intensity function. Any approximation used for first
I. INTRODUCTION derivative must satisfy the following conditions:[1]
The edge detection is a terminology in the Image 1. It must be zero in the area of constant intensity.
processing particularly in the area of feature extraction to refer 2. It must be nonzero at the onset of intensity step or
to algorithm which aims at identifying points in a digital ramp.
image at which the image brightness changes sharply [1]. 3. It must be nonzero at points along an intensity ramp.
There are some well-known methods for edge detection such First derivative are implemented using magnitude of gradient.
as Sobel, Canny, Prewitt and Robert algorithms which are For an image f (x,y) the gradient of image f at (x,y) is defined
different in terms of performance on hardware, speed and as [5]
simplicity [1]. The Sobel operator is mainly used for hardware f = grad (f) = = (1)
implementation due to efficiency and simple mathematical
model that make it easy for real-time edge detection Where Gx is the gradient in the horizontal direction, Gy is the
application [2]. The edge detection is mainly applicable in gradient in the vertical direction.
case of data transmission; where the edge detected data reduce The two gradient are calculated using the partial derivative of
the amount of data to be transmitted. Edge detection finds its image function f with respect to x and y at every pixel location
application in Computer vision applications, boundary of the image. Digital approximations of these partial
detection, motion detection, segmentation, texture analysis derivatives can be expressed as [1].
and object identification [2]. Gx = ߲f/߲x = [f(x + 1, y) – f(x – 1, y)]/2 (2)
Gy = ߲f/߲y = [f(x, y + 1) – f(x, y – 1)]/2 (3)
The sobel edge detector is very popular than simple gradient The Gradient magnitude is given by
operators, because its less complex and easy for computations G = |Gx| + |Gy| (4)
[2]. The accuracy of the Sobel for edge detection is relatively Here G represents the value of rate of change in the direction
less because it uses only two masks which detect the edges in of gradient vector.
horizontal and vertical directions only. The accuracy can be
enhanced by using the Soble operator which uses a larger set
of masks [1,2]. III. HARDWARE IMPLEMENTATION

Some recent FPGA implementations are available in the

literature for the Sobel edge detector. In [3] the author
discussed the FPGA implementation of the Sobel edge
detector, which uses multiple processing elements in parallel
to compute gradient along each direction. The drawback of
this paper is it requires more FPGA resources. In second paper
[4] the author discussed the area optimized Sobel operator,
which uses only one processing element to compute the
gradient for all the direction. It requires less FPGA resources.
But here delay is increased compared to reference [3].

Fig1: Block diagram for Sobel edge detection algorithm

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 operator, and generation data and gradient are the middle
The above figure 1 shows the entire block diagram of this signals. The function and structure of each module explained
project. The input image is gray scale image of size 128 x128 in the following sections.
each of 8 bits. The Coefficient (coe) file of the input image is
generated using MATLAB. The coe file is stored in Blocki. i. Pixel generation module
Rom which is then processed using the Sobel edge detection
algorithm. The resulting edge detected image is displayed on
monitor using VGA interfacing.

A. Block Memory
Spatran 3E FPGA consist of special Block memories. These
Block memories help in speeding up the memory operations.
Here single port Block ROM used which can support up to
360 Kbits. The width and depth of the design is user defined.
The schematic for the block memory is shown in fig 2.

Fig 4: 3x3 Pixel generation module [7]

The above figure 4 shows the 3 x 3 pixel generator module. It
contains a 9 shift registers and two FIFOs. Each parallel in
parallel out shift register are used to shift the input pixels at
each positive edge of the clock. The FIFO is used to store a
row of image data. The image data input according to the
clock signal, so P1, P2, •••, P9 form the 3 × 3 pixel data
Fig2: Schematic symbol of Block Memory [6] template which are stored in 9 shift registers. When the data is
The memory operations take place on the rising edge of the continuously input,3×3 pixel data template change. It can
clock signal (CLK) when the block memory is enabled and contain all pixel values of an image.
when the block memory is not enabled the memory
configuration and output remain unchanged. When WE isii. ii. Sobel enhancement operator
asserted the input data is stored in the memory at the location
selected by the address [6]. The Sobel operator only considers the two orientations which
 are 0 degree and 90 degree convolution kernels. In order to
B. Sobel edge detection algorithm increase the accuracy, the orientation of the convolution
The architecture for Sobel edge detection is shown in figure kernels is increased from 2 to 4 [7].The convolution kernels
3. The pixel values are stored in the block memory are given for the 4 orientations are shown in the Table 1.
as the input for the Sobel edge detection design. This design TABLE 1: Convolution Kernels [7]
uses 3x3 convolution kernels to compute gradient,
processing an image size of 128x128 each of 8 bit pixels of
Gray Scale Image.




Fig3: Architecture for sobel edge detection [7] 

The above architecture is divided into three modules Using the four masks mentioned above the gradient
i. 3x3 pixel generation module calculation is done using the following equations [3]
ii. Sobel enhancement operator module Gx = (P3 – P1) +2(P6-P4) + (P9-P7) (5)
a. Existing gradient calculation unit [3]. Gy = (P7 – P1) +2(P8-P2) + (P9-P3) (6)
b. Area optimized gradient calculation unit [4] Gdr = (P8 – P2) +2(P9-P1) + (P6-P4) (7)
c. Proposed gradient calculation unit Gdl = (P2 – P8) +2(P3-P7) + (P6-P8) (8)
iii. Binary Segmentation module Gradient can be found by using the equation
In this architecture, Data input are the pixel values of the Gray G = |Gx| + |Gy| + |Gdr| + |Gdl| (9)
Scale Image, Result is the output of the edge detection

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a. Existing Gradient Calculation Unit c. Proposed gradient calculation unit
In the Sobel enhancement operator for calculating the
gradient for all the direction, it increases the propagation
delay [3]. The pipelined gradient calculation unit is used to
reduce the delay. It uses multiple processing elements in
parallel to compute gradient along each direction. But it
requires more registers to store the intermediate values and
it needs more FPGA resources. Existing gradient
calculation unit is shown the figure 5.

Fig 7: Proposed gradient calculation unit

The above figure shows the proposed architecture for

calculating the gradient for all the direction realized through
two processing Element. Processing element consists of
subtraction, multiplication and addition operation to calculate
the convolution of 3 x 3 pixel values. Multiplexers are
selecting the input pixel values for all the directions and R3,
Fig 5: Existing Gradient Calculation Unit[3] R4, R5 and R6 register to store the intermediate results.
Finally calculate the maximum Gradient value. This
b. Area optimized Gradient calculation unit architecture greatly economizes the FPGA resources and also
 reduces propagation delay compared to the existing
The existing implementation of the Sobel edge detector use architectures [3] [4].
four processing elements in parallel for computing gradient
along different directions. Each processing element (PE) iii. Binary Segmentation Module
performs the same set of operations (addition, subtraction and
multiplication by 2) on input applied them. Here only The edge detected image can be obtained from the Sobel
difference for four gradient computation units (PE0, PE45, gradient by using threshold value. Input for this module is the
PE90 and PE135) is in inputs applied to them at a particular gradient value from gradient calculation unit. 8 bit comparator
time [4]. Therefore, by switching the inputs applied to anyone is used to compare the gradient value with the user defined
of processing element in appropriate manner, the same threshold value. The final result is the binary image of edge
processing element can be used to compute all four gradients detection having only two pixel values, 0 and 255. Block
along different directions. The advantage of this architecture diagram of the binary segmentation module shown in the
is it requires less FPGA resources compared to the standard figure 8.
architecture [4]. But drawback of this architecture is delay is
high. The below figure shows the area optimized gradient
calculation unit.

Fig8: Binary segmentation module [8]

C. VGA Interfacing
VGA means Video Graphic Array. It is a video display
standard. It gives a simple method to connect a monitor with
the system for displaying information or images. VGA has
been widely used as a standard display interface. There is
Fig 6: Area optimized gradient calculation unit [4] more and more need for displaying the result of the process in
real time because of the fast development of embedded system,
especially the development of high speed image processing
algorithm. The screen for a standard VGA monitor contains
640 columns by 480 rows of pixels. An image is displayed on
the screen by turning on and off individually pixels. The
combinations of many such pixels generate an image.

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Figure 8: VGA Monitor Scan Proces
The VGA monitor control circuit uses 5 signals V-sync, H-
sync, Red_out, Green_out and Blue_out as shown in the Figure 11: Simulation result for proposed gradient calculation
below figure 9. unit.

Figure 12 depicts the simulation result for thresholding block.

The gradient value is compared with user defined threshold
value.

Figure 9: The symbol for VGA monitor control[8]

The horizontal and vertical sychronization signals are used to

control the scan rates. H_sync signal control the time it takes
to scan the row and V_sync signal is used to scan the entire
screen. VGA control circuit works at 25.175MHz of clock. Figure 12: Simulation result for thresholding block
Red, Green and blue signals are used control of the image
pixel displayed on the monitor. Simulation result for Sobel edge detection after integrating the
all the modules is shown in figure 13. The final output
IV.TESTING AND RESULTS consists of only two values 0 and 255.

The design of Sobel edge detection algorithm is described in

Verilog. Design and testing of individual module has been
carried out. Figure 10 depicts the simulation results for 3 x 3
pixel generation unit. The input to this module is the pixel
values store in 1-D array. The nine input values represent 3 x
3 window. The output will be undefined till the two FIFO’s
and 9 shift registers are filled.

Figure 13: Simulation result for Sobel edge detection after

integration.

Synthesis report for the existing [3], area optimized [4] and
proposed gradient architecture is compared. The table 2 shows
that the area is reduced 40% and also reduced propagation
delay compared to standard architecture. Because proposed
architecture requires only 2 cycles to compute gradient for all
the direction compared to the existing architecture.

Figure 10: Simulation result for 3 x 3 pixel generation

module.

Figure 11 depicts the simulation result for proposed Sobel
edge detection for compromised delay and area. The inputs for
this block are 3 x 3 pixel generator. These values convolved
with four masks to generate gradient.

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This design of Sobel edge detection algorithm is also v. CONCLUSION
simulated and tested on the cadence tool. The below table 3 This paper presents implementation of compromised Sobel
shows the synthesis report for area, power and delay for three edge detection algorithm is designed, simulated and tested.
architectures. The advantage using our proposed architecture The high level implementation of the project is done using
reduced area up to 15.78%, which reduces the power by an MATLAB. In order to improve the speed and reducing the
average of 10.02% compared to existing architecture [3], and FPGA resource usage the Gradient calculation block is
it also reduces the delay compared to the area optimized modified using proposed architecture. The hardware is
architecture [4]. realized on Spartan 3E FPGA kit. The VGA monitor
controller is developed to interface the FPGA with the
monitor to display the edge detected output on the monitor.
The timing reports of both the existing, area optimized [6] and
proposed architecture are compared. The propagation delay is
reduced up to 51% and also area is reduced up to 40%
compared to the existing architectures [1] [2].

REFERENCES

[1]. R. C. Gonzalez and R. E. Woods, Digital Image Processing,

Pearson Education, New Delhi, India, 2009.

[2]. Rahul R, Gaulkar, Swati R. Dixit and A.Y. Deshmukh “Design of

Different input images and their edge detected images are VHDL based Multi-Direction Sobel Edge Detection Processor”,
shown the Figure 14. The figures A, C, E are the input images International Journal of current Engineering and Technology, vol,
and figures B, D, F are their edge detected results respectively 4, No. 2 pp. 745-748. April 2014.

[3]. Vanishree, K.V Ramana Reddy “Implementation of Pipelined

Sobel Edge Detection Algorithm on FPGA for High Speed
Applications”, IEEE transaction on Electronic Design, 2013.

[4]. Sanjay Singh, Anil Kumar Saini, Ravi Saini,

A.S Mandal, Chandra Shekar and Anil vohra “Area Optimized
FPGA-Based Implementation of The Sobel Compass Edge
Detector”, Research article, Central Electronics Engineering
Research Institute. pp 1-6 .Volume 2013.

[5]. H. Jiang, H. Ard¨o, and V. ¨Owall, “A hardware architecture for

real-time video segmentation utilizing memory reduction
techniques,”IEEE Transactions on Circuits and Systems for Video
Technology, vol. 19, no. 2, pp. 226–236, 2009..
A B [6] Muralikrishna, B.; Raghu Kanth , B Swaroop vemana, V.G ;
“Image Processing Using IP Core Generator through FPGA”,
International Journal of Computer Applications, vol 46 No 23 pp
48-52. May 2012.

[7]. KC Sudeep, Dr. Jharna Majumdar, “A Novel Architecture for Real

Time Implementation of Edge Detectors on FPGA”, IJCSI
International Journal of Computer Science, Volume 8, Issue 1, pp.
193-202, January 2011 .

[8]. Enoch Hwang “Build a VGA Monitor Controller”, Circuit

Cellular. Issue 172, November 2004.

C D

E F
Figure 14: Simulation Result

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