SYSTEM VERILOG

ASSERTIONS
HANUMANTHA RAO G
 CONTENTS

● INTRODUCTION TO SVA
● BUILDING BLOCKS
● SVA TERMINOLOGY
● IMPLICATION OPERATORS
● REPETITION OPERATORS
● BUILT IN FUNCTIONS
● CONSTRUCTS
● ASSERTION DIRECTIVES
● NESTED IMPLICATIONS
● FORMAL ARGUMENTS
 INTRODUCTION TO SVA
● Verification :: Main objective of verification is to verify the design under test (DUT) thoroughly and
make sure there are no functional bugs.
● There are 2 parts we consider to verify the design

1. A constrained random testbench

2. Code coverage tool

● Code coverage make sure all the lines of the design executed at least once.
● Because of huge complexity of the designs, we need to make sure good quality of test bench which
can be randomize.
● These test bench should have self checking mechanisms , because it is difficult to check the each
simulation behaviour and it may prone to human error.
● These checking process are two types.

1. Data checking :: deals with Data integrity.

2. Protocol checking :: It checks the control signal behaviour.

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● Assertions are mainly used for protocol checking, it means to validate the behaviour of the system .
● An assertion is a description of a property of the design.
● Ex :: After the request signal is asserted, the acknowledge signal must arrive 1 to 3 clocks later
● Before the introduction of SVA :: we need to use large code
 BUILDING BLOCKS

● BOOLEAN EXPRESSION :: we need to create the expression required for sequence

● SEQUENCE :: In the design, functionality is represented by combination of multiple logical events.
These events might be simple boolean expressions that evaluate in a single cycle or events that
evaluate over a period of time in multiple clock cycles

sequenc e name_of_sequence ;

< tes t expression> ;

endsequence

sequence s1;

@{posedge clk) a || b;

endsequence
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● PROPERTY :: No of sequences can be combined logically or sequentially to create more complex
sequences. This is called Property.
● We need to provide the clock inside sequence or property.
● Basic syntax for property is ::

property name_of_property;

< test expression >; or

< complex sequence expressions >;

endproperty

● Property is the one which will be verified during simulation. It has to be asserted to take effect in
simulation.
● SVA provides a keyword assert to check the property.
● Syntax ::

assertion_name : assert property (property_name) ;

 SVA TERMINOLOGY

● There are 2 types of assertions.

1) Immediate assertions ::

a) Test expression is evaluated just like any other Verilog expression within a procedural block.

b) Based on simulation event semantics.

Ex ::

Always @(event) begin

assert($fifo_empty);

end
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2. CONCURRENT ASSERTIONS ::

● Based on clock cycles

● Sampling of variables is done in the "preponed" region and the evaluation of the expression is done
in the "observed" region of the scheduler.
● Can be placed in a procedural block, a module, an interface or a program definition.
IMPLICATION OPERATORS

● Implication operator is equivalent to if-then structure.

● LHS of implication is called antecedent and RHS is called consequent.
● When LHS is true then only assertion will evaluate RHS.
● Ex ::

sequence seq;

@(posedge clk) a ##2 b;

endsequence

● In the above sequence, sequence starts on every positive edge of the clock and it looks for “a” to
be high on every positive clock edge. If the signal “a” is not high on any given positive clock edge,
an error is issued by the checker.
● If we want the sequence to be checked only after “a” is high, this can be achieved by using the
implication operator.

@(posedge clk) a |-> ##2 b;

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● There are 2 types of Implication operators

1. OVERLAPPED ::

If there is a match on the antecedent, then the consequent expression is evaluated in the same clock
cycle. Overlapped implication is denoted by the symbol |->.

The implication construct can be used only with property definitions. It cannot be used in sequences.
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● OVERLAPPED WITH DELAY :: We can you the delays(no of clock cycles) after which property should
valid.
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● IMPLICATION WITH SEQUENCE ::
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● IMPLICATION WITH TIMING WINDOW :: we can use timing window, if behaviour was expected within
some clocks
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● INFINITE TIMING WINDOW :: we can use infinite timing window, if there is no time bound for the
response.
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2. NON-OVERLAPPED ::

● If there is a match on the antecedent, then the consequent expression is evaluated in the next clock
cycle. Non-overlapped implication is denoted by the symbol |=>.
REPETETION OPERATORS
● If signal "start" is high on a given positive edge of the clock, then, starting from the next clock cycle,
signal "a" stays high for 3 continuous clock cycles; one clock cycle after that, signal "stop" is high

● Suppose same sequence, when signal “a” has to be high for many cycles it will be difficult to right the
assertion. In those cases we can write these repetition operators.

@(posedge clk) $rose(start) |-> ##1 a[*3] ##1 stop;

● There are 3 types of repetition operators.

1.Consecutive repetition operator [*]

2.Non-consecutive repetition operator [=]

3.Go to repetition operator [->]

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● Consecutive repetition operator [*] ::

If we want to check that a signal or a sequence will match continuously for the number of clocks
specified, we use this repetition operator.

On a sequence ::
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● Sequence with delay window ::
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● It is also possible to provide a window for the number of repetitions.

● After start signal asserted, waits for 2 cycles, then “a” should be high, “a” can be high for 1 to infinite clock
cycles.but after “a” is low, Then after 1 cycle stop will be high.
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● Go to repetition operator [->] ::

● if there is a vahd start signal on any given positive edge of the clock, 2 clock cycles later, signal "a" will
repeat three times continuously or intermittently before there is a valid stop signal
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● Non-consecutive repetition operator [=] ::

Property p26 ;

@(posedge clk) $rose(start) | -> ##2 (a[=3]) ##1 stop ;

Endproperty

● After valid start, 2 cycles after “a” will be high for 3 clocks continuously or intermittently before valid
stop. Here a could be low any no of cycles before valid stop.
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BUILT-IN FUNCTIONS
● $onehot(expression) :: checks for only one bit of expression is high at a time. Returns value 1 if only 1 bit is
high.

● $onehot0(expression) :: checks for 1 bit or none of the bits are high.Returns value 1 if only 1 bit or 0 bit is
high.
● $isunknown(expression) :: checks if any bit of expression is X or Z.
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● $rose(expression) :: monitors the rising edge of the expression. If expression is multiple bit size, LSB bit
will be considered.
● $fell(expression) :: monitors the failing edge of the expression. If expression is multiple bit size, LSB bit
will be considered.
● $countones(expression) :: count no of bits high in the expression. X and Z values are not counted as 1’s.

● $past(expression) :: gives the value of signal “n” clock cycles before.

property system_prop;

@ (posedge clk) ($rose(req) && $past( ! req,1)) |=> ($rose(gnt) && $past( ! gnt,1));

endproperty
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● $stable(expression) :: checks the expression was stable or not compared from current evaluation time to
previous evaluation time. Returns 1 if it was stable.
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● $changed(expression) :: returns 1 if the expression value changed from previous evaluation time time to
current evaluation time.
●
CONSTRUCTS
● AND :: The binary operator "and" can be used to combine two sequences logically. The final property
succeeds when both the sequences succeed. Both sequences must have the same starting point but
they can have different ending points. The starting point of the check is when the first sequence
succeeds and the end point is when the other sequence succeeds
●
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● INTERSECT :: The "intersect" operator is very similar to the "and" operator with one additional requirement.
Both the sequences need to start at the same time and complete at the same time. In other words, the length of
both sequences should be the same.
● sequence s1;

$past( ! req,1) ##1 ($rose(gnt) and $past( ! gnt,1));

endsequence

sequence s2;

$past( ! req,1) ##1 $rose(gnt) ##1 $fell(gnt);

endsequence

property intersect_prop;

@ (posedge clk) req |-> s1 intersect s2;

Endproperty

intersect_assert : assert property (intersect_prop);

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● OR :: The binary operator "or" can be used to combine two sequences logically. The final property
succeeds when any one of the sequence succeeds.
●
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● FIRST_MATCH :: Whenever a timing window is specified in sequences along with binary operators such
as and and or, there is a possibility of getting multiple matches for the same check. The construct
"first_match" ensures that only the first sequence match is used and the others are discarded.
● The first_match operator matches only for the first match out of all possible multiple matches.

sequence seq;

first_match(req1 ## [1:4] req2);

Endsequence

req1 ##1 req2

req1 ##2 req2

req1 ##3 req2

req1 ##4 req2

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● THROUGHOUT :: if we want to test a sequence based on precondition, we use Implication operator.
But in case that precondition should be hold true until total test sequence completes, in those scenarios
will use “throughout” construct.
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● Within :: The "within" construct allows the definition of a sequence contained within another sequence.
● seq1 within seq2
● Ex :: after start is high, i must see ack 1 to 3 three times within 10 clks

Property P1;

@(posedge ck) $rose(start) |-> ack[*1:3] within 1’b1[*10];

property within_prop;

@ (posedge clk) 28 $rose(burst_enable) |=> ( ! slave_busy[*6]) within (($fell(master_busy)) ##1 ! master_busy[*7]);

31 endpropert

\\\
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● Disable iff :: Sometimes if we dont want to proceed the check if some condition is true.
● In that case SVA has a construct called disable iff, it acts like a asynchronous reset to the checker.

disable iff (expression) < property defenition>

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● Expect :: it is similar to wait statement in verilog.
● The expect statement is a procedural blocking statement that is similar to an assert statement and used to block the execution until the
property is evaluated.
● Syntax :: expect (property or sequence) <statements>
● initial begin

#100;

expect(@(posedge clk) req1 ##2 req2) else $error "expect failure");

End

property prop;

@(posedge clk) req1 ##2 req2;

endproperty

initial begin

#100;

expect prop else $error "expect failure");

end
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● Matched :: Whenever a sequence is defined with multiple clocks, the construct "matched" is used to detect
the endpoint of the first sequence.
●
CONT…
● If-else ::
NESTED IMPLICATION
● SVA allows having nested implication.
● These are useful when we multiple gating conditions.
USING FORMAL ARGUMENTS
● If we want to repeat some of the properties, that can be defined with formal arguments.
● Property is bound to a specific clock.