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CPU Interaction With Memory, IO and Cache

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7 views

CPU Interaction With Memory, IO and Cache

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mi86822370
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Computer Organization and Assembly language

Department of CS/IT HU

CPU Interaction with Memory, I/O and Cache


The connections between the CPU and Memory are shown in Figure 6.4. This figure also
includes the I/O (input and output) subsystem. The I/O system will be discussed in subsequent
chapters. The control unit is connected to memory by three buses:

 address bus
 data bus
 control bus

Bus:
It is a communication path between two or more devices.
Several devices can be connected to one bus, but only two devices can be communicating
over the bus at one time.

Figure 6.4: Subsystems of a computer. The CPU, Memory, and I/O subsystems communicate
with one another via the three busses. (Figure 1.1)

As an example of how data can be stored in memory, let us imagine that we have some data in
one of the CPU registers. Storing this data in memory is effected by setting the states of a group
of bits in memory to match those in the CPU register. The control unit can be programmed to do
this by

1. Sending the memory address on the address bus,


2. Sending a copy of the register bit states on the data bus, then
3. Sending a “write” signal on the control bus.
For example, if the eight bits in memory at address 0x7fffd9a43cef are in the state:

0x7fffd9a43cef: b7

the al register in the CPU is in the state:

%al: e2

and the control unit is programmed to store this value at location 0x7fffd9a43cef, the control unit
CU then

1. places 0x7fffd9a43cef on the address bus,


2. places the bit pattern e2 on the data bus, and
3. places a “write” signal on the control bus.

Then the bits at memory location 0x7fffd9a43cef will be changed to the state:

0x7fffd9a43cef: e2

Important

When the state of any bit in memory or in a register is changed any previous states are lost
forever. There is no way to “undo” this state change or to determine how the bit got in its
current state.

Cache Memory in Computer Organization


Cache memory is a small, high-speed storage area in a computer. The cache is a smaller and
faster memory that stores copies of the data from frequently used main memory locations. There
are various independent caches in a CPU, which store instructions and data. The most important
use of cache memory is that it is used to reduce the average time to access data from the main
memory.

By storing this information closer to the CPU, cache memory helps speed up the overall
processing time. Cache memory is much faster than the main memory (RAM). When the CPU
needs data, it first checks the cache. If the data is there, the CPU can access it quickly. If not, it
must fetch the data from the slower main memory.

Characteristics of Cache Memory


 Cache memory is an extremely fast memory type that acts as a buffer between RAM and
the CPU.

 Cache Memory holds frequently requested data and instructions so that they are
immediately available to the CPU when needed.
 Cache memory is costlier than main memory or disk memory but more economical than
CPU registers.

 Cache Memory is used to speed up and synchronize with a high-speed CPU.

Cache Memory

Levels of Memory
 Level 1 or Register: It is a type of memory in which data is stored and accepted that are
immediately stored in the CPU. The most commonly used register is Accumulator,
Program counter, Address Register, etc.

 Level 2 or Cache memory: It is the fastest memory that has faster access time where
data is temporarily stored for faster access.

 Level 3 or Main Memory: It is the memory on which the computer works currently. It is
small in size and once power is off data no longer stays in this memory.

 Level 4 or Secondary Memory: It is external memory that is not as fast as the main
memory but data stays permanently in this memory.

Cache Performance
When the processor needs to read or write a location in the main memory, it first checks for a
corresponding entry in the cache.

 If the processor finds that the memory location is in the cache, a Cache Hit has occurred
and data is read from the cache.

 If the processor does not find the memory location in the cache, a cache miss has
occurred. For a cache miss, the cache allocates a new entry and copies in data from the
main memory, and then the request is fulfilled from the contents of the cache.

The performance of cache memory is frequently measured in terms of a quantity called Hit
ratio.
Hit Ratio (H) = hit / (hit + miss) = no. of hits/total accesses
Miss Ratio = miss / (hit + miss) = no. of miss/total accesses

We can improve Cache performance using higher cache block size, and higher associativity,
reduce miss rate, reduce miss penalty, and reduce the time to hit in the cache.

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