Compact bipolar transistor modeling -

Issues and possible solutions

M. Schroter
Chair for Electron Devices and Integrated Circuits
University of Technology Dresden, Germany
[email protected]
http://www.iee.et.tu-dresden.de/iee/eb/eb_homee.html

Workshop on Compact Modeling, San Francisco, February 2003

Compact Bipolar Transistor Modeling

Contents
• Introduction
• Design requirements
• Model forms, complexity and hierarchy
• Geometry scaling
• Model deployment
• Conclusions

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Compact Bipolar Transistor Modeling

Motivation: accurate models can save a lot of money !

The cost of a reticle set vs technology node

⇒ if “good modeling” saves just one design iteration it has already paid for itself !!

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Compact Bipolar Transistor Modeling Introduction

Introduction
Major applications of bipolar transistors
• high-frequency operation (examples)
• wireless communications: WLAN (e.g. 60GHz), 802.11, Bluetooth, Free Space Optics, Ultra Wide
Band (Impulse) Radio, ...
• wireline communications: OC768, OC192, Ethernet, ...
• automotive: collision warning and avoidance (24-77 GHz range)
• disc drives (using "high-voltage" transistor versions), "standard" automotive
• precision analog ...

Process technologies
• Si and SiGe Bipolar/BiCMOS
• III-V material-based HBTs: AlGaAs, InGaAs, InP, GaN...

⇒ a compact model is expected to cover wide range of applications and processes

But: there is more to design and modeling than just the transistor behavior

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Compact Bipolar Transistor Modeling Design requirements

Design requirements
Examples for the importance of geometry scaling for circuit optimization

• LNA design:
• need to be able to size emitter area for achieving low noise and
high gain simultaneously tD

• frequency divider, MUX, DEMUX ...: NFmin

• proper transistor sizing for both diff pairs and emitter
followers to achieve maximum speed with low jitter, etc. JC
• sizing criteria (e.g., can use critical current density as suitable starting point)

• process variations
• statistical simulation
C’
• matching simulation ijBC C
CBC rCx
rB
• model complexity B’ iT
B CBE
• this equivalent circuit is about as simple as CjS
ijBE E’
designers usually are willing to deal with
• designers want lumped elements values for cir- rE
cuit synthesis and sizing estimates E S

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Compact Bipolar Transistor Modeling Design requirements

A challenging modeling problem: power amplifiers and drivers

⇒ device modeling under extreme conditions
integrated power transistors:
• high current densities at low voltages
⇒ modeling in high-current region
• high voltage swings (e.g., reflections)
⇒ modeling of (3D) breakdown phenomena

• high temperatures due to self-heating

⇒ modeling of (3D) thermal behavior

• high frequency / fast switching

⇒ modeling of charge storage,
parasitic and distributed effects
(PA from: Jack Ma, 2001)

⇒ impact on, e.g., ACPR (caused by distortion), power dissipation (battery life time), jitter,
stability, device/circuit failure time ...

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Compact Bipolar Transistor Modeling Thoughts on model forms: overall requirements

Thoughts on model forms: overall requirements

process development
• include all physical effects
• model parameters without wafers
• rapid eval. of process variations
• “debugging” of process issues

compact simulator
param. extraction • EC topology, equations to
• well-defined, fast, reliable model fit in different interfaces
• using standard equipment • I, Q contin. differentiable
• min. parameter interaction • modular, easily extendable

circuit design
• accurate, valid over wide range
• smooth geometry scaling (for optim.)
• computationally fast and reliable
• easy to understand

⇒ physics-based, geometry scalable, fast model with simple equivalent circuit and fast pa-
rameter extraction
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Compact Bipolar Transistor Modeling Thoughts on model forms: overall requirements

Example for an advanced bipolar transistor model: HICUM

Equivalent circuit and physical effects covered by HICUM/Level2:
• effective internal transistor
• substrate coupling • incl. emitter perimeter injection
Rsu (iT) and related charge (Qf)
S’ ⇒ reduces perimeter transistor
S
QjS
eff. internal transistor to perimeter diode
iTS Csu
rCx • simplifies geometry scaling
ijSC C’ C
,
Q BCx
,,
Q BCx ijBCx Q ijBCi iAVL
• GICCR incl. bias dependent
dS QjCi Qr collector resistance and charge
CrBi
B B* B’ iT • geometry scalable (Rth,Rsu,Cth?)
rBx QjEp r*bi QjEi Qf
• BC (weak avalanche) break-
CEox iBEt ijBEi
ijBEp down, BE tunnelling
E’
rE ∆Tj • parasitic substrate transistor
T
• parasitic isolation capaci-
P Rth Cth
E tances
• thermal network • NQS effects (iT and Qf)
• more features: see www
(self-heating, thermal coupling (via node T))

⇒ existing advanced models offer sufficient choice and flexibility

But: does this really satisfy all (h.f.) circuit design needs ?

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Compact Bipolar Transistor Modeling Thoughts on model forms: overall requirements

Model complexity and hierarchy

HICUM/Level0 S
SGPM/Level0 S

conceptual phase
CjS CjS
ijSC rCx gjSC
C’ C C’ rCx C
CCox CjCx ijBC CjCi CdC iAVL ijBC
CCox CjCx CjCi CdC
B’ B’
B rB CjE CdE B rB CjE CdE
CEox CEox
ijBE E’ ijBE E’
∆Tj
rE rE

P Rth Cth
E E

HICUM/Level2 SGPM/Level2
rsu
S’ rsu
QjS
S S’
Qsu QjS
S
iTS
rCx Qsu
ijSC C’ C iTS
rCx
ijBCx ijBCi ijSC C’ C

optimization and validation

QdS QjCi QdC iAVL
CrBi ijBCx ijBCi
QdS QjCi QdC
B B* B’ iT
rBx QjEp rBi
B B* B’
QjEi QdE iT
rBx QjEp rBi QjEi
QEox iBEt QdE
ijBEp ijBEi
QEox iBEt ijBEi
E’ ijBEp
rE ∆Tj E’
rE

P Rth Cth
E
E

HICUM/Level4
C’ C’
Tkn T2n T1n

E’ E’

*
Tk3 T23
Csu
rsu
S special applications
B

C’
C’n ∆rCx

S’
C’c1 ∆rCx

S’
C’ck ∆rCx

S’
C’w

S’
rCx1 C
(e.g., distributed effects)
B
Tk2 T22 T12
Tn Tc1 TcK Tw

E’ E’ E
C’ C’
Tk1 T31 T21 T11

E’ E’ E’ E’
y symmetry
lines

Note: model generation is based on HICUM/Level2 parameter extraction only !

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Compact Bipolar Transistor Modeling Geometry scaling

Geometry scaling
dealing with different device designs . . .
bKB bpo bpm bov bE0 bs bec bKC

silicide silicide

n+
ws p+ poly p+ poly
SiGe n+
p+ n+
SiO2 SiGe p+ wox
wox SiO2
wCi bsic n+
bsic n+
wCx sinker wCi
n-SIC n-epi wCx sinker
p+ n-SIC n-epi

n+ buried layer n+ buried layer

wj wj
b b

. . . and configurations
C E B

B E B C C E B E C

C BE B E B E B E B C
B E C E B C E B E C E B E C E B E C

. . . is accomplished by parameter generation and sizing tool TRADICA, but . . .

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Compact Bipolar Transistor Modeling Geometry scaling

Trends in Communication Systems ...

... with impact on circuit performance (noise, linearity/ACPR, ...) and modeling
higher frequencies (Broadband) higher integration (SoC)
substrate coupling:
CMOS

thermal effects and

parasitic h.f. effects: substrate
coupling:
intra device
inter device metal

Pi SiO2

Si substrate

e.g., heat sink

⇒ need accurate modeling of distributed (3D) electro-static, -magnetic, and -thermal effects
for reducing design iterations and cost

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Compact Bipolar Transistor Modeling Model deployment - major obstacles

Model deployment - major obstacles

• parameter extraction
• need methodology for extraction single "specific" parameter set for geometry scaling
(single device extraction is only the beginning...)
=> need reliable methods and implementation for production use
• need proper test structures (transistors and some others)
• minimize extraction and model/parameter generation effort

• model implementation
• so far major obstacle since dependent on simulator interface (and vendors)
• solution for model evaluation: distribution via standardized description language (e.g., Verilog)
• solution for model integration: model compilers (fast implementation from description language)

• education of modeling and design engineers

• model features and main application area
• model limitations

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Compact Bipolar Transistor Modeling Conclusions

Conclusions

• mask cost explosion increases necessity for accurate modeling

• geometry scaling is mandatory for cost efficient design
(need to cover many process variants and transistor configurations)

• model hierarchy provides designers with the demanded flexibility

• mandatory precondition for modeling engineers: no additional parameter extraction effort

• a variety of open issues exist for h.f. compact transistor modeling and applications
• mostly 3D electro-static, -magnetic, -thermal problems
• related more to external transistor rather than internal behavior
• model deployment bottleneck: extraction and implementation
• existing advanced compact bipolar transistor models offer sufficient choice

There’s no "one hat fits all" model and "push button" extraction method

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Compact Bipolar Transistor Modeling Availability of HICUM/Level2 V2.1 in Circuit Simulators

Availability of HICUM/Level2 V2.1 in Circuit Simulators

(Please contact simulator vendor for details and the latest status of availability)
simulator first release latest release comments

ELDO-RF 10/99 9/02 ELDO v5.8_1.1 (AMS 2002.1) with externally accessi-
ble thermal node
10/99 11/01 • SPECTRE 4.4.6/4.4.7 with HICUM2.1
SPECTRE-RF
• (10/99: CNXT ref = HICUM2.0)
ADS 7/00 2/02 can be combined with ICCAP

Smart-SPICE 11/00 11/00 can be combined with UTMOST

APLAC 10/01 10/01 APLAC 7.62a

HSPICE 2/01 2/02 version 2001.2 with HICUM2.0; AURORA compatible

TEKSPICE 8/02 8/02 various numerical improvements

Xpedion upcoming

stand-alone kit / 4/02 4/02 replace DEVICE as reference simulator

SPICE3F5

Apache NSpice, HSIM, MicrowaveOffice: code sent as per request, implementation in progress
• Various (other) proprietary simulators (ASX (IBM), ...)
• Verilog-A version of model code (in progress)

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Compact Bipolar Transistor Modeling Geometry scaling: TRADICA overview

Geometry scaling: TRADICA overview

Process specific parameters Design rules

Process control sheet resistances,
monitor capacitances per area,
sat. currents per area,
(PCM) data ...

Transistor configurations
E width and length, number
of E, B, C stripes, location ... critical bias points
TRADICA ⇒ transistor sizing

model characteristics
(fT, fmax, NFmin ... as
model parameters function of geometry and
• device libraries bias)
• for specified bias points

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