5

FUNCTIONS OF COMBINATIONAL LOGIC

Basic adders
Half Adder (HA)
Half Adder is a logic circuit for the addition of two one-bit binary
numbers. Half adder gives a sum (s)and carry (c) on its output.
The symbol for Half Adder is

A
Inputs H.A. Outputs
B

Fig. 5.1

The logic circuit for HA is

A
C(carry)
B (C= AB)

S (sum)
(S= AB+ AB)

Fig. 5.2

Aand B are inputs. The carry (c) output is produced with an AND
gate. The Sum (s)output is produced with an Exclusive OR gate.
The truth table for HA is as follows.
 FUNCTIONSOF COMBINATIONAL LOGIC 169
Table 5.1
Inputs
outputs
A B
(S= AB+ AB) (C= AB)
0 0
1 1
1 0
1 1
1

Discuss the operation of aHalf Adder (CU Nov, 2015)

Using NANDgates construct an HA.
Ans:

4 B

C= AB

B
B- AB

AB
1
s=(B AB) (A-AB)
A-AB

Fig. 5.3

S=(B-AB{B AB) using De Morgan's theorem

= B AB+ A-AB
170 EECTRONICS-ll

-BAB+A-AB
=B(A +B) +A(A +B)
= BA + BB+ AA +AB
= AB+ BA
Full Adder (FA)
Full adder is alogic circuit that can add three bits at atime.
are hree inputs. Sum and carry are outputs. The additional There
used here is for handling input carries. input
When we want to add two binary numbers, each having
twO Or
more bits, the LSBs can be added by using a HA. The carry resulted
from the addition of LSBs is carried over to the next column and
added to the two bits in that colum.
The block diagram or symbol is
A S
B F.A.
out
in

Fig. 5.4

The logic circuit ofaFA is as follows

 171
FUNCTIONS OF COMBINATIONAL LOGIC

A B C in

AND

(AB+AC+BC)
|AND OR
Carry out

JAND

Sum S = A BC,
Hx-OR
Fig. 5.5

Truth table of FA is as follows

Table 5.2

Outputs
Inputs
B Cin Sum S Carry Cout
A
0 0
1
0
1 0
0
1
0
1
1
0
1
1
172 ELECTRONICS-II
Here A, B, C are the three inputs. (C represents any carry
generated by the previous stage). Sum and carry (out) are the outputs.
the next stage.
Cot IS the carry output to be added in to
Sum S=ABOC
ABC
= ABC + ABC + ABC +

Carry output C.
out
=ABC + ABC + ABC + ABC
= ABC+ ABC + AB(C+C)
- ABC+ ABC+ AB [+C=1]
= ABC+ A (BC + B)
= ABC + A (B+C)

= ABC+ AB + AC= B(AC+A) +AC

= B(A +C)+AC [:AC +A=A+C]
C = AB+ BC + AC
out

3. Construct a FA by using two HAand an OR gate

S
in
S
H.A.
C
A

H.A.
Cout
B C

Fig. 5.6
Parallel binary adders
A single full adder is capable of adding three one bit numbers or
two one bit numbers and an input carry, But when we have to add
binary numbers with two bit, an additional full adder is to be used.
 UNCTIONS OF COMBINATIONL LOGIC 173
Example

+ 0 1
1 00

Heretwo adders are required for 2 bit numbers.

Similarly for two
it binary numbers, four adders are to be used.
Exarmple
Carry from right column
1 1
+ 1 1 0 1
1 0

Carry from third column becomes a sum bit.

For 8 bit numbers, 8 adders are required.
Carry output of each adder is connected to the carry input of the
t higher - order adder.
r bit parallel adder
Afour bit parallel binary adder is as shown in figure.
A, B, A, B, A, B, A, B,
Co

A BC A BC A BC. in
A BC in

SB FA(4) FA(3) FA(2) FA(1) (LSB)

C COut C Out

C
S S, S, S,
Fig. 5.7
174 ET
The numhers being added are writen as A, A, A A and 9,
f the
B
B Vumhers form the least significarnt bits (1.SBs)entered tu 4tt
numhers are represented hy A, and B T hese are in to
first full adder FA Here whatever the carry takes plae te
transfermed to the FA2) Carry output of cach FA s
carT input of the next higher-order adder. The next hipher
A. and B. are presented to the FA(2) and so on. Other
oerations are repeated in all full adders. Thisresults in surn bts
S.. S, andS, The output carry fron the left most full. adder
the most significant sum bit. The final surn appears as a 5digin s
besSRIE
S. S. S
For example, when we want to add two 4-b1t numbers 1011 and
T101. the LSB of twonumbers 1and 1are entered in to the firt fut)
adder FA(l). The sum output S, is 0 and the carry output C. is 1
Cary output is transferred to the second full adder FA(2) as a thurd
input.
Inaddition to this input, the second column bits of
land 0 are entered in to second the two number
FA(2) as inputs. The sumn of these S
Is 0 and the carry output 1is
This carry 1.0andl(third column transferred to third full adder FA(3
full adder FA(3). The sum inputs) is connected to the third
output S, is 0 and the carry output I s
transferred to the fourth FA(4).
bits of the two numbers 1and 1This carry l and the most sign1ficant
are entered in to the fourth full
FA(4). Then it results the sum output adder
S, as l
becomes the mostsignificant sum bitS,. So the and the carry output
resultant sumis 1100

0
Carry from right column

S, S, S Ss
+Cary lorm nght column becomes a
sum bit.
 COMBINATIONAL LOGIC 175
FUNCIONS OF
Where this full
Ans:In asimple
adder and parallel adder systemis applicable?
ovide the
voting systemthat can be uscdto simultaneously
number "yes' votes and the number of 'no" votes.
omparators
Acomparator is a logic circuit, uscd to comparc the
two binary numbers. A comparator circuit magnitudes
determines whether
tumbers are equal or not,
uality
An exclusive NOR (X-NOR) gate is used as a basic
comparator.
cause its Output iS a l only if its two input bits are equal. 1.e., the
aMput is a Iit and only if the input bits
coincide.
Basic comparator operation is as follows.

1 (; input bits are equal)

1
D
1
are equal)
1

Fig. 5.8
For example :Consider two four bit binary number A, A, A,A,
i B, B, B, B, They are cqual if and only if A, =B,, A, = B, A, =
nd A, = B,.Thus equality holds when A, coincides with B,, A,
Vitcides wih B,, A, coincides wilh B, and A, coincides with B,.
e implementation of this logic.
176 ELECTRONICS-Il

Equality = (A,OB,) (A, OB,) (A, OB,)A, OB,) can be

shown as in figure.
A
A, OB,
B,
A, A,OB,
B. -
.Equality =(A, OB,)
A
A, OB (A, OB,) (A,OB,)
B, (A, OB,)
A A, OB,
B,

Fig. 5.9
Problem
For binary inputs 01 and 10to the inputs of comparator, determine
the output by following logic levels.
A,=1: 0

B,=0
Low indicates
A, =0: not equal

B, =1
A, A, =01
B,B, = 10
Fig. 5.10
5. What are the comparator outputs when A, A, A, A, = l001and
B,B, B, B, = 1010
 177
HIMTONR OF COMUNATONAL LOGN
Ans:

(OMP

Fg.5.11
A<B outputis HIGH andthe other outputs A>Band A=Bare
LOW.
Decoder
idoat
A
decoder is a logic circuit, which identifies various combinatiOns
of input values andgenerates an outputcorresponding to cach of the
input combinations.
For example consider a 2 to 4 decider. It has two inputs (say A
and B)and four output lines.
Table 5.3

Inputs Output
() () 1 0 )
() () ()
) ()
() )

Decoder is a logic circuitthat convertsan Nbit binaryinputcode

in to M output lines such that only onc output line is activated for
each one of the possible contributions ol inputs.
The basic function of u decoder is to detot the preNence of a
178 ELECTRONCS-I
dote
specified combinationof bits(code) on its inputs and to indicate that
presence by aspecified output level.
Here Moutput lines mean one to 2N lines. This indicates the
presence of one or more n-bit combinations in the output.
Basic binary decoder
Decoding operation can be performed by simple AND gate decoder
excited with the 4BCDbits as shown in figure.
When the applied input bits are
A, A, A, A, =0101 (decimal 5) the gate is activated, producing
an output 1. The output line is named as "line 5."
1=A,
0= A, Line Sis Y=A, A, A, A
l=A
0= A,
Fig. 5.12

The figure shows as simple decoder.

(Note : LSB is the right most bit in a horizontal arrangement and
the topmost bit in a vertical arrangement).
4-Bit decoder
To decode all possible combinations of 4-bits, 2 = 16 decoding
gates are required. This is known as 4-line-to-16-line decoder. There
are 4 inputs and 16 outputs. For any given code on the inputs, one of
the sixteen outputs is activated. So it is also called as 1-of-16 decoder.
 doded pen od ypeudk
178 ELECTRONICs-Il

specificdcombination of bits (codc) on its inputs andto indicate that

prescnce by a specified output level.
Here M output lines mean one to 2N lines. This indicates the
presence of one or more n-bit combinations in the output.
Basicbinary decoder
Decoding operation can be performed by simple AND gate decoder
excited with the 4BCD bits as shown in figure.
When the applied input bits are
A,A, A,A, =0101 (decimal 5) the gate is activated, producing
an output 1. The output line is named as 'line 5.
1=A
0= A, Line 5 is Y= A, A, A, An
l=A,
0=A
Fig. 5.12

The figure shows as simple decoder.

(Note : LSB is the right most bit in a horizontal arrangement and
the topmost bit in a vertical arrangement).
4-Bit decoder
To decode all possible combinations of 4-bits, 2 = 16 decoding
gates are required. This is known as 4-line-to-16-line decoder. There
are 4 inputs and 16 outputs. For any given code on the inputs, one of
the sixteen outputs is activated. So it is also called as 1-of-16 decoder.
 FUNCTIONS OF COMBINATIONAL LOGIC
179

Table 5.4
Decimal Binary inputs
digit A,|A, A Decoding Active low outputs
|A function 0|1|2345\67}89|10 1112|13|14|15

o00A, A, A, A, 0|1| 1|1||U 1 1

000
1|A, A, A, A| 1|0|1 1|1||
1

2 0 A,A, A, A| 11|0| 1
3
1A, A, A1
4 0

5 1
01A,A, A 1

6 1|0A, A, A, A|1|1
7 0 1 |A, A, A, A 1|1|1| 1|1|1
8 00A, A, A, Ag 1 01|1
9 1A, A, A, A, 1|1|1| 1 1

10 1 o A, A, A, 1| 1|0 1 1

11 0 1A, A, A, A| 1| 1|1 1

12 00A, A, A, Ao| 1| 1 |0

13 A, A, A, Ao 1|10
1
14 1 A, A, A, Ao
15 1A, A,A, A 1 |0

For the above active low outputs 16 NAND gates are required.
(Active low means 1 for 0 and 0 for 1)
BCD to Decimal decoder
6 Construct a decoder for 4 inputs and 10 output lines (0 to 9)
using AND gates.
Ans: If AND gates are used output is active high. (1 for 1 and 0
for 0)
 180 ELECTRONICS-II
First of alldraw the truth table
Table 5.5
Address Selected
A, A, A, A, line
0
0 1 1
0 1 2
1 1 3
0 1 4
1 0 1
0 1 0 6
1 7
0 0
1 0 0 1

Here any of the output lines is activated (giving output 1) when

the correct BCD code is applied as inputA, A, A, A, called address

A, A, A A0 Line

Fig. 5.13
 181
FUNCTIONS OF COMBINATIONAL LOGIC
fthatline. An invalid code provides 0 output. The circuit given
elowis called as 4to 10 line decoder or 1 of 10 decoder. Because a
-bit address selects 1 of 10 output lines at atime.
Note: To select 1 of 16output lines, 6 more AND gates would be
added.)
Note: Inthe abOve figure, an Active high output is produced. ror
active lowoutputs NAND gates are to be used).
BCD to 7-segment Decoder
IC 74471s often found useful for displaving the decimal numerals
sing LEDs. It converts a BCD nibble (4 bits) in to an output that can
irive a seven - segment LED display.
Seven segment LED display is made of seven Light Emitting
Diodes. Table 5.6
Segments
Digit activated
a
a, b, c, d, e, f
1 b, c
K a, b, g, e, d
K 3
4
a, b, g, c, d
b, c, f, g
a,c, d, f, g
6 c, d, e, f,g
d
a, b, c
a, b, c, d, e, f, g
9 a, b, c, f, g.
Fig. 5.14

Each segment of LED that emits light when current flows through
Anexternal driving circuit is required to provide a LOW or HIGH
evel voltage for the activation of a given segment. When a level
forward
oltage is applied to a segment input, that particular LED is
iased and current flows through it.
he 74LS47 BCD - to -7 segment Decodor
7
7447 is an IC device that decodes BCD input and drives a
(shown
egment LED display. Here all of the outputs are active LOW
y the bubbles).
 182 ELECTRONICS-Il

LT IS for lamp test. RBI 0S for Ripple Blank1ng input. BI for

Blanking input and RBO for Ripple Blanking output.

BIRBO b BI/RBO

BCD ab
inputs

LT LT
RBI a RBI

GND

Fig.5.15

Figure shows the logic symbol. When a LOW is applied to LT

input anda HIGH is applied to BI/ RBO. all of the seven segments
in the display becomes turn on.
The use of Lamp test is to verify that no segments are burned out.
Encoders
An encoder is a device which converts familiar number Or symbols
in to coded format, Encoder is a logic circuit that perfornms the reverse
operation of the decoder.
Encoder has anumber of input lines. only one of which is activated
at agiven time. It produces an N-bit output code depending on which
input isactivated at a given time. It produces an N-bit output code. In
M inputs only one is HIGH at a time.
 LOGIC 183
TUNCTIONS OF COMBINATIONAL

The Decimalto - BCD Encoder

+ 5V

A, A, A A,
Fig. 5.16

Here switches are push-button switches similar to that of pocket

calculator. When button 4 is pressed, A, and A, OR gates gets HIGH
inputs. Sothe output
A,A,A,A, =0110
184 ERTRONNCS Il

If button 7is pressed, A, A,A,A, = l011

The alyove encoder is a10 line -to -4 line encoder. The logic
symbol for a decimalto BCD encounter is as shown below.
DEC /BCD

nhno
GIg
euisa
sandui 2=2
22 = 4
2'= 8

Fig. 5.17
The BCD (8421= 2 22 2' 29) code is as shown in the table given
below.
Table 5.7

BCD
Decimal
A, A, A, A
0 0
1
2 0
3
4
5

7 0
 FUNCTIONS OF COMBINATIONAL LOGIC 185

Herethe MSB of A, is 1 for decimal digits 8 or 9. So an OR is

pliedforA,.
A, =8+9
similarly for A, bit, the decimal digits 4, 5,6 or 7are ORed to get 1.
A, =4+5 +6+7
A, =2+3 +6+7
A,=l+3+5+7+9
To implement alogic circuitry for encoding each decimal digit to
BCD code we require four OR gates whose outputs are A A, A

(LSB)
A,

2
3

4
5
6
7

(MSB)
Fig. 5.18
If input line 7 becomes HIGH (all other lines are LOW) then A,.,
, and A, produces a HIGH on its outputs. A, become LOW. Now
CD output will be A, A, A, A, = 0111 for decimal 7.