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Assignment No.2

Assignment No.2

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Vinay Bansode
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0% found this document useful (0 votes)
7 views1 page

Assignment No.2

Assignment No.2

Uploaded by

Vinay Bansode
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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Sinhgad Technical Education Society’s

SKN SINHGAD INSTITUTE OF TECHNOLOGY & SCIENCE


(Affiliated to Savitribai Phule Pune University, Approved by AICTE and NAAC Accredited with ‘A’ grade)
Gat No. 309, Off Pune-Mumbai Express Way, Kusgaon (Bk.), Lonavala-410401.
Department of Information Technology

Assignment 2
UNIT -2: Combinational Logic Design
Q.1 What do you mean by half adder?
Q.2 What do you mean by full adder?
Q.3 Design full adder using logic gates
Q.4 State the difference between half adder and full adder
Q.5 Draw truth table and logic diagram of full substractor
Q.6 Explain in detail look ahead carry generator
Q.7 Draw a neat circuit diagram of BCD adder using IC 7483 and explain
Q.8 What is multiplexer tree? Explain
Q.9 Design 16:1 multiplexer using 4:1 multiplexers
Q.10 Design 4:1 multiplexer using 2.1 multiplexer
Q.11 Implement the function using 8:1 multiplexer
F(A,B,C,D)=∑m(0,2,3,6,8,9,12,14)
Q.12 Implement full adder using 8:1 multiplexer and draw the diagram
Q.13 Design full substractor and full adder using multiplexer
Q.14 Implement the function using 8:1 multiplexer
F(A,B,C,D)=∑m(0,1,4,5,6,8,10,12,13)
Implement the function using 8:1 multiplexer
Q.15 F(A,B,C,D)=A’BD+A’BD’+ACD+B’CD+A’C’D
Implement the function using single 4:1 multiplexer and few logic gates
Q.16 F(A,B,C,D)=∑m(0,2,5,6,7,9,12,15)
Implement the function using 8:1 multiplexer
Q.17 F(A,B,C,D)=∑m(0,1,2,3,4,5,6,8,9,10,12,13,15)
Q.18 What do you mean by priority encoder
Q.19 Write short note on :3 to 8 line decoder
Q.20 Design 3-bit binary to 3 bit gray code converter using 3:8 decoder
Q.21 Design BCD to Excess-3 code converter
Q.22 Design and implement binary to gray code converter using logic gates
Q.23 Design full adder using 3:8 decoder
Q.24 Design Full Subtractor using basic gates.
Q.25 Differentiate Multiplexor & Demultiplexor.
Q.26 Design BCD Adder using binary adder IC 7483.
Q.27 Implement following using IC 74138 Decoder
y0 (A, B, C) = ∑m(0, 3, 4)
y1 (A, B, C) = ∑m(0, 1, 7)
y2 (A, B, C) = ∑m(0, 5, 6)
y3 (A, B, C) = ∑m(0, 4, 7)

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