Fa ea Ne, es DATA BUS ed for data 110% m a °° he aa bn «opt i ee CPU a pest deviss swell as 8 bit dats, but at AHA hs, As microprocessoe has only 8 da, paral. On these data fines, data canbe ion ne aman 9 of a OO on he dls ee tes dau Hines s0-808S-is-a B bit microprocessor A INTERNAL DATA BUS 2 ren sie owns dls between one da He 0d ime fn. General purpose registers, Inston register, Arithmetic logic unit, Aecumolatcr, Flags and Temporary register have been connected to this data bus in a bidirectional 2.5. BLOCK DIAGRAM OF 8085 microprocessor. Tis microprocessor is capable of addressing 62K of memory. Ths microprocessor is manufactured on a single LSI chip using NMOS nology. Iisa 40 pin IC package. The Intel 8085 ses a single +5 V d.c. powet supply its operation. It can operate with a 3.14 MHz single phase clock. The clock cycle is of sec. The block diagram consists of basically the following units, Timing end control unit as shown in Fig. 2.1 il discuss each block separately, ch reine meal Purpose Registers, There atest 8 bit registers B, C, D, E, 1. L eset contains 8 Nip-lops hence, each register ean store maximum & Bit (1 Lyx da Fr soring dat rete hn 8 bi, tee egies ae med inp airs. There are thiee 8 pir DE pai HA pic yee imam 16 bit of dia 2 Byte) -52 Accumulator ti ako 8 bis regiyer ‘tore maximum 8 bit of data oe — pen pe aE kof eB artes ssa toc Halvays tak first 8 bic number trea aoe nomi accumulator. It wl eespmcarn 308 P HERP HER PNi MERE SN MR elt in ALU ae storey San 8 LSBs of ee a 4} operation 9 prom ania an 8 i registers Ws and Z. Bag, 3, Temporary Ma These feuiter tied only BY the ser for eZ pair can be used by the obit of cl rs-can be nk use these 8 wae = roprocessor 8085 bi vit A This EX-ORing of two $ bit aumbers (a) ANDing, ORing 1) Inveting 8 bt number (©) Comparison of two 8 bit number \€ @ Rowing $b curber towards leith, with or without cary. Sones. Flag Register or PSW (Programm Status Word). PSW is & bit register which 2bvains& flip-flops. Bit DS, D3 and DI of register are not used, rest of five flip-flops are called as status flags as shown in Fig. 22. When microprocessor performs arithmetic and logical operation in ALU, is obtained in ALU. The status of this result is copied into these status ta present in PSW register is called as ferent status flags ate deseribed below Sy MSE is iid iw ayia 94 ae Te as Similarly when microprocessor c sim owes peroms sbiraon of two @ bit numbem(e-) (0) > te aoa teow ; wil be aero hence CF = 9 TOW required for Performing the subtraction (ry) eae borrow equal © 1 59 C=, MS Subtraction ( 9) by taking additions!————s aecealary carry (AC) ov Halt carryfag, The satus of AC fag 6 simile: © ea Seep tat A Hag wil dct te sus of 4 LSB it sates status of only iy Party ag (P), Pay (P), zero 2) and sig (S) Mag indicates sta ra a ul ta “ALU Panty i umber of oe’ it (0) in he esl f see coin the 8 LSB’s of fsa is od number (3,5. 7 ~) then ibis aa dd hi nie ad P= 0. I mber of 1's bis 8 LSBs of relieve Sate (2.4678), thm i calle eve party res and P = 1 ivy Zero fag (2), all he 8 5B of he esl bined in ALU ae zero Fe. (0000 (000), = 00H then 2 = 1 TF anyone or more dan ove bits one, them results non-zero Ze, from OF Ht FFI Hence, 20 (0) Sign flag (S). When microprocessor performs any arnetc o logical operation Stevo # bt aumbers then the esis obained in ALU Sign flag will dinecty Sopp MSB of # LSI of the est ALU. (a) ie te result obtained in ALU is unsigned number then there is no ise of sim fag (0) tthe rent obtained in ALU is signed number but out of the range of (+127), {0 C-128),, then sign fag will not give correct sign of result. Hence itis of no (© If the result obtained in ALU is 8 bit signed binary number with in the range from (+127)p to (-128)py then sign flag will give correct sign of result. If S = 0, then result is positive ICS = 1, then result is negative. 2.5.6. Instruction Register (IR) and Instruction Decoder (ID). Microprocessor 8085 has 8 bit instruction register which can store 8 bit number as shown in Fig. 23. TReTRUCTON mecister 0) t THSTROCTION DECODER (co) Subang Fig. 2, Insrcon restr and Instruction Secoda™ ——stn i EN me raaretion decoue® (I ed 10 ach ID output i, . gee DS 85 (YoY ts, Each cca na oF 8 pups Ee 56 com ular operation. So The 8 ing Ere controlled BY these no me 8 ang whieh is given 8S inp erate conto eef the 255 ID output are ; Da SD output generate seen he acti 256 coool ‘one [D cir 2p scl om ing nae ts as a pointer t0 the next 2.57, 16 Bit Rewsters © program counter Ms of the memory location bi ate a points 10 the nex {the exact number by vega counter (FO) THC aan xd and always conta stasion to be excel and 2775 Treg, by the Proce e plete ins! ns the 16 he proc 2, The oa eae es fetched the COMIC’ jnstraction®, for example, for fsouction afer the pres" AS TAT anu of he In ic updates the hich de processor up depend ire bye instruction, i UDK vd Ses serum i updnes the PC By one a area ofthe Gead-write memory (RAM) in ‘The’ Stack pointer (SP). The stack is a0 bitalston, mote fist ema ih emery stration re Ick ei position (Where the fit i ron assed i te RANTS CT atytions fil memory positions in wranaton stra) afew, task aes he ast bye written onto the stick re Suck pine einer nos he ws of he lst byte wat ris eae aTeE Tp Stack a7 Sack Top. The Stack pointer is decremented aay when ds ed oot fom he sek proaressivey decreas 2.58. Interrupt Control, This unit is responsible for enabling and disabling of Interrupts. There are five hardware intecupts INTR, RST 5.5, RST 6.5, RST 7.5 and Trap. 259. Serial VO Control. With microprocessor 8085 parallel data transfet is possible Shoup data lines Dj-D,, Buti we want 10 send out data serially or if we want serial data inthis can be done tough SOD and SID pins of microprocessor 26. PIN CONFIGURATION Microprocessor BIBS is «40 pin IC. Fg. 24 Sse folong MS Me Pin configuration of Inte 8085 A. The various pins are discus‘ oe na f é + X, and X, (Pin 1 and 2). Th Pitt tpt sti sis ittyy 2, Pr conan 6085 A ss ae the input pins of microprocessor. These terminals 1 oscillator which drives the interoal cireuitry of the microprocessor to produce a suitable clock. The microprocessor operates at half of the ‘ecillator frequency. Generally crystal oscillator is used. The clock generation circuit is shown in Fig 125, The frequency at which microprocessor operates is half of the crystal frequency. Crystal frequency of 8085 is 6.28 MHz. So the operating frequency is 3.14 MHz. —a —— F028 RESET OUT (Pin 3), This is output pin of microprocessor. This signal is given out to reset all external devicesi (tie inst iM sssor and known a8 estat we int Wns gt $5 Location = RST 65 Location RST75 Location ae request signal. It is used as in ques in 30, i a EE ny. When it goes hah | ‘uspends the normal sequence of aera ero oes ot cere is content. It ra mieroproceson executes Ine TOpL SeIVCe FOONE =; dlterrpt scknowcige bar) Pin 11). Its Oulput pin of snictopemessstiy a ner esse Toy sigh is seat on this pin to acknowledge AD,-AD, (Pin 12-19). ime mulilexedaddressfdata bus Ze., these are used as res wel a ata bus These are used forthe last significant 8 bit of the memory sis UO ass ds heft lock eel ofa machine cyele. Again they are ssed fo aa daring second yd til cok cyl. So, during the first clock eycle the least ‘VSS (Pin 20). Ground reference. mae AeAyg(Pin 21-28), As phe bs : ‘“ignificant bits of memory ad mee 0 one crane dress or 8 bit of VO address. we foc the mos‘Opcode Memory Memory VO reod VO write Interrupt acknowledge HALT HOW RESET Ea where Z= Tristate (High impedance) X= Unspecified When an ouput is wit, it means that tis neither in a“ nr in in a high impedance state. 1 isin effet, disconnected from the system \Aadress Latch Enable (ALE) (Pin 30). Ouput pin of microprocessor. It goes high ‘uring first clock eycle of « machine eye” and enables the lower 8 bits of the adress to be latched either into memory or extemal device state but is WR (Write bar) (Pin 31). This s a write consol signal (ative ow. 18 ompat in of microprocesor. When it goes low the data on the dita bus s writen ino selected memory or HO device. RD (Read bar) (Pjn 32), This is 2 Read contol signal. It is oxtput pin of tmicroprpcessx, This signal indcaes that the data ito be read from the selerted VO or memory 10/M ,(npuvOutputy(Memory) (Pin 34). I is output pin of microprocessor. It is a satay signal Which Gistoguishes whether address is for memory or UO. When it goss high th eres on the addres bus is for UO devices, When it gocs low the ads on the address bus is forthe memory. If 10/M = 1 VO device is selected. 1o/M ‘Memory is selected. Ready (Pin 35). This pin is used by the processor to check whether the VO device is ready to send or receive data. If ready is high peripheral is ready and if itis low microprocessor wails til it goes high. Microprocessor uses this signal for synchronisation with the slow devices. Sa ae TiN OoVCC (Pin 40, is +5 V power sup Arachne tat misopreceso! 808i faving ADy-ADy Bus Which i wed fr sending adres as well as data, These are used forthe lower 8 bits address as well as ata, Now during the frst clock eycle adres i transferred on these lines and data during second and thie cock eyeles. Therefore, during the fist clock cycle lower address. mus be latched (Otherwise A,-A, will be lst. i. 26 shows a schematic that uses alach and the ALE signal to demultiplex the tes. The bus AD,-AD; is connected asthe UP fo the latch 74LS373, As we know latch 2 basically 4 Mip-op, whose Truth table is shown in Table 2.3, Table 2.3, Qh (Previous O/P) ° ‘The ALE : Sigal is coma rounded, “OPE 10 E (Enable pin of rata In the first clock eye xj | ‘means that the output 80S high, when ALE ic 4: arabe at yas PES scone pp ALE Io high the latch is enabled, Thin put data, i During the second an So the address is latched and is Output control OC is id fs disabled. 1¢ means tha third clo Cycle ALE he =e ALE goes 2 DD, ‘MPU remains the eset When ALE, 4s low, the latch one and data is, available on28 Domutpeng ne Bis ABAD, 28. INSTRUCTION CYCLE For executing an instruction, a microprocessor fetches the instruction and executos tte time taken for the execution of an instruction is called Instruction cycle. An instruction cycle consists ofa Fete rece Cycle} The execution oF any “A program consists of a sequence of READ and WRITE operations of which eacn transfer a byte of data between the SDSS A and a particular VO device aes oF memory fires. These READ and WRITE operations ae the only communication between the _procesor and the other components, and areal that is necessity wo execute any instruction program 21. Mada Cycle, Each READ of WRITE operations ofthe 8085 A is refened as Machine Cycle An 8085 A insirction’s execution consists ofa nunber of machine es These cyles vary from ove 10 five (M, to M,) depending onthe istrvton. Es ine eyele consi a numberof clock cycles (also referred 1 as Fates) (The fst gale wil be executed by either four or sx clock periods andthe machine yes Patodsj The BOKS A machine cycle hasbeen shown i‘fom the memory are data or operand address whereas inthe cave of fetch operation, {isan opcode. In some insrvtions the write operation is erfones. Inthe we ation data are seat from the CPU to the memory oF to an exp device So execute operation Iay also consists of one or more read of write cycles. Fig. 29 shows the istacton yele, which contains fetch cycle and exccute cycle a Bina iG CONTROL SIGNALS ‘As we know that RD (Read) is «conto signal Because this signal is used oth for feading memory and for reading an input device, iis necessary € generate to different Read signal : one Yor memory and anater for input. Sina, two separate Write signal must be generated, Fig. 210 shows that four diferent control signals are generated by combining the als RD . WR and JOVAF. The signal IOV goes low for the memory opecation his signal is ANDed with RD and WR signals by sing bobbled pt NAND gates own in Fig. 2.10. When bot input signals go lon, the outputs of the gate 20 low and generale MEMRD (Memory Read) and MEMWR(Memory Wsite) conto! signals. When the IO/M signal goes high, it indicates the peripheral VO. Fig. 2.10 shows the generation ‘of TORD (VO Read) and TOWR (VO Write) comrol sginals wt —_—: 211 Gye cowed Xan, “second method of generating clock signal is using a. parallel-resonant LC circuit, in Fig 2.12 pale LC cireit can be used asthe frequency source for the valucs of L and C can be choses using the following formula : fe mare e a : * 6212.0 wed ct cea daw ‘ f= UCC, ; To mininize vans in chosen as twice that of C, of 3p ei Tecommended that Lol Cor Mp ee 8 Value for € should = tmp Hoe th etn, sac sireuit is not recommended for 1 RC crit may aso ney sls eyeny is of no cm ano HR for he $085 if an acta shows a clock circuit for generating oq er S88 isthe to as tha fequencis grey higher or an aPRNMAL exe omponent cost, Fig. 21° ‘ircuit. ha eat ety of 3 ME. Nae 01 be attempted. on ee ee