Basic Computer Organization

In this lecture, we will study

i. Computer Instructions, Instruction Codes, and Instruction Cycles

ii. Timing and Control

iii. Memory-Reference Instructions

iv. Input/Output and Interrupts

v. Complete Computer Description and Design of a Basic Computer

Chapter Exercises
Computer Instructions and Instruction Codes

3
 Computer Instructions

A computer instruction is a binary code that specifies

a sequence of microoperations for the computer.

4
 Instruction Codes

An instruction code is group of bits that instruct the computer to

perform a specific operation.

An instruction code is usually divided into different parts, and each

part has its own particular interpretation.

5
 Instruction Codes

The most basic part of an instruction code is its OPERATION CODE (or
OPCODE); it is a group of bits that define operations such as add, subtract,
multiply, shift, and complement.

For instance, the ADD operation can be assigned the opcode 110010. When
the computer sees this opcode, it automatically knows to add the operands.

6
 Stored Program Organization

The simplest way to organize a computer is to have

one processsor register & an instruction code format with two parts.

The first part specifies the operation to be performed

and the second part specifies the address of the required operand.

The operand is read from the memory and is then operated on

together with the data stored in the processor register.

7
 Stored Program Organization

For a memory unit with 4096

words, we need 12 bits to
specify an address
(since 212 = 4096).

If we store each instruction in a

16-bit memory word, then we
have 4 bits available for the
operation code (opcode).With a
For operations such as ‘clear AC’ or 4-bit opcode, we will be able to
‘complement AC’ (that do not
specify a total of 24 = 16 distinct
require an operand from the memory,
the instruction only has one part. operations.
8
 Addressing Modes

The first part of an instruction i.e., the opcode, specifies a particular operation
to be performed. This operation has to be performed on some operand i.e.,
data, stored in a computer register or in the main memory.

The way any operand is selected during program execution is dependent on

the addressing mode being used in the instruction. The three addressing
modes we will discuss at this point are:

> Immediate
> Direct
> Indirect
9
 Addressing Modes

Immediate Addressing: When the second part of the instruction code specifies the required
operand, the instruction is referred to as an “Immediate Instruction” (because it has an
immediate operand).

Direct Addresssing: When the second part of the instruction code specifies the address of
the required operand, the instruction is said to have a “Direct Address” (because the address
of the operand is directly present in the instruction itself).

Indirect Addressing: When the second part of the instruction code contains not the address
of the operand but rather the address of the memory word in which the address of the
operand is present, the instruction is said to have an “Indirect Address”.
10
Immediate Direct Indirect
Addressing Addressing Addressing

Operand

11
 The leftmost bit (I)
signifies the addressing
mode.

I = 0 indicates direct
addressing

I = 1 indicates indirect
addressing

Effective
Address

Effective
Address
Computer Registers

13
 Computer Registers

OUTR

14
 Common Bus System

A basic computer has eight registers, a memory unit, and a control unit;
paths must be provided to transfer information from one unit to another.

If separate lines of communication are used between each

unit, the number of wires will be excessive.
It is more efficient to use a COMMON BUS SYSTEM.

15
Common Bus System
Computer Instructions

17
 Computer Instructions

A basic computer has three

instruction code formats:

> Memory-Reference Instruction Format

> Register-Reference Instruction Format
> Input-Output Instruction Format

18
 Memory-Reference Instructions

A memory-reference instruction refers to a memory address as operands.

The other operand is always the accumulator.

A memory-reference instruction uses 12 bits to specify the address of the operand

and 1 bit to specify the addressing mode I; I=0 indicates direct addressing mode
while I = 1 indicates indirect addressing mode.

The opcode in a memory-reference instruction can take any value from 000 to 110.
19
 Register-Reference Instructions

Register-reference instructions perform operations on registers instead of memory.

A register-reference instruction is identified by the opcode 111, with a 0 in the

leftmost bit (i.e., bit 15).

A register-reference instruction specifies an operation on or a test of the

accumulator (AC). An operand from memory is not needed, and so the 12 bits (that
are generally reserved for the address) are used to specify the register operation.
20
 Input-Output Instruction

These instruction enable communication between the computer and the

outside environment.

An input-output instruction is identified by the opcode 111, with a 1 in the leftmost

bit (i.e., bit 15).

A input-output instruction does not need an operand from the memory, and so the
12 bits (that are generally used to specify the address) are used to specify the
input-output operation instead. 21
Basic Computer Instructions

22
 Instruction Set Completeness

A set of instructions are said to be complete if the computer includes

a sufficient number of instructions in each of the following categories:

1. Arithematic, logical, and shift instructions

2. Instructions for moving information to/from memory and processor registers

3. Program control and status checking instructions

4. Input and output instructions

23
Timing and Control

24
 Timing and Control

The timing for all registers in a basic computer is controlled by a

Master Clock Generator.

The clock pulses are applied to all flip-flops and registers in the
system, as well as, the flip-flops and registers in the control unit.
The clock pulses DO NOT change the state of a register
until the register is enabled by a control signal
generated in the control unit.
25
 Two Major Types of Control Organizations

Hardwired Control Microprogrammed Control

In this type of control In this type of control

organization, the control logic is organization, the control
implemented with gates, flip- information is stored in a control
flops, decoders, and other memory. This memory is
digital circuits. programmed to initiate the
It can be optimized to produce a required sequence of
fast mode of operation. microoperations.

26
Block Diagram of a Typical Control Unit

27
 Block Diagram of a Typical Control Unit

An instruction read
from the memory
is placed in the IR

I signifies the
addressing mode
I = 0 :- direct addressing
I = 1 :- indirect addressing

This decoder decodes

the opcode

This decoder decodes

outputs of the SC into
timing signals

The 4-bit SC can

count from 0 to15 28
 Example of Control Timing Signals

The sequence counter

SC responds to positive
transitions of the clock.

Initially, the CLR input

of the SC is active.

29
 Example of Control Timing Signals

Initially, the CLR input of the

SC is active.

The first +ve transition of

the clock clears SC to 0

30
 Example of Control Timing Signals

When SC clears to 0, it in turn

activates the timing signal T0
out of the decoder.

T0 remains active during

one clock cycle.

31
 Example of Control Timing Signals

This positive clock transition

will activate only those registers
whose control inputs are
connected to timing signal T0.

32
 Example of Control Timing Signals

SC is incremented with every

positive clock transition,
unless its CLR input is active.

33
 Example of Control Timing Signals

When D3T4 = 1
SC is cleared

34
 Example of Control Timing Signals

And so, at the next

positive clock transition (T4),
the counter is cleared.

35
 Relationship Between Data Transfer,
Clock Transitions, and Timing Signals

In order to fully comprehend the operation of a computer, it is crucial to understand the

timing relationship between clock transitions and timing signals.

For instance, the register transfer statement

T0 : AR ß PC

specifies a transfer of contents of PC into AR if the timing signal T0 is active.

T0 is active during an entire clock cycle interval; during this time, the contents of PC are
placed on the bus and the ‘load’ input of the AR is enable.
But the actual transfer does not occur until the end of the clock cycle when the clock
goes through the next positive transition.
36
Instruction Cycle

37
 Instruction Cycle
A program residing in the memory is basically a sequence of instructions,
and a specific cycle has to be followed for the execution of each instruction,
as illustrated below:

Fetch the instruction from memory

Decode the instruction

A typical instruction cycle
Read the effective address from memory
(in case of indirect addressing)

Execute the instruction

38
 Instruction Cycle: Fetch and Decode

Initially, the PC is loaded with the address of the first instruction in the program. The
sequence counter (SC) is cleared to 0, providing a decoded timing signal T0.
After each clock pulse, the SC is incremented by 1, so that the next timing signals
T1 , T2, T3 and so on can be generated.

The microoperations for the fetch and decode phases can be specified by the
following register transfer statements:

T0 : AR ß PC
T1 : IR ß M[AR], PC ß PC+1
T2 : D0, D1,….., D7 ß Decode IR (12-14), AR ß IR (0-11), I ß IR(15)
39
 Fetch and Decode: Microoperation 1

T0 : AR ß PC

The address of the instruction is transferred from PC to AR.

40
 Fetch and Decode: Microoperation 2

T1 : IR ß M[AR], PC ß PC+1

The contents of the memory word M, whose address is present in AR, is moved to
IR, and the PC is incremented by one (so that it now points to the next instruction to
be fetched). This happens with the clock transition associated with the next timing
signal, i.e., T1.

41
 Fetch and Decode: Microoperation 3

T2 : D0, D1,….., D7 ß Decode IR (12-14), AR ß IR (0-11), I ß IR(15)

At time T2 :

i) the opcode (which is present in bits 12, 13, and 14 of the IR) is decoded.

ii) the address of the operand (which is present in bits 0 – 11 of the IR) is
transferred to AR.

iii) the single bit (bit 15 of the IR) which indicates the indirect addressing
mode is transferred to flip-flop I.

42
Diagramatic Representation of The Fetch Phase

43
Flowchart for
Instruction Cycle:
Initial Configuration

44
Memory-Reference Instructions

45
 Memory-Reference Instructions

Execution of a memory-reference instruction starts with the timing signal T4.

46
 Memory-Reference Instructions
1. AND to AC

AC ß AC ∧M[AR]

This instruction performs the AND logic operation on pairs of bits in the AC
(accumulator) and the memory word specified by the effective address present in
AR. The result is then transferred to AC.
The microoperations that execute this instruction are:

D0T4: DR ß M[AR]
D0T5: AC ß AC ∧ DR, SC ß 0

47
 Memory-Reference Instructions
2. ADD to AC

AC ß AC + M[AR], E ß Cout

This instruction adds the contents of the memory word specified by the effective
address to the value of AC. The sum is transferred to AC and the output carry is
transferred to E (extended accumulator) flip-flop.
The microoperations needed to execute this instruction are:

D1T4: DR ß M[AR]
D1T5: AC ß AC + DR, E ß Cout, SC ß 0

48
 Memory-Reference Instructions

3. LDA: Load to AC

AC ß M[AR]

This instruction transfers the memory word specified by the effective address to AC.
The microoperations needed to execute this instruction are:

D2T4: DR ß M[AR]
D2T5: AC ß DR, SC ß 0

49
 Memory-Reference Instructions

4. STA: Store AC

M[AR] ß AC

This instruction stores the contents of AC into the memory word specified by the
effective address.
The microoperation needed to execute this instruction is:

D3T4: M[AR] ß AC, SC ß 0

50
 Memory-Reference Instructions

5. BUN: Branch Unconditionally

PC ß AR

This instruction transfers the control of the program to the instruction specified the
effective address.
The microoperation needed to execute this instruction is:

D4T4: PC ß AR, SC ß 0

51
 Memory-Reference Instructions

6. BSA: Branch and Save Return Address

M[AR] ß PC, PC ß AR+1

This instruction is useful for branching to a subroutine or procedure.

When executed, this intruction stores the address of the next instruction into a
memory location specified by the effective address. The effective address plus one is
then added to PC (which will serve as the first address in the subroutine).

52
 Example of BSA Instruction Execution

Address contained
I = 0 (i.e., direct)
Addresses in BSA

Memory, PC, and AR

Before Execution of BSA

53
 Example of BSA Instruction Execution

During Execution:

M[AR] ß PC, PC ß AR+1

i.e.,
M[135] ß 21, PC ß135+1 = 136

Memory and PC After

Execution of BSA (Indirect) address

I=1 contained in BUN

(i.e., indirect)

54
Example of BSA Instruction Execution

55
 Memory-Reference Instructions

6. BSA: Branch and Save Return Address

M[AR] ß PC, PC ß AR+1

The microoperations needed to execute the BSA instruction are:

D5T4: M[AR] ß PC, AR ß AR + 1

D5T5: PC ß AR, SC ß 0

56
 Memory-Reference Instructions
7. ISZ: Increment and Skip if Zero (this is the longest instruction)

M[AR] ß M[AR] + 1
If M[AR] +1 = 0 then PC ß PC+1

This instruction increments the word specified by the effective address, and if the
incremented value is equal to 0, PC is incremented by 1.
The microoperations needed to execute this instruction are:

D6T4: DR ß M[AR]
D6T5: DR ß DR + 1
D5T6: M[AR] ß DR, if (DR = 0) then (PC ß PC+1), SCß 0
57
Control Flowchart of Memory-Reference Instructions

58
Input and Output

59
 Input and Output

A computer can serve no useful purpose

unless it communicates with the external environment.

Instructions and data stored in the memory

must come from some input device,
and the results of the computations
must be transmitted to the user through some output device.

60
Input-Output Configuration

1-bit Output Flag

Initially set to 1

Output Register

Input Register

1-bit Input Flag

Initially set to 0

61
Input-Output Configuration: Flow of Information Transfer

Initially, FGI is set to 0. When

you press a key on the keyboard,
an 8-bit alphanumeric code is
shifted into INPR and FGI is set
to 1. (As long as the flag is set,
pressing another key does not
change the information in INPR).
62
Input-Output Configuration: Flow of Information Transfer

The computer checks the flag;

if FGI = 1, information from INPR
is transferred in parallel to AC
and FGI is cleared to 0.

63
Input-Output Configuration: Flow of Information Transfer

Initially, FGO is set to 1.

The computer checks the flag; if
it is 1, the information from AC is
transferred in parallel to OUTR
and FGO is cleared to 0. The
printer accepts the coded info,
prints the corresponding
character, and when this is done,
FGO is set to 1.
(As long as FGO = 0, no new info
goes into OUTR)

64
Input/Output Instructions

65
Program Interrupt

66
 Programmed Control Transfer

The process of communication just described is referred to as

PROGRAMMED CONTROL TRANSFER.

In this case, the computer keeps checking the flag bit,

and when it finds that the bit is set,
it initiates an information transfer.

67
 Programmed Control Transfer

Programmed control transfer is INEFFICIENT,

because of the difference in the information flow rates
between the processor and the input/output device.

68
Program Interrupt: An Alternative to Programmed Control Transfer

An alternative to programmed control transfer is to

let the input/output device inform the processor
when it is ready for data transfer,
and in the meantime, the processor is free
to perform other useful tasks.

THIS IS KNOWN AS “PROGRAM INTERRUPT”.

69
Step 1 Program Interrupt: How It Works

Step 2

Step 3
When the When a flag is The computer
computer is set, the computer momentarily
running a is interrupted deviates from
program, it does from its current what it is doing to
not check the program, and is take care of the
flags. informed that a input/output
flag has been set . operation, before
returning to its
original task.

70
Flowchart of Interrupt Cycle

R= Interrupt Flip-Flop

IEN = Interrupt Enable

Flip-Flop

When IEN = 0, the flags

cannot interrupt the
computer.

When IEN = 1, the

computer can be
interrupted.

71
 Demonstration of Interrupt Cycle

Before the interrupt, the

main program is being
Current point executed (specifically, the
of execution
instruction at location 255 is
being executed).

When R = 1, the interrupt

cycle begins…

Before Interrupt
72
Demonstration of Interrupt Cycle

When the interrupt cycle

begins…

the content of PC (i.e., 256)

is placed in memory
location 0

PC is set to 1

and R is cleared to 0

After Interrupt
73
Demonstration of Interrupt Cycle

At the beginning of the next

intruction cycle, the instruction
whose address is stored in PC
is read.

This instruction takes the

control to the I/O Program.

After Interrupt
74
Demonstration of Interrupt Cycle

When the I/O program is

finished, the control goes back
to memory location 0, which
further takes the control to
location 256.

After Interrupt
75
 Microoperations for Interrupt Cycle

1. RT0: AR ß 0, TR ß PC
(During the first timing signal, AR is cleared to 0, and the content of PC is transferred to a
temporary register TR.)

2. RT1: M[AR] ß TR, PC ß 0

(During the second timing signal, the return address is stored in the memory location 0,
and PC is cleared to 0.)

3. RT2: PC ß PC + 1, IEN ß 0, R ß 0, SC ß 0
(During the third timing signal, PC is incremented, IEN, R, and SC are cleared to 0.)
76
Complete Computer Description

77
Complete Flowchart
for Computer Operation

78
Design of a Basic Computer

79
 Components of a Basic Computer

A memory unit with 4096 words of 16 bit each

A basic components consists of

Nine registers (PC, AR, DR, AC, IR, TR, OUTR, INPR, SC)

Seven flip-flops (I, S, E, R, IEN, FGI, FGO)

Two decoders (3x8 operation decoder, 4x16 timing decoder)

A 16-bit common bus

Control logic gates

Adder and logic circuit connected to the input of AC

80
Control Functions and Microoperations for Basic Computer

81
Control Functions and Microoperations for Basic Computer

82
83
Exercises

84
1.

85
Solution:
256 K = 28 x 210 = 218

64 = 26
a. Address part: 18 bits, Register code part: 6 bits, Indirect bit: 1 bit

32 - (18+6+1) = 32 - 25 = 7 bits for opcode.

b.

c. No. of bits in data input: 32 bits, No. of bits in address input: 18 bits

86
2.

87
Solution:

A direct address instruction needs TWO references to memory: one to read the
instruction and one to read the operand.

An indirect address instruction needs THREE references to memory: one to read

the instruction, one to read the effective address, and one to read the
operand.

88
3.

89
Fig. 5-4. 111
001
010
011
100

101
110

90
Solution:

a. Memory read to bus and load to IR: IR ← M[AR]

b. TR to bus and load to PC: PC ← TR
c. AC to bus, write to memory, and load to DR:
DR ← AC, M[AR]← AC

d. Add DR (or INPR) to AC: AC ← AC + DR

91
4.

92
Solution:

93
Solution:

The contents of AC are placed on the bus (with S2S1S0 = 100), LD of DR is

enabled, contents of DR are moved to AC through the adder and logic
circuit, and LD of AC is enable, all during the same clock cycle.

94
5.

95
 Solution

a. IR ← M[PC]

PC cannot provide address to memory; address must be transferred to AR first.

AR ← PC

IR ← M[AR]

b. AC ← AC+TR

Add operation must be performed with DR; contents of TR must first be moved to DR.
DR ← TR
AC ← AC+DR

96
 Solution (continued)

c. DR ← DR+AC (AC does not change)

Result of addition are transferred to AC (not DR). So to make sure that the contents of AC
do not change, its contents must first be transferred to DR or TR.

AC ← DR, DR ← AC (switch the contents of AC and DR )

AC ← AC+DR (perform the addition)

AC ← DR, DR ← AC (switch back)

97
 Solution (continued)

c. Suppose AC = 10 and DR = 5.

AC ← DR, DR ← AC AC = 5, DR = 10

AC ← AC+DR AC = 10 + 5 = 15

AC ← DR, DR ← AC AC = 10, DR = 15

98
6.

99
Fig. 5-5

100
Table 5-2

101
Solution:

102
Table 5-2

103
Solution:

104
Table 5-2

105
Solution:

106
Table 5-2

107
7.

Solution:

CLE: Clear E

CME: Complement E

108
Table 5-2

109
8.

110
Solution:

111
9.

112
 Solution

1. CLA: Clear AC

Hexadecimal code for CLA is 7800, where ‘7’ is the opcode and ‘800’ is the address.

2. CLE: Clear E

Hexadecimal code for CLE is 7400, where ‘7’ is the opcode and ‘400’ is the address.
113
 Solution (continued)

3. CMA: Complement AC

Hexadecimal code for CMA is 7200, where ‘7’ is the opcode and ‘200’ is the address.

A 9 3 7

1010 1001 0011 0111

Complement: 0101 0110 1100 1000

5 6 C 8
114
 Solution (continued)

4. CME: Complement E

Hexadecimal code for CME is 7100, where ‘7’ is the opcode and ‘100’ is the address.

115
 Solution (continued)

5. CIR: Circulate Right AC and E

Hexadecimal code for CIR is 7080, where ‘7’ is the opcode and ‘080’ is the address.

CIR : AC ← shr AC, AC(15) ← E, E ← AC(0)

A 9 3 7

AC : 1010 1001 0011 0111 E=1

shr, AC, AC(15) ← E, E ← AC(0) : 1101 0100 1001 1011 E=1
D 4 9 B

116
 Solution (continued)

6. CIL: Circulate Left AC and E

Hexadecimal code for CIL is 7040, where ‘7’ is the opcode and ‘050’ is the address.
CIL : AC ← shl AC, AC(0) ← E, E ← AC(15)

A 9 3 7

AC : 1010 1001 0011 0111 E=1

shl AC, AC(0) ← E, E ← AC(15) : 0101 0010 0110 1111 E=1
5 2 6 F

117
 Solution (continued)

7. INC: Increment AC

Hexadecimal code for INC is 7020, where ‘7’ is the opcode and ‘020’ is the address.

8. SPA: Skip next instruction if AC is positive

Hexadecimal code for SPA is 7010, where ‘7’ is the opcode and ‘010’ is the address.
118
 Solution (continued)

9. SNA: Skip next instruction if AC is negative

Hexadecimal code for SNA is 7008, where ‘7’ is the opcode and ‘008’ is the address.

10. SZA: SZA: Skip next instruction if AC = 0

Hexadecimal code for SZA is 7004, where ‘7’ is the opcode and ‘004’ is the address.
119
 Solution (continued)

11. SZE: Skip next instruction if E = 0

Hexadecimal code for SZE is 7002, where ‘7’ is the opcode and ‘002’ is the address.

12. HTL: Halt computer

Hexadecimal code for HLT is 7001, where ‘7’ is the opcode and ‘001’ is the address.
120
Solution

121
10.

122
 Solution

Instruction at address 021 has I = 0 and opcode of the AND instruction. The address part is 083.

Also, M[083] = B8F and AC = A937.

1. AND: AND memory word to AC

AND: DR ← M[AR]

AC ← AC ∧ DR When I = 0,
AND instruction has
AC: A 9 3 7 the hexadecimal code
0xxx
1010 1001 0011 0111

DR: B 8 F 2

1011 1000 1111 0010

AC ∧ DR: 1010 1000 0011 0010 (= A832) 123
 Solution (continued)

2. ADD: ADD memory word to AC

ADD: DR ← M[AR]
When I = 0,
AC ← AC + DR, E ← Cout ADD instruction has
the hexadecimal code
1xxx
AC: A 9 3 7
1010 1001 0011 0111

DR: B 8 F 2
1011 1000 1111 0010

AC + DR: 0110 0010 0010 1001 (= 6229) , E = 1

124
 Solution (continued)

3. LDA: Load memory word to AC

LDA: AC ← M[AR] When I = 0, LDA has the

hexadecimal code 2xxx

4. STA: Store content of AC in memory

STA: M[AR] ← AC When I = 0, STA has the

hexadecimal code 3xxx

125
 Solution (continued)

3. LDA: Load memory word to AC

LDA: DR ← M[AR] When I = 0, LDA has the

hexadecimal code 2xxx
AC ← DR

4. STA: Store content of AC in memory

When I = 0, STA has the

STA: M[AR] ← AC hexadecimal code 3xxx
126
 Solution (continued)

5. BUN: Branch Unconditionally

BUN: PC ← AR When I = 0, BUN has the

hexadecimal code 4xxx

5. BSA: Branch and save return address

BSA: M[AR] ← PC, PC ← AR+1 When I = 0, BSA has the

hexadecimal code 5xxx
AR ← PC

127
 Solution (continued)

7. ISZ: Increment and skip if zero

When I = 0, ISZ has the

hexadecimal code 6xxx

ISZ: M[AR] ← M[AR] + 1 (M[AR] = DR)

If M[AR] + 1 = 0 then PC ← PC + 1

128
Solution

129
11.

130
 Solution

Address Memory

PC = 7FF EA9F

A9F 0C35

C35 FFFF

131
 Solution

Indirect ISZ: DR ß M[AR]

DR ß DR + 1

M[AR] ß DR, if (DR = 0) then (PC ß PC+1), SCß 0

132
 Solution (continued)

Indirect ISZ: DR ß M[AR]

DR ß DR + 1

M[AR] ß DR, if (DR = 0) then (PC ß PC+1), SCß 0

133
 Solution (continued)

Indirect ISZ: DR ß M[AR]

DR ß DR + 1

M[AR] ß DR, if (DR = 0) then (PC ß PC+1), SCß 0

134
 Solution (continued)

Indirect ISZ: DR ß M[AR]

DR ß DR + 1

M[AR] ß DR, if (DR = 0) then (PC ß PC+1), SCß 0

135
 Solution (continued)

Indirect ISZ: DR ß M[AR]

DR ß DR + 1

M[AR] ß DR, if (DR = 0) then (PC ß PC+1), SCß 0

136
 Solution (continued)

Indirect ISZ: DR ß M[AR]

DR ß DR + 1

M[AR] ß DR, if (DR = 0) then (PC ß PC+1), SCß 0

137
 Solution (continued)

Indirect ISZ: DR ß M[AR]

DR ß DR + 1

M[AR] ß DR, if (DR = 0) then (PC ß PC+1), SCß 0

138
12.

139
 Solution

a. PC contains 3AF, and at memory location 3AF,

we have the value 932E

9 = 1001
So, 932E becomes 1001 32E = 1 001 32E = 1 ADD 32E

1 ADD 32E

Next Instruction to be fetched and executed

140
 Solution (continued)

b. AC = 7EC3

Next instruction = 1 ADD 32E

09AC

DR 8B9F

We will ADD 7EC3 and 8B9F => 7EC3 + 8B9F = 0A62

So, AC = 0A62 and Carry = 1 (carry is moved to E, So E = 1)

141
 Solution (continued)

c. PC = 3AF + 1 = 3B0

IR = 932E
AR = 9AC

DR = 8B9F

AC = 0A62
E=1

I=1
SC = 0000

142
13.

143
Table 5-4

144
13.

145
 Solution

Original Instruction New Instruction

and Microoperations and Microoperations

AC ß AC ∧M[AR] AC ß AC + M[EA]

D0T4: DR ß M[AR] D0T4: DR ß M[AR]

D0T5: AC ß AC ∧ DR, SC ß 0 D0T5: AC ß AC + DR, SC ß 0

146
 Solution (continued)

Original Instruction New Instruction

and Microoperations and Microoperations

M[EA] ß M[EA] + AC
AC ß AC + M[AR], E ß Cout

D1T4: DR ß M[AR] D1T4: DR ß M[AR]

D1T5: AC ß AC + DR, E ß Cout, SC ß 0 D1T5: DR ß AC, AC ß AC + DR
D1T6: M[AR] ß AC, AC ß DR, SC ß 0

147
 Solution (continued)
Original Instruction New Instruction
and Microoperations and Microoperations

AC ß M[AR] AC ß AC - M[EA]

D2T4: DR ß M[AR] D2T4: DR ß M[AR]

D2T5: AC ß DR, SC ß 0 D2T5: DR ß AC, AC ß DR
D2T6: AC ß AC

D2T7: AC ß AC + 1
D2T8: AC ß DR + AC, SC ß 0

148
 Solution (continued)

Original Instruction New Instruction

and Microoperations and Microoperations

M[AR] ß AC AC ß M[EA], M[EA] ß AC

D3T4: M[AR] ß AC, SC ß 0 D3T4: DR ß M[AR]

D3T5 :M[AR] ß AC, AC ß DR, SC ß0

149
 Solution (continued)

Original Instruction New Instruction

and Microoperations and Microoperations

PC ß AC If (M[EA] = AC) then (PC ß PC + 1)

D4T4: PC ß AR, SC ß 0 D4T4: DR ß M[AR]

D4T5: TR ß AC, AC ß AC + DR
D4T6: If (AC = 0) then PC ß PC + 1,

AC ß TR, SC ß 0

150
 Solution (continued)

Original Instruction New Instruction

and Microoperations and Microoperations

M[AR] ß PC, PC ß AR+1 If (AC > 0) then PC ß EA

D5T4: M[AR] ß PC, AR ß AR + 1 If (AC (15) = 0)

D5T5: PC ß AR, SC ß 0 then (PC ßAR), SC ß 0

151
14.

152
Solution:

This change converts the ISZ instruction from a memory-reference

instruction to a register-reference instruction.

The new instruction ICSZ can be executed at time T3 instead of

time T6, which helps save 3 clock cycles.

153
15.

154
Fig. 5.3

Fig. 5.5(a)

155
Flowchart for
Instruction Cycle:
Initial Configuration
(Fig. 5-9)

156
Solution:

157
16.

158
Fig. 5.3

159
 Solution

a. Diagram of the
computer showing
memory and registers.

160
Solution (continued)

b. Placement of a typical three-word instruction

and the corresponding operand in memory.

161
 Solution (continued)

c. Microoperations needed to fetch

a memory-reference instruction and
place the operand in DR.

162
17.

163
 Solution

Solution

1. Read 40-bit double instruction from memory to IR, increment PC

2. Decode opcode 1
3. Execute instruction 1 using address 1
4. Decode opcode 2
5. Execute instruction 2 using address 2
6. Go to step 1
164
18.

165
 Solution

a. BUN 2300 0 (Branch direct with address 2300) 0 BUN 2300

b. ION (Interrupt Enable On)

BUN 0 1 (Branch indirect with address 0) 1 BUN 0

166
19.

167
Fig. 2-12

168
Solution (Step 1)

169
Solution (Step 2)

170
Solution (Step 3)

171
Solution (Step 4)

172
Solution (Step 5)

173
Solution (Step 6)

174
Solution (Step 7)

175
Solution (Step 8)

176
20.

177
 Solution

We need to construct a new flip-flop using a combination of JK flip-flop and

additional control logic.

The control logic will be designed using the control variables w, x, y, z, T1, T2, T3,
and T5.

The control logic will essentially serve as inputs to the JK flip-flop (i.e., JF and KF).

178
 Solution (continued)

Characteristic Table of JK Flip-Flop Register Transfer Operations

Required from the F Flip-Flop

179
Solution (continued)

JF = xT3 + zT2 + ?
KF = yT1 + zT2 + ?

180
Solution (continued)

JF = xT3 + zT2 + wT5G

KF = yT1 + zT2 + wT5G’

181
 Solution (continued)

JF = xT3 + zT2 + wT5G KF = yT1 + zT2 + wT5G’

182
22.

Solution

Memory’s “write” operation pertains to all those operations that involve a

transfer like this: M[AR] ß xx

Write = D3T4 + D5T4 + D6T6 + RT1 (from Table 5.6)

STA BSA ISZ one of the microoperations

of the interrupt operation

183
23.

Solution
(T0 + T1 + T2)' (IEN) (FGI + FGO) : R ← 1
RT2 : R ← 0

or from Table 5.6

T0’ T1’ T2' (IEN) (FGI + FGO) : R ← 1
RT2 : R ← 0

184
 Solution (continued)

(T0 + T1 + T2)' (IEN) (FGI + FGO) : R ← 1

RT2 : R ← 0

185
 25.

Solution
Clearing the sequence counter means CLR (SC), i.e., any microoperation that
involves the part “SC ß 0”.

CLR(SC)= RT2 + D7T3 (I’+I) + (D0 + D1 + D2 + D5) T5 + (D3 + D4) T4 + D6T6

(from Table 5.6)

186
 Solution (continued)

CLR(SC)= RT2 + D7T3 (I’+I) + (D0 + D1 + D2 + D5) T5 + (D3 + D4) T4 + D6T6

187