IEC Exp 3 Student
IEC Exp 3 Student
Objective:
Introduction:
The series-parallel networks are networks that contain both series and parallel circuit configurations.
The series circuit can be solved using the Kirchoff’s voltage law (KVL) and Voltage divider rule
(VDR). The parallel circuit can be solved using the Kirchoff’s current law (KCL) and Current divider
rule (CDR). The combination of series-parallel network can be solved using KVL, KCL, VDR and
CDR. In solving networks (having considerable number of branches) by the application of Kirchhoff’s
Laws, one sometimes experiences great difficulty due to a large number of simultaneous equation that
have to be solve. However, such complicated networks can simplify by successively replacing delta
meshes by equivalent Y systems and vice versa.
a) They have only one terminal in common (i.e., one lead of one is connected to only one lead of
the other.
b) The common point between the two elements is not connected to another current-carrying
element.
The current is the same through series elements. The total resistance of a series circuit is the sum of
the resistance levels. In general, to find the total resistance of N resistors in series, the following
equation is
applied:
RT = R1+R2+R3+...........+RN (Ohms) I=E/RT (Amperes)
The voltage across each resistor (Figure 1) using Ohm’s law; that is,
The voltage divider rule states that the voltage across a resistor in a series circuit is equal to the value
of that resistor times the total impressed voltage across the series elements divided by the total
resistance of the series elements. The following VDR equation is applied:
Where, Vx is the voltage across Rx, E is the impressed voltage across the series elements, and RT is the
total resistance of the series circuit.
The current divider rule states that the current through any parallel branch is equal to the product of
the total resistance of the parallel branches and the input current divided by the resistance of the
branch through which the current is to be determined. The following CDR equation is applied:
Figure 1: Series Circuit Figure 2: Parallel Circuit Figure 3: Voltage Sources in series
In Figure 3(a), for example, the sources are all “pressuring” current to the right, so the net voltage is
ET = E1 + E2 + E3 = 10V + 2V + 6V = 18V as shown in the figure.
In Figure 3(b), however, the greater “pressure” is to the left, with a net voltage of
ET = E2 + E3 – E1 = 9V + 3V – 4V = 8V and the polarity shown in the figure.
In many circuit applications, we encounter components connected together in one of two ways to form
a three- terminal network: the “Delta,” or (also known as “pi,” or ) configuration, and the “Y”
(also known as the “T” ) configuration.
It is possible to calculate the proper values of resistors necessary to form one kind of network ( or Y)
that behaves identically to the other kind, as analyzed from the terminal connections alone. That is , if
we had two separate resistor networks one and one Y, each with its resistors hidden from view, with
nothing but the three terminals (A,B, and C ) exposed for testing, the resistor could be sized for the
two networks so there would be no way to electrically determine one network apart from the other. In
other words, equivalent and Y networks behave identically.
There are several equations used to convert one network to the other.
To convert a Delta () to Wye (Y) To convert a Wye (Y) to Delta ()
R AB R AC R A RB + RB RC + RC R A
RA= RAB=
R AB + R AC + R BC RC
R AB RBC R A RB + RB RC + RC R A
RB = RBC=
R AB + R AC + R BC RA
R AC RBC R A RB + RB RC + RC R A
RC = RAC=
R AB + R AC + R BC RB
Pre-Lab Homework:
Read about the basic laws of series and parallel circuits and theories related to Delta to Wye conversion and
perform the simulation using PSpice 9.1. and MUST present the simulation results to the instructor before the
start of the experiment.
Apparatus:
1. Trainer Board
2. AVO meter or Multimeter
3. DC source
4. Resistors
5. Connecting Wires
Precautions:
Circuit Diagram:
Figure 4
R1 R2
E R5
R4 R3
(a) (b)
Figure 5
Data Table:
Table-1 (For Figure-4)
Value of Resistors: R1=1kΩ, R2=1kΩ, R3=3.25kΩ, R4=2kΩ, R5=10kΩ, R6=5kΩ, R7=5.57kΩ,
R8=1kΩ.
Value of Voltage Sources: E1=20V, E2=10V.
𝐕𝐑 𝐕𝐑𝟏 𝐕𝐑𝟐 𝐕𝐑𝟑 𝐕𝐑𝟒 𝐕𝐑𝟓 𝐈𝐑 𝐈𝐑𝟏 𝐈𝐑𝟐 𝐈𝐑𝟑 𝐈𝐑𝟒 𝐈𝐑𝟓
𝐕𝐑 𝐕𝐑𝟏 𝐕𝐑𝟐 𝐕𝐑𝟔 𝐕𝐑𝟕 𝐕𝐑𝟖 𝐈𝐑 𝐈𝐑𝟏 𝐈𝐑𝟐 𝐈𝐑𝟔 𝐈𝐑𝟕 𝐈𝐑𝟖
Reports:
1. Verify Kirchhoff’s Voltage Law (KVL) and Kirchhoff’s Current Law (KCL) by analyzing
practical data and support them by comparing the results with the theoretical values by proper
circuit solution.
2. Verify - Y conversion formula from the experiment.
3. Verify the measured value of total circuit current with theoretical value. Show necessary
calculation.
4. Comment on the result as a whole.
5. Write the lab report following the template as given before.
References
1. Robert L. Boylestad ,”Introductory Circuit Analysis”, Prentice Hall, 12th Edition, New York, 2010,
ISBN 9780137146666.