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Sequential Circuit

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11 views13 pages

Sequential Circuit

Uploaded by

22022118
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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TRƯỜNG ĐẠI HỌC CÔNG NGHỆ

KHOA ĐIỆN TỬ VIỄN THÔNG

Digital Design & Microprocessors

Sequential Circuit 1

1
VNU - University of Engineering and Technology 1 Faculty of Electronics and Telecommunications
Sequential Circuits

Circuits where the output depends on both current inputs and previous outputs. (Ex. Latches, Flip-flops)

Fig 1. Sequential Design Schematic

VNU - University of Engineering and Technology 2 Faculty of Electronics and Telecommunications


Sequential Circuit

Sequential Circuit: (Clock-based logic circuit) can be either level sensitive or edge sensitive. (In practical applications mostly
edge sensitive)

Positive Negative Positive Negative


Edge Edge Level Level

Fig 2. Clock Sensitive Type

VNU - University of Engineering and Technology 3 Faculty of Electronics and Telecommunications


Synchronous and Asynchronous Reset

➢ Synchronous Reset: Reset depend on clock


➢ Asynchronous Reset: Reset Independently

(A) (B)

Fig 3. (A) Synchronous Reset (B) Asynchronous Reset

VNU - University of Engineering and Technology 4 Faculty of Electronics and Telecommunications


D Flip-Flop
module d_ff_edge ( // Positive edge trigger
input clk,
input d,
output reg q
);
always @(posedge clk) begin
q <= d;
end
endmodule

module d_ff_level ( // Positive level trigger


input clk,
input d,
output reg q
);
always @(posedge clk or d) begin
if (clk)
q <= d;
end
endmodule

VNU - University of Engineering and Technology 5 Faculty of Electronics and Telecommunications


D Flip-Flop
`timescale 1ns/1ns // Generate clock signal with a period of 10 time units
module tb_d_flip_flop; always #5 clk_tb = ~clk_tb;
// Inputs for the testbench
reg clk_tb; initial begin
reg d_tb; // Initialize signals
wire q_edge_tb; clk_tb = 0; d_tb = 0;
wire q_level_tb;
// Apply test sequence
// Instantiate the edge-triggered D flip-flop #10 d_tb = 1;
d_ff_edge uut_edge ( #10 d_tb = 0;
.clk(clk_tb), #10 d_tb = 1;
.d(d_tb), #10 d_tb = 0;
.q(q_edge_tb)
); // Edge and level behavior test
#5; // Move to next Positive clock edge
// Instantiate the level-sensitive D latch #2 d_tb = 1;
d_ff_level uut_level ( #2 d_tb = 0;
.clk(clk_tb),
.d(d_tb), #20;
.q(q_level_tb) end
); endmodule
VNU - University of Engineering and Technology 6 Faculty of Electronics and Telecommunications
D Flip-Flop

Run simulation Add all signal to the wave window then run all to observe and check.

VNU - University of Engineering and Technology 7 Faculty of Electronics and Telecommunications


D Flip Flop

Upload and verify on Board: base on the device manual to assign signal to specific pin and then click on Processing->Start
Compination to compile

VNU - University of Engineering and Technology 8 Faculty of Electronics and Telecommunications


Clock Divider

module clock_divider ( always @(posedge clk or posedge reset) begin


input clk, // 12 MHz input clock if (reset) begin
input reset, // Active-high reset counter <= 23'd0;
output reg clk_1Hz // 1 Hz output clock clk_1Hz <= 1'b0;
); end
// Parameter to divide 12 MHz down to 1 Hz else begin
parameter DIVISOR = 12_000_000; if (counter == DIVISOR - 1) begin
reg [23:0] counter; // 24-bit counter to count up to counter <= 0; // Reset the counter
12,000,000 clk_1Hz <= ~clk_1Hz; // Toggle the 1 Hz clock
output
end
else begin
counter <= counter + 1;
end
end
end
endmodule

VNU - University of Engineering and Technology 9 Faculty of Electronics and Telecommunications


LED

Blink led using divided clock

module blink_led (
input clk,
input reset,
output led
);
wire divided_clock;

clock_divider CD (
.clk(clk),
.reset(reset),
.clk_1Hz(divided_clock)
);

assign led = divided_clock;


endmodule

VNU - University of Engineering and Technology 10 Faculty of Electronics and Telecommunications


Blinking Led

Upload and verify on Board: base on the device manual to assign signal to specific pin and then click on Processing->Start
Compination to compile

VNU - University of Engineering and Technology 11 Faculty of Electronics and Telecommunications


Exercises

➢ JK Flip Flop
➢ 4-bits counter using D Flip Flop

VNU - University of Engineering and Technology 12 Faculty of Electronics and Telecommunications


Title

Content

VNU - University of Engineering and Technology 13 Faculty of Electronics and Telecommunications

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