NCP380 D-1509408

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Fixed/Adjustable

Current‐Limiting
Power‐Distribution
Switches

NCP380, NCV380
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The NCP380 is a high side power-distribution switch designed for
applications where heavy capacitive loads and short-circuits are likely
to be encountered. The device includes an integrated 55 mW (DFN
package), P-channel MOSFET. The device limits the output current to
a desired level by switching into a constant-current regulation mode
when the output load exceeds the current-limit threshold or a short is UDFN6 TSOP−5 TSOP−6
CASE 517AB CASE 483 CASE 318G
present. The current-limit threshold is either user adjustable between
500 mA and 2.1 A via an external resistor or internally fixed. The
power-switch rise and fall times are controlled to minimize current MARKING DIAGRAMS
ringing during switching.
An internal reverse-voltage detection comparator disables the 1 6
2 XXMG 5
power-switch if the output voltage is higher than the input voltage to 3 G 4
protect devices on the input side of the switch.
The FLAG logic output asserts low during over current, UDFN6
reverse-voltage or over temperature conditions. The switch is
controlled by a logic enable input active high or low. 5

Features XXXAYWG
G
• 2.5 V – 5.5 V Operating Range
1
• 70 mW High-side MOSFET
TSOP−5
• Current Limit:
♦ User adjustable from 500 mA to 2.1 A
♦ Fixed 500 mA, 1 A, 1.5 A, 2 A and 2.1 A
• Under Voltage Lock-out (UVLO) XXXAYWG
G
• Built-in Soft-start
1
• Thermal Protection
TSOP−6
• Soft Turn-off
• Reverse Voltage Protection XXX = Specific Device Code
• Junction Temperature Range: −40°C to 125°C A =Assembly Location
M = Date Code
• Enable Active High or Low (EN or EN) Y = Year
• Compliance to IEC61000−4−2 (Level 4) W = Work Week
♦ 8.0 kV (Contact) G = Pb−Free Package
♦ 15 kV (Air) (Note: Microdot may be in either location)
• UL Listed − File No. E343275
• NCV Prefix for Automotive and Other Applications Requiring ORDERING INFORMATION
See detailed ordering and shipping information in the package
Unique Site and Control Change Requirements; AEC−Q100 dimensions section on page 20 of this data sheet.
Qualified and PPAP Capable
• These are Pb-Free Devices

Typical Applications
• Laptops
• USB Ports/Hubs
• TVs

© Semiconductor Components Industries, LLC, 2016 1 Publication Order Number:


May, 2020 − Rev. 17 NCP380/D
NCP380, NCV380

USB
DATA

D+
D− USB
USB INPUT Port
IN OUT VBUS
5V
GND
Rfault 1 mF 120 mF
100 kW NCP380

FLAG FLAG ILIM*


EN EN
Rlim
GND

*For Adjustable Version Only.

Figure 1. Typical Application Circuit

OUT 1 6 IN OUT 1 5 IN IN 1 6 OUT

ILIM* 2 PAD1 5 GND GND 2 GND 2 5 ILIM*

FLAG 3 4 EN FLAG 3 4 EN EN 3 4 FLAG

UDFN6 TSOP−5
TSOP−6
(Top view)

*For adjustable version only, otherwise not connected.

Figure 2. Pin Connections

Table 1. PIN FUNCTION DESCRIPTION


Pin Name Type Description
EN INPUT Enable input, logic low/high (i.e. EN or EN) turns on power switch
GND POWER Ground connection;
IN POWER Power-switch input voltage; connect a 1 mF or greater ceramic capacitor from IN to GND as close as pos-
sible to the IC.
FLAG OUTPUT Active-low open-drain output, asserted during overcurrent, overtemperature or reverse-voltage conditions.
Connect a 10 kW or greater resistor pull-up, otherwise leave unconnected.
OUT OUTPUT Power-switch output; connect a 1 mF ceramic capacitor from OUT to GND as close as possible to the IC
is recommended. A 1 mF or greater ceramic capacitor from OUT to GND must be connected if the USB
requirement (i.e.120 mF capacitor minimum) is not met.
ILIM* INPUT External resistor used to set current-limit threshold; recommended 5 kW < RILIM < 250 kW.
PAD1** THERMAL Exposed Thermal Pad: Must be soldered to PCB Ground plane
*(For adjustable version only, otherwise not connected.
**For DFN version only.

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NCP380, NCV380

Table 2. MAXIMUM RATINGS


Rating Symbol Value Unit
From IN to OUT Pins: Input/Output (Note 1) VIN , VOUT −7.0 to +7.0 V
IN, OUT, EN, ILIM, FLAG, Pins: Input/Output (Note 1) VEN, VILIM, VFLAG, VIN, VOUT −0.3 to +7.0 V
FLAG Sink Current ISINK 1 mA
ILIM Source Current ILIM 1 mA
ESD Withstand Voltage (IEC 61000−4−2) ESD IEC 15 Air, 8 Contact kV
(Output Only, when Bypassed with 1.0 mF Capacitor Minimum)
Human Body Model (HBM) ESD Rating (Note 2) ESD HBM 2,000 V
Machine Model (MM) ESD Rating (Notes 2 and 3) ESD MM 200 V
Latch-up Protection (Note 4) LU mA
Pins IN, OUT, EN, ILIM, FLAG 100
Maximum Junction Temperature Range (Note 6) TJ −40 to +TSD °C
Storage Temperature Range TSTG −40 to +150 °C
Moisture Sensitivity (Note 5) MSL Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. According to JEDEC standard JESD22−A108.
2. This device series contains ESD protection and passes the following tests:
Human Body Model (HBM) ±2.0 kV per JEDEC standard: JESD22−A114 for all pins.
Machine Model (MM) ±200 V per JEDEC standard: JESD22−A115 for all pins.
3. Except EN pin, 150 V.
4. Latch up Current Maximum Rating: ±100 mA per JEDEC standard: JESD78 class II.
5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020.
6. A thermal shutdown protection avoids irreversible damage on the device due to power dissipation.

Table 3. OPERATING CONDITIONS


Symbol Parameter Conditions Min Typ Max Unit
VIN Operational Power Supply 2.5 − 5.5 V
VEN Enable Voltage 0 − 5.5
TA Ambient Temperature Range −40 25 +85 °C
TJ Junction Temperature Range −40 25 +125 °C
RILIM Resistor from ILIM to GND Pin 5.0 − 250 kW
ISINK FLAG Sink Current − − 1.0 mA
CIN Decoupling Input Capacitor 1.0 − − mF
COUT Decoupling Output Capacitor USB Port per Hub 120 − − mF
RqJA Thermal Resistance Junction-to-Air UDFN−6 Package (Notes 7 and 8) − 120 − °C/W
TSOP−5 Package (Notes 7 and 8) − 305 − °C/W
TSOP−6 Package (Notes 7 and 8) − 280 − °C/W
IOUT Maximum DC Current UDFN−6 Package − − 2.1 A
TSOP−5, TSOP−6 Package − − 1.0 A
PD Power Dissipation Rating (Note 9) TA v 25°C UDFN−6 Package − 830 − mW
TSOP−5 Package − 325 − mW
TSOP−6 Package − 350 − mW
TA = 85°C UDFN−6 Package − 325 − mW
TSOP−5 Package − 130 − mW
TSOP−6 Package − 145 − mW
7. A thermal shutdown protection avoids irreversible damage on the device due to power dissipation.
8. The RqJA is dependent of the PCB heat dissipation. Board used to drive this data was a 2” × 2” NCP380EVB board. It is a 2 layers board
with 2-once copper traces on top and bottom of the board. Exposed pad is connected to ground plane for UDFN−6 version only.
9. The maximum power dissipation (PD) is given by the following formula: T JMAX * T A
PD +
R qJA

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NCP380, NCV380

Table 4. ELECTRICAL CHARACTERISTICS


(Min & Max Limits apply for TA between −40°C to +85°C and TJ up to +125°C for VIN between 2.5 V to 5.5 V (Unless otherwise noted).
Typical values are referenced to TA = +25°C and VIN = 5 V.)
Symbol Parameter Conditions Min Typ Max Unit
POWER SWITCH
RDS(on) Static Drain-source On-state VIN = 5 V –40°C < TJ < 125°C − 55 75 mW
Resistance DFN Package
2.5 V < VIN < 5.5 V –40°C < TJ < 125°C − − 110
TSOP Package VIN = 5 V –40°C < TJ < 125°C − 70 95 mW
2.5 V < VIN < 5.5 V –40°C < TJ < 125°C − − 135
TR Output Rise Time VIN = 5 V CLOAD = 1 mF, 0.3 1.0 1.5 ms
RLOAD = 100 W (Note 10)
VIN = 2.5 V 0.2 0.65 1.0
TF Output Fall Time VIN = 5 V 0.1 − 0.5
VIN = 2.5 V 0.1 − 0.5
ENABLE INPUT EN OR EN
VIH High-level Input Voltage 1.2 − − V
VIL Low-level Input Voltage − − 0.4 V
IEN Input Current VEN = 0 V, VEN = 5 V −0.5 − 0.5 mA
TON Turn On Time CLOAD = 1 mF, RLOAD = 100 W (Note 11) 2.0 3.0 4.0 ms
TOFF Turn Off Time 1.0 − 3.0 ms
CURRENT LIMIT
IOCP Current-limit Threshold VIN = 5 V RILIM = 20 kW (Note 11) 1.02 1.20 1.38 A
(Maximum DC Output Current
IOUT Delivered to Load) RILIM = 40 kW 0.595 0.700 0.805
(Notes 11 and 13)
Fixed 0.5 A (Note 12) 0.5 0.58 0.65 A
Fixed 1.0 A (Note 12) 1.0 1.15 1.3
Fixed 1.5 A (Note 12) 1.5 1.75 1.9
Fixed 2.0 A (Note 12) 2.0 2.25 2.5
Fixed 2.1 A (Note 12) 2.1 2.25 2.5
TDET Response Time to Short Circuit VIN = 5 V − 2.0 − ms
TREG Regulation Time 1.8 3.0 4.0 ms
TOCP Overcurrent Protection Time 14 20 26 ms
REVERSE-VOLTAGE PROTECTION
VREV Reverse-voltage Comparator − 100 − mV
Trip Point (VOUT – VIN)
TREV Time from Reverse-voltage VIN = 5 V 4.0 6.0 9.0 ms
Condition to MOSFET Switch Off
& FLAG Low
TRREV Re-arming Time 7.0 10 15 ms
UNDERVOLTAGE LOCKOUT
VUVLO IN Pin Low-level Input Voltage VIN Rising 2.0 2.3 2.4 V
VHYST IN Pin Hysteresis TJ = 25°C 25 − 60 mV
TRUVLO Re-arming Time 7.0 10 15 ms
SUPPLY CURRENT
IINOFF Low-level Output Supply Current VIN = 5 V, No Load on OUT, Device OFF − 1.0 2.1 mA
VEN = 0 V or VEN = 5 V
IINON High-level Output Supply VIN = 5 V, Device Enable mA
Current 2 A and 2.1 A Versions − − 90
1 A and 1.5 A Current Versions − − 80
0.5 A Current Version − − 70
IREV Reverse Leakage Current VOUT = 5 V, VIN = 0 V TJ = 25°C − − 1.0 mA

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NCP380, NCV380

Table 4. ELECTRICAL CHARACTERISTICS (continued)


(Min & Max Limits apply for TA between −40°C to +85°C and TJ up to +125°C for VIN between 2.5 V to 5.5 V (Unless otherwise noted).
Typical values are referenced to TA = +25°C and VIN = 5 V.)
Symbol Parameter Conditions Min Typ Max Unit
FLAG PIN
VOL FLAG Output Low Voltage IFLAG = 1 mA 400 mV
ILEAK Off-state Leakage VFLAG = 5 V 1.0 mA
TFLG FLAG Deglitch FLAG De-assertion Time due to Overcurrent or 4.0 6.0 9.0 ms
Reverse Voltage Condition
TFOCP FLAG Deglitch FLAG Assertion due to Overcurrent 6.0 8.0 12 ms
THERMAL SHUTDOWN
TSD Thermal Shutdown Threshold 140 °C
TSDOCP Thermal Regulation Threshold 125 °C
TRSD Thermal Shutdown Rearming 115 °C
Threshold
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
10. Parameters are guaranteed for CLOAD and RLOAD connected to the OUT pin with respect to the ground, See Figure 3.
11. Adjustable current version, RILIM tolerance ±1%.
12. Fixed current version.
13. Not production test, guaranteed by characterization.

VIN
IN OUT

1 mF CLOAD RLOAD

NCP380

GND

Figure 3. Test Configuration

50%
VEN

TR TF

VEN
TOFF
VOUT 90%
TON 10%
10%
90%
VOUT
10%

Figure 4. Voltage Waveform

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NCP380, NCV380

BLOCK DIAGRAM

Blocking Control

IN OUT

Current
ILIM* Gate Driver
Limiter

Vref
TSD UVLO Osc

GND
Flag
/FLAG

EN EN Block Control Logic and Timer

*For adjustable version only, otherwise not connected.

Figure 5. Block Diagram

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NCP380, NCV380

Ton + TR

Figure 6. Ton Delay and Trise Time

Toff + Tfall

Figure 7. Toff Delay and Tfall

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NCP380, NCV380

Figure 8. Turn On a Short

Treg
TSD
Warning
TOCP

Figure 9. 2 W Short on Output. Complete Regulation Sequence

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NCP380, NCV380

TFOCP
TSD Warning

VIN

VOUT

IIN

/FLAG

Figure 10. OCP Regulation and TSD Warning Event

TOCP

Treg

Figure 11. Timer Regulation Sequence During 2 W Overload

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NCP380, NCV380

Figure 12. Direct Short on OUT Pin

Figure 13. From Timer Regulation to Load Removal Sequence

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NCP380, NCV380

TFOCP

VOUT

IOUT

/FLAG

Figure 14. From No Load to Direct Short Circuit

VREV
VOUT

VIN

TFREV

/FLAG

Figure 15. Reverse Voltage Detection

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NCP380, NCV380

T RREV

Figure 16. Reverse Voltage Removal

2.4

2.38

2.36

2.34

2.32
UVLO (V)

2.3

2.28

2.26

2.24 UVLO vs. Temperature


UVLO − hysteresis vs.
2.22 Temperature

2.2
−50 0 50 100 150
Temperature (°C)

Figure 17. Undervoltage Threshold (Falling) and Hysteresis

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NCP380, NCV380

Low−Level Output Supply Current vs Vin


−40°C 25°C 85°C 125°C
2.0

1.8

1.6

1.4

1.2
IINOFF (mA)

1.0

0.8

0.6

0.4

0.2

0.0
2.4 2.9 3.4 3.9 4.4 4.9 5.4
Vin(V)
Figure 18. Standby Current vs Vin

High−Level Output Supply Current vs Vin

−40°C 25°C 85°C 125°C


100

90

80

70

60
IINON (mA)

50

40

30

20

10

0
2.4 2.9 3.4 3.9 4.4 4.9 5.4
Vin(V)
Figure 19. Quiescent Current vs Vin

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NCP380, NCV380

TSOP Package
100

95 RDS(on) vs. Temperature


90

85

80
RDS(on) (mW)

75

70

65

60

55

50

45

40
−50 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140

Temperature (°C)

Figure 20. RDS(on) vs Temperature, TSOP Package

mDFN Package
100

95
RDS(on) vs. Temperature
90

85

80
RDS(on) (mW)

75

70

65

60

55

50

45

40
−50 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140

Temperature (°C)

Figure 21. RDS(on) vs Temperature, mDFN Package

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NCP380, NCV380

FUNCTIONAL DESCRIPTION

Overview VOUT
The NCP380 is a high side P channel MOSFET power Thermal Timer
Regulation Regulation
distribution switch designed to protect the input supply Threshold Mode
voltage in case of heavy capacitive loads, short circuit or
over current. In addition, the high side MOSFET is turned
IOUT
off during under voltage, thermal shutdown or reverse
voltage condition. Adjustable version allows the user to
program the current limit threshold using an external
IOCP
resistor. Thanks to the soft start circuitry, NCP380 is able to
limit large current and voltage surges. TOCP TREG
Overcurrent Protection Figure 24. Short circuit
NCP380 switches into a constant current regulation mode
when the output current is above the IOCP threshold. Then, the device enters in timer regulation mode, described
Depending on the load, the output voltage is decreased in 2 phases:
accordingly. • Off-phase: Power MOSFET is off during TOCP to allow
• In case of hot plug with heavy capacitive load, the the die temperature to drop.
output voltage is brought down to the capacitor voltage. • On-phase: regulation current mode during TREG. The
The NCP380 will limit the current to the IOCP threshold current is regulated to the IOCP level.
value until the charge of the capacitor is completed.
The timer regulation mode allows the device to handle
VOUT high thermal dissipation (in case of short circuit for
example) within temperature operating condition.
Drop due to
Capacitor Charge NCP380 stays in on-phase/off-phase loop until the over
current condition is removed or enable pin is toggled.
IOUT Remark: Other regulation modes can be available for
different applications. Please contact our
IOCP
ON Semiconductor representative for availability.

FLAG Indicator
Figure 22. Heavy capacitive load
The FLAG pin is an open-drain MOSFET asserted low
• In case of overload, the current is limited to the IOCP during over current, reverse-voltage or over temperature
value and the voltage value is reduced according to the conditions. When an over current or a reverse voltage fault
load by the following relation: is detected on the power path, FLAG pin is asserted low at
the end of the associate deglitch time (see electrical
V OUT + R LOAD I OCP (eq. 1)
characteristics). Thanks to this feature, the FLAG pin is not
VOUT tied low during the charge of a heavy capacitive load or a
voltage transient on output. Deglitch time is TFOCP for over
current fault and TREV for reverse voltage. The FLAG pin
IOCP × RLOAD remains low until the fault is removed. Then, the FLAG pin
goes high at the end of TFGL.
IOUT
Undervoltage Lock-out
Thanks to a built-in under voltage lockout (UVLO)
IOCP
circuitry, the output remains disconnected from input until
Figure 23. Overload VIN voltage is below VUVLO. When VIN voltage is above
VUVLO, the system try to reconnect the output after a
• In case of short circuit or huge load, the current is rearming time. TRUVLO. This circuit has a VHYST hysteresis
limited to the IOCP value within TDET time until the witch provides noise immunity to transient.
short condition is removed. If the output remains
shorted or tied to a very low voltage, the junction Thermal Sense
temperature of the chip exceeds TSDOCP value and the Thermal shutdown turns off the power MOSFET if the die
device enters in thermal shutdown (MOSFET is temperature exceeds TSD. A Hysteresis prevents the part
turned-off). from turning on until the die temperature cools at TRSD.

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NCP380, NCV380

Reverse Voltage Protection Blocking Control


When the output voltage exceeds the input voltage by The blocking control circuitry switches the bulk of the
VREV voltage during TREV, the reverse voltage circuitry power MOS. When the part is off, the body diode limits the
disconnects the output in order to protect the power supply. leakage current IREV from OUT to IN. In this mode, anode
The same time TREV is needed to turn on again the power of the body diode is connected to IN pin and cathode is
MOS plus a rearming time TRREV. connected to OUT pin. In operating condition, anode of the
body diode is connected to OUT pin and cathode is
Enable Input connected to IN pin preventing the discharge of the power
Enable pin must be driven by a logic signal (CMOS or supply.
TTL compatible) or connected to the GND. VIN and EN
should not be connected together directly. VIN should be
well established and stablized prior to enabling the IC. If no
separate EN signal is available, a 10 kW/100 nF RC network
can be added between VIN and EN to delay the EN signal.
A logic low on EN or high on EN turns-on the device. A logic
high on EN or low on EN turns off device and reduces the
current consumption down to IINOFF.

APPLICATION INFORMATION

Power Dissipation Adjustable Current-Limit Programming


The junction temperature of the device depends on (for adjustable version only)
different contributing factors such as board layout, ambient The NCP380xMUAJAA and NCP380xSNAJAA,
temperature, device environment, etc... Yet, the main respectively mDFN and TSOP6 packages, are proposed to
contributor in terms of junction temperature is the power have current limit flexibility for end Customer. Indeed, Ilim
dissipation of the power MOSFET. Assuming this, the pin is available to connect pull down resistor to ground,
power dissipation and the junction temperature in normal which participate to the current threshold adjustment. It’s
mode can be calculated with the following equations: strongly recommended to use 0.1 or 1% resistor tolerance to
2 keep the over current accuracy.
R D + R DS(on) ǒIOUTǓ (eq. 2) For this resistance selection, Customer should define first
of all, the USB current to sustain, without the device enters
Where:
in the protection sequence. Main rule is to select this pull
PD = Power dissipation (W)
down resistor in order to make sure min current limit is
RDS(on) = Power MOSFET on resistance (W)
above the USB current to provide continuously to the
IOUT = Output current (A)
upstream accessory.
TJ + PD R qJA ) T A (eq. 3) Following, the main table selection contains the USB
Where: current port for the accessory, the standard resistor selection
TJ = Junction temperature (°C) and typical/max over current threshold.
RqJA = Package thermal resistance (°C/W)
TA = Ambient temperature (°C)
Power dissipation in regulation mode can be calculated by
taking into account the drop VIN−VOUT link to the load by
the following relation:
P D + ǒV IN * R LOAD I OCPǓ I OCP (eq. 4)

Where:
PD = Power dissipation (W)
VIN = Input Voltage (V)
RLOAD = Load Resistance (W)
IOCP = Output regulated current (A)

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NCP380, NCV380

Table 5. RESISTOR SELECTION FOR ADJUSTABLE CURRENT LIMIT VERSION


Min Current Selected Resistor Value Maximum
Limit Value Theoric Resistor Value (kW) Typical OCP Target Value Current Value
(A) (kW) 1% or 0.1% (A) (A)
0.5 44.2 44.2 0.59 0.67
0.6 37.5 37.4 0.71 0.81
0.7 32.2 31.6 0.825 0.95
0.8 27.7 27.4 0.94 1.08
0.9 24.0 23.7 1.06 1.22
1.0 21.0 21 1.18 1.35
1.1 18.5 18.2 1.3 1.49
1.2 16.6 16.5 1.41 1.62
1.3 14.6 14.3 1.53 1.76
1.4 13.0 13 1.65 1.9
1.5 11.4 11.3 1.78 2.05
1.6 10.4 10.2 1.88 2.17
1.7 9.2 9.09 2.01 2.31
1.8 8.3 8.25 2.12 2.438
1.9 7.4 7.32 2.23 2.56
2.0 6.5 6.49 2.36 2.7
2.1 5.6 5.49 2.48 2.85

The “Min current limit Value” column, represents the DC Second column is the theoretical resistor value obtained
current to provide to the accessory without over current with following formula to achieve typical current target:
activation.
Rlim + −5.2959 ILIM 5 ) 45.256 ILIM 4 * 155.25 ILIM 3 ) 274.39 ILIM 2 * 267.6 ILIM ) 134.21 (eq. 5)

Rlim Versus OCP Average


48
46
44 RLIM vs. OCP Average
42
40
38
36
34
32
30
28
RLIM (kW)

26
24
22
20
18
16
14
12
10
8
6
4
2
0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8

Current Limit (A)

Figure 25. RLIM Curve vs. Current Limit

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NCP380, NCV380

When the resistor is choosing to fit with the Customer


application, the limits of the over current threshold can be
calculated with the following formula:
IOCP min + 1.6915129 * 0.0330328 Rlim ) 0.0011207(Rlim * 22.375) 2 * 0.0000451 (Rlim * 22.375) 3 )
(eq. 6)
) 0.0000009 (Rlim * 22.375) 4

IOCP max + 2.2885175 * 0.0446914 Rlim ) 0.0015163(Rlim * 22.375) 2 * 0.000061 (Rlim * 22.375) 3 )
(eq. 7)
) 0.0000012 (Rlim * 22.375) 4

IOCPtyp + 1.9900152 * 0.0388621 Rlim ) 0.0013185(Rlim * 22.375) 2 * 0.0000531 (Rlim * 22.375) 3 )


(eq. 8)
) 0.0000011 (Rlim * 22.375) 4

The minimum, typical and maximum current curves are


described in the following graph:

3.0
2.8
IOCP min vs. RLIM
2.6
IOCP vs. RLIM
2.4
IOCP max vs. RLIM
2.2

2.0

1.8
ILIM (A)

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0
5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47

RLIM (kW)

Figure 26. Current Threshold vs. Rlim Resistor

That is recommended to respect 6 kW−47 kW resistor PCB Recommendations


range for two reasons. The NCP380 integrates a PMOS FET rated up to 2 A, and
For the low resistor values, the current limit is pushed up the PCB design rules must be respected to properly evacuate
to high current level. Due to internal power dissipation the heat out of the silicon. The UDFN6 PAD1 must be
capability, a maximum of 2.4 A typical can be set for the connected to ground plane to increase the heat transfer if
mDFN package if thermal consideration are respected. For necessary. This pad must be connected to ground plane. By
the TSOP6 version 1.2 A is the maximum recommended increasing PCB area, the RqJA of the package can be
value because the part could enter in thermal shutdown decreased, allowing higher power dissipation.
mode before constant current regulation mode.
In the other side, if we want to keep 15% of accuracy, high
resistor values can be used up to 50 kW. With higher value,
the current threshold is lower than 500 mA, so in this case
degraded accuracy can be observed.

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Power Supply NCP380
GPM21BR61C106KE15L 1 6
IN IN OUT
10 mF 2 5
4.7 mF GND ILIM 100 mF
3 4 GPM31CR60J107ME39L
EN /FLAG

LDO 3.3 V
1 3
IN OUT
USB Host
Controller
VCC
GND STATUS SYS SYSTEM
EN

19
2

USB USB

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1 Transceiver Transceiver 1
NCP380, NCV380

VCC VCC
5 12 12 5
VBUS VBUS(sense) CRTL[x:0] CRTL_IN[x:0] CRTL_OUT[x:0] CRTL[x:0] VBUS(sense) VBUS
2 11 11 2
D+ D+ DATA[x:0] DATA_IN[x:0] DATA_OUT[x:0] DATA[x:0] D+ D+

Figure 27. USB Host Typical Application


3 3
D− D− D− D−
4 4
GND GND GND GND
GND GND GND
USB Port USB Port
10 10

Upstream USB Port Downstream USB Port


NCP380, NCV380

Table 6. ORDERING INFORMATION


Active Over
Enable Current UL CB
Device Marking Level Limit Evaluation Board Listed Scheme Package Shipping†
NCP380LSNAJAAT1G AAC Adj. NCP380LSNAJAGEVB Y Y TSOP−6
(Pb−Free)
NCP380LSN05AAT1G AC5 0.5 A NCP380LSN05AGEVB Y Y
TSOP−5
NCP380LSN10AAT1G AC6 1.0 A NCP380LSN10AGEVB Y Y (Pb−Free)
Low
NCP380LMUAJAATBG AA Adj. NCP380LMUAJAGEVB Y Y
NCV380LMUAJAATBG* AN Adj. NCP380LMUAJAGEVB Y Y UDFN6
(Pb−Free)
NCP380LMU05AATBG AE 0.5 A NCP380LMU05AGEVB Y Y
NCP380HSNAJAAT1G AAD Adj. NCP380HSNAJAGEVB Y Y TSOP−6
(Pb−Free)
3,000
NCP380HSN05AAT1G AC7 0.5 A NCP380HSN05AGEVB Y Y
TSOP−5 Tape / Reel
NCP380HSN10AAT1G ADA 1.0 A NCP380HSN10AGEVB Y Y (Pb−Free)

NCP380HMUAJAATBG AC Adj. NCP380HMUAJAGEVB Y Y


NCV380HMUAJAATBG* AP Adj. NCP380HMUAJAGEVB Y Y
High
NCP380HMU05AATBG AH 0.5 A NCP380HMU05AGEVB Y Y
NCP380HMU10AATBG AJ 1.0 A NCP380HMU10AGEVB Y Y UDFN6
(Pb−Free)
NCP380HMU15AATBG AK 1.5 A NCP380HMU15AGEVB Y Y
NCP380HMU20AATBG AM 2.0 A NCP380HMU20AGEVB Y Y
NCP380HMU21AATBG AU 2.1 A NCP380HMU21AGEVB Y Y
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable

www.onsemi.com
20
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

TSOP−6
CASE 318G−02
1 ISSUE V
SCALE 2:1 DATE 12 JUN 2012
NOTES:
D 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
H 2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM

ÉÉ
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
6 5 4 L2 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR

ÉÉ
GAUGE
E1 E PLANE GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
1 2 3 5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
L
MILLIMETERS
NOTE 5
M C SEATING
b PLANE DIM MIN NOM MAX

e DETAIL Z A 0.90 1.00 1.10


A1 0.01 0.06 0.10
b 0.25 0.38 0.50
c 0.10 0.18 0.26
D 2.90 3.00 3.10
c E 2.50 2.75 3.00
0.05 A E1 1.30 1.50 1.70
e 0.85 0.95 1.05
L 0.20 0.40 0.60
A1 L2 0.25 BSC
DETAIL Z
M 0° − 10°

STYLE 1: STYLE 2: STYLE 3: STYLE 4: STYLE 5: STYLE 6:


PIN 1. DRAIN PIN 1. EMITTER 2 PIN 1. ENABLE PIN 1. N/C PIN 1. EMITTER 2 PIN 1. COLLECTOR
2. DRAIN 2. BASE 1 2. N/C 2. V in 2. BASE 2 2. COLLECTOR
3. GATE 3. COLLECTOR 1 3. R BOOST 3. NOT USED 3. COLLECTOR 1 3. BASE
4. SOURCE 4. EMITTER 1 4. Vz 4. GROUND 4. EMITTER 1 4. EMITTER
5. DRAIN 5. BASE 2 5. V in 5. ENABLE 5. BASE 1 5. COLLECTOR
6. DRAIN 6. COLLECTOR 2 6. V out 6. LOAD 6. COLLECTOR 2 6. COLLECTOR

STYLE 7: STYLE 8: STYLE 9: STYLE 10: STYLE 11: STYLE 12:


PIN 1. COLLECTOR PIN 1. Vbus PIN 1. LOW VOLTAGE GATE PIN 1. D(OUT)+ PIN 1. SOURCE 1 PIN 1. I/O
2. COLLECTOR 2. D(in) 2. DRAIN 2. GND 2. DRAIN 2 2. GROUND
3. BASE 3. D(in)+ 3. SOURCE 3. D(OUT)− 3. DRAIN 2 3. I/O
4. N/C 4. D(out)+ 4. DRAIN 4. D(IN)− 4. SOURCE 2 4. I/O
5. COLLECTOR 5. D(out) 5. DRAIN 5. VBUS 5. GATE 1 5. VCC
6. EMITTER 6. GND 6. HIGH VOLTAGE GATE 6. D(IN)+ 6. DRAIN 1/GATE 2 6. I/O

STYLE 13: STYLE 14: STYLE 15: STYLE 16: STYLE 17:
PIN 1. GATE 1 PIN 1. ANODE PIN 1. ANODE PIN 1. ANODE/CATHODE PIN 1. EMITTER
2. SOURCE 2 2. SOURCE 2. SOURCE 2. BASE 2. BASE
3. GATE 2 3. GATE 3. GATE 3. EMITTER 3. ANODE/CATHODE
4. DRAIN 2 4. CATHODE/DRAIN 4. DRAIN 4. COLLECTOR 4. ANODE
5. SOURCE 1 5. CATHODE/DRAIN 5. N/C 5. ANODE 5. CATHODE
6. DRAIN 1 6. CATHODE/DRAIN 6. CATHODE 6. CATHODE 6. COLLECTOR

RECOMMENDED GENERIC
SOLDERING FOOTPRINT* MARKING DIAGRAM*
6X
0.60
XXXAYWG XXX MG
G G
1 1
3.20 6X
0.95 IC STANDARD

XXX = Specific Device Code XXX = Specific Device Code


A =Assembly Location M = Date Code
Y = Year G = Pb−Free Package
0.95 W = Work Week
PITCH G = Pb−Free Package
DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering


*This information is generic. Please refer to device data sheet
details, please download the ON Semiconductor Soldering and
for actual part marking. Pb−Free indicator, “G” or microdot “
Mounting Techniques Reference Manual, SOLDERRM/D.
G”, may or may not be present.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB14888C Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: TSOP−6 PAGE 1 OF 1

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com


MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

TSOP−5
CASE 483
5 ISSUE N
1 DATE 12 AUG 2020
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
NOTE 5 D 5X Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
0.20 C A B 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
2X 0.10 T THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
M 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
5 4 FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
2X 0.20 T S
B FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
1 2 3 EXCEED 0.15 PER SIDE. DIMENSION A.
K 5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
B TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
G DETAIL Z
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
A A
MILLIMETERS
TOP VIEW DIM MIN MAX
A 2.85 3.15
B 1.35 1.65
DETAIL Z C 0.90 1.10
J D 0.25 0.50
G 0.95 BSC
C H 0.01 0.10
0.05 J 0.10 0.26
H SEATING K 0.20 0.60
C PLANE
END VIEW M 0_ 10 _
SIDE VIEW S 2.50 3.00

GENERIC
SOLDERING FOOTPRINT*
MARKING DIAGRAM*
1.9
0.074 5 5
0.95
0.037 XXXAYWG XXX MG
G G
1 1
Analog Discrete/Logic

2.4 XXX = Specific Device Code XXX = Specific Device Code


0.094 A = Assembly Location M = Date Code
Y = Year G = Pb−Free Package
1.0 W = Work Week
0.039 G = Pb−Free Package
(Note: Microdot may be in either location)
0.7 *This information is generic. Please refer to
0.028 SCALE 10:1 ǒinches
mm Ǔ
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
*For additional information on our Pb−Free strategy and soldering may or may not be present.
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ARB18753C Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: TSOP−5 PAGE 1 OF 1

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2018 www.onsemi.com


MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

UDFN6 2x2, 0.65P


CASE 517AB
ISSUE C
SCALE 4:1 DATE 10 APR 2013

NOTES:
D A B 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
NOTE 5 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.25MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE

ÍÍ
TERMINALS.
PIN ONE 5. TIE BARS MAY BE VISIBLE IN THIS VIEW AND ARE CONNECTED TO
REFERENCE

ÍÍ
E THE THERMAL PAD.

ÍÍ
MILLIMETERS
DIM MIN MAX
0.10 C
A 0.45 0.55
A1 0.00 0.05
0.10 C END VIEW A3 0.127 REF
TOP VIEW b 0.25 0.35
D 2.00 BSC

ÉÉÉ ÉÉ
A3 A3 D2 1.50 1.70
EXPOSED Cu MOLD CMPD E 2.00 BSC

ÉÉÉ
ÇÇÇ ÉÉ
ÇÇ
DETAIL B E2
0.10 C 0.80 1.00
e 0.65 BSC
A L 0.25 0.35
L1 --- 0.15
6X 0.08 C A1
A1 GENERIC
NOTE 4
SIDE VIEW C SEATING
PLANE
DETAIL B MARKING DIAGRAM*
ALTERNATE
CONSTRUCTIONS

DETAIL A
XXMG
D2 L G
1 3 L L
XX = Specific Device Code
M = Date Code
L1
G = Pb−Free Package
E2 DETAIL A
ALTERNATE TERMINAL
(Note: Microdot may be in either location)
CONSTRUCTIONS *This information is generic. Please refer to
device data sheet for actual part marking.
6 4 6X b Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
e 0.10 M C A B
0.05 M C RECOMMENDED
BOTTOM VIEW
SOLDERING FOOTPRINT*
PACKAGE
OUTLINE 1.70 6X
0.47

0.95 2.30

1
0.65 6X
PITCH 0.40
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98AON22162D Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: UDFN6 2X2, 0.65P PAGE 1 OF 1

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com


ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
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PUBLICATION ORDERING INFORMATION


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Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

ON Semiconductor:
NCP380HMU20AATBG NCP380LMU20AATBG NCP380HMU21AATBG NCP380HMU05AATBG
NCP380HMU10AATBG NCP380HMU15AATBG NCP380HMUAJAATBG NCP380HSN05AAT1G
NCP380HSN10AAT1G NCP380HSNAJAAT1G NCP380LMU05AATBG NCP380LMU10AATBG
NCP380LMU15AATBG NCP380LMUAJAATBG NCP380LSN05AAT1G NCP380LSN10AAT1G NCP380LSNAJAAT1G
NCV380LMUAJAATBG NCV380LMU15AATBG NCP380HSN05AAT2G NCV380HMUAJAATBG

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