UNIT-IV

FUNDAMENTAL OF MICROPROCESSORS
 INTRODUCTION TO MICROPROCESSORS:
A Microprocessor is an important part of a computer architecture without which you will not be
able to perform anything on your computer. It is a programmable device that takes in input performs some
arithmetic and logical operations over it and produces the desired output. In simple words, a Microprocessor is
a digital device on a chip that can fetch instructions from memory, decode and execute them and give results.

 Basics of Microprocessor:
A Microprocessor takes a bunch of instructions in machine language and executes them, telling the
processor what it has to do. Microprocessor performs three basic things while executing the instruction:
1. It performs some basic operations like addition, subtraction, multiplication, division, and some
logical operations using its Arithmetic and Logical Unit (ALU). New Microprocessors also perform
operations on floating-point numbers also.

2. Data in microprocessors can move from one location to another.

3. It has a Program Counter (PC) register that stores the address of the next instruction based on the
value of the PC, Microprocessor jumps from one location to another and takes decisions.

A typical Microprocessor structure looks like this.

 Clock Speed of different Microprocessor:

 16-bit Microprocessor:
8086: 4.7MHz, 8MHz, 10MHz
8088: more than 5MHz
80186/80188: 6MHz
Digital Logic Design and Microprocessor Notes (CSE) Page | 1
 80286: 8MHz
 32-bit Microprocessor:
INTEL 80386: 16MHz to 33MHz
INTEL 80486: 16MHz to 100MHz
PENTIUM: 66MHz
 64-bit Microprocessor:
INTEL CORE-2: 1.2GHz to 3GHz
INTEL i7: 66GHz to 3.33GHz
INTEL i5: 2.4GHz to 3.6GHz
INTEL i3: 2.93GHz to 3.33GHz
We do not have any 128-bit Microprocessor at work at present one of the reasons for this is that
we are a long way from exhausting the 64-bit address space itself, we use it at a constant rate of roughly 2 bits
every 3 years. At present we have only used 48 bits of 64 bits so why require 128-bit address space. Also, 128-
bit Microprocessor would be much slower than the 64 bit Microprocessor.
 Types of Processor:
 Complex Instruction Set Computer (CISC):CISC or Complex Instruction Set Computer is a computer
architecture where instructions are such that a single instruction can execute multiple low-level operations
like loading from memory, storing into memory, or an arithmetic operation, etc. It has multiple addressing
nodes within a single instruction.CISC makes use of very few registers.
Example:
1. Intel 386
2. Intel 486
3. Pentium
4. Pentium Pro
5. Pentium II
 Reduced Instruction Set Computer (RISC): RISC stands for Reduced Instruction Set Computer. It is
designed to reduce the execution time by simplifying the instruction set of the computer. Using RISC
processors, each instruction requires only one clock cycle to execute results in uniform execution time. RISC
makes use of multiple registers to avoid large interactions with memory. It has few addressing nodes.
Example:
1. IBM RS6000
2. MC88100
3. DEC Alpha 21064
 Characteristics of a Microprocessor:
There are three important characteristics of a microprocessor. They are as follows:
1. Clock Speed
2. Word Size
3. Instruction Set
1. Clock Speed:
The speed at which a microprocessor can execute the instructions is called the clock speed. Basically clock speed is
the number of cycles that the processor executes per second. We measure it in MHz (Mega Hertz) or GHz (Giga
Hertz). Here, MHz means 1 million cycles per second and GHz means 1 billion cycles per second. Moreover, a cycle
basically means a single electric cycle. Besides, every microprocessor has an internal clock that regulates the speed
at which it executes the instructions.
2. Word Size:
Digital Logic Design and Microprocessor Notes (CSE) Page | 2
It is the number of bits that a processor can process in a single instruction. Furthermore, the word size decides the
amount of RAM that the processor can access at a time. Moreover, it also decides the number of input and output
pins on the microprocessor. These pins in to decide the architecture of the processor. The number of input and output
pins is always equal. For example, the first commercial processor Intel 4004 was a 4-bit processor. Hence, it has 4
input/output pins. Today, mostly 32-bit or 64-bit are used.
3. Instruction Set:
An instruction is basically a command which tells the computer to operate on some piece of data. The set of machine-
level instructions that a microprocessor executes is the instruction set.
The operations involved in the instructions can be as follows:
 Arithmetic operations
 Logical operations
 Data transfer
 Input/output operations
 control flow
 Comparisons between 8085, 8086 and 80386:

80386
Parameters 8085 Microprocessor 8086 Microprocessor Microprocessor

Year of
1977 1978 1985
Introduction
It is an 8-bit It is a 32-bit
It is a 16-bit microprocessor that
microprocessor that has microprocessor that has
Basic has the ability to function 16-bit
the ability to function 8- the ability to function 32-
data.
bit data. bit data.
Arithmetic logic 8085 contains an 8-bit 8086 contains a 16-bit ALU 80386 contains a 32-bit
unit (ALU) size ALU size. size. ALU size.
It holds 216 bytes or
It holds 220 bytes or 1MB as the
Accessible 64kb as the highest It holds 4GB as the highest
highest accessible memory
memory Scope accessible memory accessible memory scope
scope.
scope.
8086 contains 5MHz, 8MHz, 80386 contains 12MHz to
Frequency of 8085 contains 3MHz of
and 10MHz as three versions of 40MHz of clock
clock an on-chip oscillator.
clock frequency. frequency.
8085 has an 8-bit address 8086 has a 16-bit address bus 80386 has a 32-bit address
Address bus
bus size. size. bus size.
This microprocessor The 80386 microprocessor
The 8086 microprocessor
Pipelining doesn’t support supports pipelining
supports pipelining architecture.
pipelining architecture. architecture.
The 8085 The 8086 microprocessor The 80386 microprocessor
microprocessor supports supports two modes of supports three modes of
Operation mode
a single mode of operations, i.e. minimum and operations, i.e. real,
operation. maximum mode. protected, virtual mode.
Digital Logic Design and Microprocessor Notes (CSE) Page | 3
 It contains 6,500 It contains 2,75,000
Transistors It contains 29,000 transistors.
transistors. transistors.
The operations like
addition, decrement, All the procedures of
subtraction, increment, All the procedures of microprocessors with
comparison, AND, shift, microprocessors with division division and
Operations
OR, and X-OR, can be and multiplication can be multiplication can be
completed by 8085. But, functioned by this processor. functioned by this
it can’t function division processor.
and multiplication
It includes 9 flags. .(sign flag,
It includes 5 flags.(sign
zero flag, auxiliary carry flag,
flag, zero flag, auxiliary
Flags parity flag, carry It includes 4 flags. ().
carry flag, parity flag and
flag,overflow,direction,interrupt
carry flag)
and trap)
Memory It doesn’t allow memory It allows memory
It allows memory segmentation.
Segmentation segmentation. Segmentation.

 Architecture of 8086:

The following diagram shows the architecture of a 8086 Microprocessor.8086

Microprocessor is divided into two functional units, i.e., EU (Execution Unit) and BIU (Bus Interface Unit).

Digital Logic Design and Microprocessor Notes (CSE) Page | 4

 EU (Execution Unit): Execution unit gives instructions to BIU stating from where to fetch the data
and then decode and execute those instructions. Its function is to control operations on data using the
instruction decoder & ALU. EU has no direct connection with system buses as shown in the below
figure, it performs operations over data through BIU.

Let us now discuss the functional parts of 8086 microprocessors:

 ALU:

It handles all arithmetic and logical operations, like +, −, ×, /, OR, AND, NOT operations.

 Flag Register:

It is a 16-bit register that behaves like a flip-flop, i.e. it changes its status according to the result stored
in the accumulator. It has 9 flags and they are divided into 2 groups − Conditional Flags and Control Flags.

U U U U OF DF IF TF SF ZF U AF U PF U CF

 Conditional Flags: It represents the result of the last arithmetic or logical instruction
executed. Following is the list of conditional flags

 Carry flag: This flag indicates an overflow condition for arithmetic operations.
 Auxiliary flag: When an operation is performed at ALU, it results in a carry/barrow from lower
nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), then this flag is set, i.e. carry given by D3 bit
to D4 is AF flag. The processor uses this flag to perform binary to BCD conversion.
 Parity flag: This flag is used to indicate the parity of the result, i.e. when the lower order 8-bits
of the result contains even number of 1’s, then the Parity Flag is set. For odd number of 1’s, the
Parity Flag is reset.
 Zero flag: This flag is set to 1 when the result of arithmetic or logical operation is zero else it is
set to 0.
 Sign flag: This flag holds the sign of the result, i.e. when the result of the operation is negative,
then the sign flag is set to 1 else set to 0.
 Overflow flag: This flag represents the result when the system capacity is exceeded.

 Control Flags: Control flags controls the operations of the execution unit. Following is the list of control
flags.
 Trap flag: It is used for single step control and allows the user to execute one instruction at a time
for debugging. If it is set, then the program can be run in a single step mode.
 Interrupt flag: It is an interrupt enable/disable flag, i.e. used to allow/prohibit the interruption of
a program. It is set to 1 for interrupt enabled condition and set to 0 for interrupt disabled condition.
 Direction flag: It is used in string operation. As the name suggests when it is set then string bytes
are accessed from the higher memory address to the lower memory address and vice-a-versa.

 General purpose register:

Digital Logic Design and Microprocessor Notes (CSE) Page | 5
 There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL. These registers
can be used individually to store 8-bit data and can be used in pairs to store 16bit data. The valid
register pairs are AH and AL, BH and BL, CH and CL, and DH and DL. It is referred to the AX, BX,
CX, and DX respectively.AX, BX, CX, DX, SP, BP, SI, DI are General Purpose Registers.
AX register: It is also known as accumulator register. It is used to store operands for arithmetic
operations.
BX register: It is used as a base register. It is used to store the starting base address of the memory area
within the data segment.
CX register: It is referred to as counter. It is used in loop instruction to store the loop counter.
DX register: This register is used to hold I/O port address for I/O instruction.

 Stack pointer register

It is a 16-bit register, which holds the address from the start of the segment to the memory location,
where a word was most recently stored on the stack.

BP (Base Pointer): Base pointer is used to store the base address of the memory or stack.

SI (Source Index): Source Index is used to hold the index value of source operand for string instructions.

DI (Destination Index): DI is used to hold the index value of destination operand for string instructions.

General purpose registers are used for holding data, intermediate results, counters, mode of addressing and also
for storing effective address.

 BIU (Bus Interface Unit):

BIU takes care of all data and addresses transfers on the buses for the EU like sending addresses,
fetching instructions from the memory, reading data from the ports and the memory as well as writing
data to the ports and the memory. EU has no direction connection with System Buses so this is possible
with the BIU. EU and BIU are connected with the Internal Bus.

It has the following functional parts −

 Instruction queue: BIU contains the instruction queue. BIU gets upto 6 bytes of next
instructions and stores them in the instruction queue. When EU executes instructions and is
ready for its next instruction, then it simply reads the instruction from this instruction queue
resulting in increased execution speed.Fetching the next instruction while the current
instruction executes is called pipelining.
 Segment register: BIU has 4 segment buses, i.e. CS, DS, SS& ES. It holds the addresses of
instructions and data in memory, which are used by the processor to access memory locations.
It also contains 1 pointer register IP, which holds the address of the next instruction to executed
by the EU.
 CS: It stands for Code Segment. It is used for addressing a memory location in the code
segment of the memory, where the executable program is stored.

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 DS: It stands for Data Segment. It consists of data used by the program and is accessed in the
data segment by an offset address or the content of other register that holds the offset address.
 SS: It stands for Stack Segment. It handles memory to store data and addresses during
execution.
 ES: It stands for Extra Segment. ES is additional data segment, which is used by the string to
hold the extra destination data.
 Instruction pointer − It is a 16-bit register used to hold the address of the next instruction to
be executed.
 8086 Pin Diagram: 8086 was the first 16-bit microprocessor available in 40-pin DIP (Dual Inline
Package) chip. Let us now discuss in detail the pin configuration of a 8086 Microprocessor. Here is the
pin diagram of 8086 microprocessor.

Let us now discuss the signals in detail −

 Power supply and frequency signals: It uses 5V DC supply at VCC pin 40, and uses ground
at VSS pin 1 and 20 for its operation.
 Clock signal: Clock signal is provided through Pin-19. It provides timing to the processor for
operations. Its frequency is different for different versions, i.e. 5MHz, 8MHz and 10MHz.
 Address/data bus: AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order
byte data and AD8AD15 carries higher order byte data. During the first clock cycle, it carries
16-bit address and after that it carries 16-bit data.

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 Address/status bus: A16-A19/S3-S6. These are the 4 address/status buses. During the first
clock cycle, it carries 4-bit address and later it carries status signals.
 S7/BHE: BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the
transfer of data using data bus D8-D15. This signal is low during the first clock cycle, thereafter
it is active.
 Read ($\overline {RD}$):It is available at pin 32 and is used to read signal for Read operation.
 Ready: It is available at pin 22. It is an acknowledgement signal from I/O devices that data is
transferred. It is an active high signal. When it is high, it indicates that the device is ready to
transfer data. When it is low, it indicates wait state.
 RESET: It is available at pin 21 and is used to restart the execution. It causes the processor to
immediately terminate its present activity. This signal is active high for the first 4 clock cycles
to RESET the microprocessor.
 INTR: It is available at pin 18. It is an interrupt request signal, which is sampled during the
last clock cycle of each instruction to determine if the processor considered this as an interrupt
or not.
 NMI: It stands for non-mask able interrupt and is available at pin 17. It is an edge triggered
input, which causes an interrupt request to the microprocessor.
 $\overline {TEST}$:This signal is like wait state and is available at pin 23. When this signal
is high, then the processor has to wait for IDLE state, else the execution continues.
 MN/$\overline{MX}$:It stands for Minimum/Maximum and is available at pin 33. It indicates
what mode the processor is to operate in; when it is high, it works in the minimum mode and
vice-aversa.
 INTA: It is an interrupt acknowledgement signal and id available at pin 24. When the
microprocessor receives this signal, it acknowledges the interrupt.
 ALE: It stands for address enable latch and is available at pin 25. A positive pulse is generated
each time the processor begins any operation. This signal indicates the availability of a valid
address on the address/data lines.

 DEN: It stands for Data Enable and is available at pin 26. It is used to enable Trans receiver
8286. The trans receiver is a device used to separate data from the address/data bus.
 DT/R: It stands for Data Transmit/Receive signal and is available at pin 27. It decides the
direction of data flow through the Trans receiver. When it is high, data is transmitted out and
vice-a-versa.
 M/IO: This signal is used to distinguish between memory and I/O operations. When it is high,
it indicates I/O operation and when it is low indicates the memory operation. It is available at
pin 28.
 WR: It stands for write signal and is available at pin 29. It is used to write the data into the
memory or the output device depending on the status of M/IO signal.
 HLDA: It stands for Hold Acknowledgement signal and is available at pin 30. This signal
acknowledges the HOLD signal.
 HOLD: This signal indicates to the processor that external devices are requesting to access the
address/data buses. It is available at pin 31.
 QS1 and QS0: These are queue status signals and are available at pin 24 and 25. These signals
provide the status of instruction queue. Their conditions are shown in the following table −

Digital Logic Design and Microprocessor Notes (CSE) Page | 8

 QS0 QS1 Status

0 0 No operation

0 1 First byte of opcode from the queue

1 0 Empty the queue

1 1 Subsequent byte from the queue

 S0, S1, S2: These are the status signals that provide the status of operation, which is used by the
Bus Controller 8288 to generate memory & I/O control signals. These are available at pin 26,
27, and 28. Following is the table showing their status −

S2 S1 S0 Status

0 0 0 Interrupt acknowledgement

0 0 1 I/O Read

0 1 0 I/O Write

0 1 1 Halt

1 0 0 Opcode fetch

1 0 1 Memory read

1 1 0 Memory write

1 1 1 Passive

 LOCK: When this signal is active, it indicates to the other processors not to ask the CPU to
leave the system bus. It is activated using the LOCK prefix on any instruction and is available
at pin 29.
 RQ/GT1 and RQ/GT0: These are the Request/Grant signals used by the other processors
requesting the CPU to release the system bus. When the signal is received by CPU, then it
sends acknowledgment. RQ/GT0 has a higher priority than RQ/GT1.

 Minimum Mode And Maximum Mode:

In the 8086 microprocessor, there are two modes of operation: minimum mode and
maximum mode.

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 Minimum mode is used when the 8086 microprocessor is operating as a standalone
processor without any external coprocessors or support chips. In this mode, the 8086 uses a single
8-bit bus for both data and instructions, and a single 20-bit address bus. The minimum mode
requires a minimum set of support chips, such as clock generator, address latch, and bus controller.

Maximum mode is used when the 8086 microprocessor is operating with one or more
external coprocessors or support chips. In this mode, the 8086 uses a multiplexed bus for data and
instructions, and a 20-bit address bus. The maximum mode requires additional support chips, such
as a bus controller, a clock generator, and a data buffer.

An 8086 is a 16-bit HMOS microprocessor. It is available in 40 pin DIP chip. It uses a 5V DC

supply for its operation. The 8086 uses a 20-line address bus. It has a 16-line data bus. The 20 lines
of the address bus operate in multiplexed mode. The 16-low order address bus lines have been
multiplexed with data and 4 high-order address bus lines have been multiplexed with status
signals.

1. Minimum Mode:

When MN/MX’ = 1, the 8086 microprocessor runs in the minimum mode. All the control signals
required for memory operations and I/O interfaces are provided by the system’s only processor
running in minimum mode, the 8086, alone. The circuit in this case is simple, but it does not permit
multiprocessing.

In this mode, the microprocessor chip itself transmits all control signals. The system’s latches,
transceiver, clock generator, memory, and I/O devices make up the remaining parts.

Digital Logic Design and Microprocessor Notes (CSE) Page | 10

2. Maximum Mode

When 8086 is used as more than just a processor to perform calculations that is when 8086 is
operating in maximum mode. The MN/MX pin is connected to the ground to operate the 8086 in
maximum mode. The system’s components are identical to those in the minimum mode system.

 Difference between minimum mode and maximum mode in 8086 microprocessor

S.No Minimum mode Maximum mode

1 There can be only one processor. There can be multiple processors.

2 Performance is slower. Performance is faster.

3 The circuit is simple. The circuit is complex.

4 Multiprocessing cannot be
Multiprocessing can be performed.
performed.

5 MN/MX is 1 to indicate the

MN/MX is 0 to indicate the maximum mode
minimum mode.

Digital Logic Design and Microprocessor Notes (CSE) Page | 11

S.No Minimum mode Maximum mode

6 The 8086 generates INTA for The 8288 Bus Controller generates the interrupt
interrupt acknowledgment. acknowledgment signal (INTA).

7 The 8086 itself provides an ALE for Because there are several processors, the 8288 bus
the latch. controller provides ALE for the latch.

8 The system is more affordable. The system costs more money.

9 It is used for small systems. It is used for large systems.

10 The multiprocessor setup is not

The multiprocessor configuration is accepted.
supported.

 Central Processing Unit (CPU): The Central Processing Unit (CPU) is the primary
component responsible for executing instructions and performing calculations. The CPU
serves as the brain of the microprocessor and is a key element in any computer or digital device.

Here are the main functions and components of a CPU within a microprocessor:

1. Control Unit (CU):

 The Control Unit manages and coordinates the operations of the CPU. It fetches
instructions from memory, decodes them, and controls the flow of data between
various components within the CPU.
2. Arithmetic and Logic Unit (ALU):
 The Arithmetic and Logic Unit is responsible for performing arithmetic operations
(addition, subtraction, multiplication, division) and logical operations (AND, OR,
NOT, XOR) on data. The ALU carries out the actual computation based on the
instructions provided by the Control Unit.
3. Registers:
 Registers are small, high-speed storage locations within the CPU used for
temporarily holding data, instructions, and addresses. The registers include:
 Program Counter (PC): Keeps track of the memory address of the next
instruction to be fetched.
 Instruction Register (IR): Holds the current instruction being executed.
 Accumulator: Stores the result of arithmetic and logic operations.
 General-Purpose Registers: Used for various temporary data storage
during processing.
4. Clock and Clock Control:

Digital Logic Design and Microprocessor Notes (CSE) Page | 12

  The CPU operates based on a clock signal, which synchronizes the timing of its
operations. The clock control unit ensures that different parts of the CPU operate
in harmony with the clock signal.
5. Cache Memory:
 Cache memory is a small, high-speed type of volatile computer memory that
provides quick access to frequently used instructions and data. It helps improve the
overall speed and efficiency of the CPU.
6. Bus Interface Unit (BIU) / Memory Management Unit (MMU):
 The Bus Interface Unit manages communication between the CPU and other
components, including memory. The Memory Management Unit may handle
memory-related tasks such as virtual memory management.
7. Instruction Set Architecture (ISA):
 The Instruction Set Architecture defines the set of instructions that the CPU can
execute. It includes operations such as load, store, arithmetic, logic, and control
flow instructions.
8. Flags and Status Register:
 The CPU often includes flags or status bits that indicate the result of certain
operations. Common flags include the zero flag (Z), carry flag (C), sign flag (S),
and overflow flag (V).

 Arithmetic and Logic Unit (ALU):

The Arithmetic and Logic Unit (ALU) is a critical component within a microprocessor responsible
for performing arithmetic and logic operations on binary data. It is an essential part of the Central
Processing Unit (CPU) and plays a key role in executing instructions and manipulating data.

Here are the main functions and features of the Arithmetic and Logic Unit (ALU) in a
microprocessor:

1. Arithmetic Operations:
 Addition: The ALU can perform binary addition, adding two binary numbers
together. It takes two binary inputs and produces a sum.
 Subtraction: Subtraction is often implemented using two's complement
representation. The ALU performs binary subtraction, producing a difference.
 Multiplication: Some ALUs can perform multiplication, usually through a series
of shifts and additions.
 Division: Division is also a complex operation, often implemented through
iterative subtraction and shifting.
2. Logic Operations:
 AND Operation: The ALU performs the bitwise AND operation, where each bit
of the output is the result of the AND operation on the corresponding bits of the
input operands.
 OR Operation: The ALU performs the bitwise OR operation, producing an output
where each bit is the result of the OR operation on the corresponding bits of the
input operands.

Digital Logic Design and Microprocessor Notes (CSE) Page | 13

  XOR Operation: The ALU performs the bitwise XOR (exclusive OR) operation,
where each bit of the output is the result of the XOR operation on the corresponding
bits of the input operands.
 NOT Operation: The ALU can also perform bitwise inversion (NOT operation),
flipping each bit of the input.
3. Data Manipulation:
 The ALU manipulates binary data based on the instructions provided by the Control
Unit. It can shift bits left or right, rotate bits, and perform other operations to modify
data.
4. Registers and Operand Inputs:
 The ALU takes its input from registers or directly from the system's data bus. It
typically has two inputs (operands) and produces a single output (result).
 In a multi-bit ALU, operations are performed in parallel on corresponding bits of
the operands.
5. Control Signals:
 The ALU is controlled by various control signals that specify the operation to be
performed (addition, subtraction, AND, OR, XOR, etc.) and other parameters.
6. Flags and Status Bits:
 The ALU often sets flags or status bits based on the results of operations. Common
flags include the zero flag, carry flag, sign flag, and overflow flag.
7. Output:
 The result of the ALU operation is typically stored in a register or directly sent to
other components of the CPU or memory.
8. Multiplexers and Select Lines:
 The ALU may include multiplexers and select lines that allow the CPU to choose
between different operations, such as selecting between addition and subtraction.

 Address, Data and Control bus:

The 8086 has distinct buses for addressing, data, and control. Here's a brief overview of these
buses in the context of the 8086:

1. Address Bus (A16-A19, A0-A15):

 Width: The 8086 has a 20-bit address bus, allowing it to address 220220 or
1,048,576 different memory locations.
 Segments and Offsets: The 8086 uses a segmented memory model, where the
address is composed of a segment and an offset. The segment and offset are
combined to form the actual physical address.
 Segment Registers: Segment registers like CS (Code Segment), DS (Data
Segment), SS (Stack Segment), and ES (Extra Segment) hold the higher 16 bits of
addresses.
2. Data Bus (D0-D15):
 Width: The data bus of the 8086 is 16 bits wide, allowing it to transfer 16 bits of
data between the microprocessor and memory or peripherals in a single operation.

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 Bidirectional: The data bus is bidirectional, meaning it can be used for both read
and write operations.
3. Control Bus:
 The control bus in the 8086 microprocessor consists of various control signals that
manage the flow of data and operations. Some of the key control signals include:
 RD (Read): Indicates that data is to be read from memory or an I/O device.
 WR (Write): Indicates that data is to be written to memory or an I/O device.
 ALE (Address Latch Enable): Used to latch the address onto the external
address bus during a read or write cycle.
 M/IO (Memory/Input-Output): Specifies whether the current bus cycle is
accessing memory or an I/O device.
 DT/R (Data Transmit/Receive): Indicates the direction of data transfer on
the data bus.
 INTA (Interrupt Acknowledge): Acknowledges interrupt requests.

The coordination of these buses allows the 8086 microprocessor to fetch instructions and data from
memory, execute operations, and communicate with peripherals. The segmentation approach used
by the 8086, where a 20-bit physical address is formed by combining a 16-bit segment address
with a 16-bit offset address, allowed it to address a larger memory space than the actual 16-bit
address bus might suggest.

 Working Registers: The 8086 microprocessor has a set of sixteen 16-bit registers, which can
be used for a variety of purposes. These registers are categorized into different groups based
on their functions. Here's an overview of the working registers in the 8086:

1. Data Registers (AX, BX, CX, DX):

 These are the primary general-purpose data registers.
 Each of these registers can be used for general data storage and manipulation.
 AX (Accumulator) is often used for arithmetic and logic operations.
 BX (Base Register) is often used for addressing data in memory.
 CX (Count Register) is frequently used as a counter in loop operations.
 DX (Data Register) is used for I/O operations and extending the precision of
multiplication and division.
2. Index Registers (SI, DI, BP, SP):

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  SI (Source Index) and DI (Destination Index) are commonly used for string
operations.
 BP (Base Pointer) is typically used as a base address in certain addressing modes.
 SP (Stack Pointer) is used to point to the top of the stack during push and pop
operations.
3. Segment Registers (CS, DS, SS, ES):
 These registers hold segment addresses used in the segmented memory model of
the 8086.
 CS (Code Segment) points to the segment containing the current program or code.
 DS (Data Segment) points to the segment containing data.
 SS (Stack Segment) points to the segment containing the stack.
 ES (Extra Segment) is an additional segment register used for various purposes.
4. Pointer Registers (IP):
 IP (Instruction Pointer) is used to point to the next instruction to be executed within
the current code segment.
5. Flags Register (FLAGS):
 The FLAGS register contains individual bits, known as flags that indicate the status
of various operations.
 Flags include the zero flag (ZF), carry flag (CF), sign flag (SF), overflow flag (OF),
and others.

The working registers play a crucial role in the execution of instructions and data manipulation.
For example, during arithmetic and logic operations, data is often loaded into the AX register, and
the result is stored back in AX or another register as needed. The BX register is commonly used
for base addressing, and the SI and DI registers are often used for string operations.

 Special Function Registers (SFRS):

Special function registers in the 8086 microprocessor:
1. Flag Register (FLAGS):
 The FLAGS register is a 16-bit register that contains individual flags that represent
the status of various operations. Key flags include:
 Zero Flag (ZF): Set if the result of an operation is zero.
Digital Logic Design and Microprocessor Notes (CSE) Page | 16
  Carry Flag (CF): Set if there is a carry-out or borrow into the most
significant bit during arithmetic operations.
 Sign Flag (SF): Reflects the sign of the result (positive or negative).
 Overflow Flag (OF): Indicates if there is signed arithmetic overflow.
 Parity Flag (PF): Set if the number of set bits in the result is even.
2. Segment Registers (CS, DS, SS, ES):
 These registers hold segment addresses and play a crucial role in the segmented
memory model of the 8086:
 Code Segment (CS): Points to the segment containing the current program
or code.
 Data Segment (DS): Points to the segment containing data.
 Stack Segment (SS): Points to the segment containing the stack.
 Extra Segment (ES): An additional segment register used for various
purposes.
3. Pointer Registers (IP, SP, BP, SI, DI):
 These registers are used for addressing and pointing to specific locations in
memory:
 Instruction Pointer (IP): Points to the next instruction to be executed
within the current code segment.
 Stack Pointer (SP): Points to the top of the stack during push and pop
operations.
 Base Pointer (BP): Used as a base address in certain addressing modes.
 Source Index (SI) and Destination Index (DI): Used in string operations.
4. Control Registers (CS, DS, SS, ES):
 The control registers are used to configure and control various aspects of the
microprocessor's operation. For example:
 Status and Control Register (ST0): Controls the operation of the
coprocessor (if present).
 Machine Status Word (MSW): Contains various control bits related to the
microprocessor's operation.
 Task Register (TR): Holds the segment selector for the task being currently
executed.
5. Segment Descriptor Table Registers (GDTR, LDTR):
 These registers are part of the protected mode in later x86 architectures, and they
hold the base address and limit for the Global Descriptor Table (GDTR) and Local
Descriptor Table (LDTR), respectively.
6. Interrupt Descriptor Table Register (IDTR):
 This register holds the base address and limit for the Interrupt Descriptor Table
(IDT) and is used in protected mode.
7. Test Registers (TR0-TR7):
 These registers are part of the Task State Segment (TSS) mechanism used in the
8086 for task switching.
8. Flag Manipulation Instructions (CLC, STC, CMC, CLD, STD, CLI, STI):
 While not registers per se, these instructions directly affect certain flags in the
FLAGS register, altering the microprocessor's operation.

Digital Logic Design and Microprocessor Notes (CSE) Page | 17

 Clock Circuit /Reset Circuit:

In the 8086 microprocessor, clock and reset circuits play crucial roles in the proper functioning of
the processor. Let's discuss these aspects:

Clock Circuit:

The 8086 microprocessor requires a clock signal to synchronize its internal operations. The clock
signal ensures that different parts of the processor operate in harmony and at the correct timing.
The clock signal is provided by an external oscillator circuit connected to the CLK pin of the 8086.

The main features of the clock circuit in the 8086 are:

1. Clock Frequency: The 8086 supports a variable clock frequency. The minimum and
maximum frequencies are specified in the datasheet. The clock frequency determines the
execution speed of instructions.
2. Oscillator Circuit: The external clock is usually generated by an oscillator circuit
connected to the CLK pin. The oscillator generates a stable and precise clock signal.
3. Bus Cycle Timing: The clock signal determines the timing of bus cycles. The 8086
operates on a system of bus cycles, where each instruction or operation takes a certain
number of clock cycles to complete.

Reset Circuit:

The reset circuit is responsible for initializing the microprocessor when power is applied or when
a reset signal is activated. The 8086 has two types of resets:

1. Power-On Reset (POR): This occurs when power is first applied to the microprocessor.
The power-on reset circuit ensures that the processor starts in a known state. It initializes
the internal registers and clears memory to predefined values.
2. External Reset: This can be initiated by an external signal applied to the RESET pin of
the 8086. External resets are used to restart the microprocessor during system operation.

Key aspects of the reset circuit:

 Reset Signal: A low signal on the RESET pin indicates that a reset is active.
 Initialization: During a reset, the microprocessor initializes its internal registers,
instruction pointer, flags, etc.
 Memory State: The reset may also affect the state of external memory and other
peripherals.

 Stack And Stack Pointer:

The stack is a region of memory used for temporary storage of data during program execution. It
operates on a Last In, First Out (LIFO) basis, meaning that the last item placed onto the stack is

Digital Logic Design and Microprocessor Notes (CSE) Page | 18

the first one to be removed. The stack is crucial for handling subroutine calls, storing return
addresses, and managing local variables.

Stack in 8086:

1. Stack Operations:
 Push: Data is placed onto the stack. The SP is decremented, and the data is stored
at the new location pointed to by SS: SP.
 Pop: Data is retrieved from the stack. The data at the location pointed to by SS: SP
is used, and then SP is incremented.
2. Stack Growth:
 In the 8086, the stack grows downward in memory. This means that when data is
pushed onto the stack, the SP is decremented.
3. Stack Size:
 The size of the stack is determined by the size of the stack segment (SS). For
example, in real mode, where each segment can be up to 64 KB, the stack can
potentially grow up to 64 KB.
4. Instructions:
 The 8086 provides instructions like PUSH and POP to facilitate stack operations.
For example, PUSH AX pushes the contents of the AX register onto the stack, and
POP BX retrieves the top of the stack into the BX register.

Digital Logic Design and Microprocessor Notes (CSE) Page | 19

 Program Counter:The Program Counter (PC) in the context of the 8086 microprocessor is
more commonly referred to as the Instruction Pointer (IP). The IP is a 16-bit register that plays

Digital Logic Design and Microprocessor Notes (CSE) Page | 20

 a crucial role in the execution of programs. It is used to keep track of the memory address of
the next instruction to be executed.

Key Points about the 8086 Instruction Pointer (IP):

1. Size:
 The IP register is 16 bits wide, allowing it to hold a 16-bit memory address. The
8086 is a 16-bit microprocessor, and its architecture is based on 16-bit data and
addresses.
2. Role in Instruction Fetch:
 During the fetch-execute cycle, the IP is used to determine the memory address of
the next instruction. The instruction at this address is then fetched from memory for
execution.
3. Automatic Increment:
 After fetching an instruction, the IP is automatically incremented to point to the
next memory location. The amount of increment depends on the size of the
instruction. For example, if the instruction is two bytes long, the IP is incremented
by 2.
4. Branching and Control Transfer:
 Branch instructions, such as jumps and calls, can modify the content of the IP,
causing control to transfer to a different part of the program.
5. IP in Conjunction with CS:
 The CS (Code Segment) register works in conjunction with the IP to form the
complete address of the next instruction. The physical address of the instruction is
given by the formula: CS * 16 + IP.
6. Initialization:
 At the start of a program or after a reset, the IP is typically initialized to the address
of the first instruction to be executed.

Example in Assembly Language:

Digital Logic Design and Microprocessor Notes (CSE) Page | 21
Here's a simple example in 8086 assembly language to illustrate the role of the IP:

Assembly Copy code:

ORG 1000H; Set the origin address to 1000H

MOV AX, 1234; Load a value into AX

ADD AX, 5678; Add another value to AX

In this example, at the beginning of the program, the IP is set to 1000H (the origin address). The
instructions at memory addresses 1000H and 1002H are fetched and executed sequentially. After
the execution of each instruction, the IP is automatically incremented to point to the next
instruction.

 Interrupts in 8086 microprocessor:

Interrupts are signals or events that can temporarily suspend the normal program execution and
transfer control to a specific interrupt service routine (ISR).There are two types of interrupts in the
8086: hardware interrupts and software interrupts.

1. Hardware Interrupts in 8086:

The 8086 microprocessor has a total of 256 interrupt vectors, numbered from 0 to 255. These
vectors are addresses in memory where the interrupt service routines (ISRs) are located. The
hardware interrupts are classified into two types: maskable and non-maskable.

1. Maskable Interrupts (INTR):

 These interrupts can be masked (disabled) or unmasked (enabled) using the
Interrupt Flag (IF) in the FLAGS register.
 When a maskable interrupt occurs, the processor checks the IF flag. If IF is set (1),
the interrupt is serviced; if IF is clear (0), the interrupt is ignored.
Digital Logic Design and Microprocessor Notes (CSE) Page | 22
 
Examples of maskable interrupts include external hardware interrupts (INT0 to
INT7) and the interrupt generated by the Programmable Interrupt Controller (PIC).
2. Non-Maskable Interrupt (NMI):
 This is a higher-priority interrupt that cannot be disabled by clearing the Interrupt
Flag (IF).
 NMI is generally used for critical events that need immediate attention, such as
hardware errors.
 The NMI interrupt vector is 2.

2. Software Interrupts in 8086:

Software interrupts are triggered by specific instructions in the program, and they are also known
as software traps. The INT instruction is used to generate a software interrupt. When a software
interrupt occurs, control is transferred to the specified interrupt vector.

Examples of software interrupts include:

 INT 10h: Video Services

 INT 21h: DOS Services
 INT 13h: Disk Services

 INT- Interrupt instruction with type number: It is 2-byte instruction. First byte provides
the op-code and the second byte provides the interrupt type number. There are 256 interrupt
types under this group.

The starting address for type0 interrupt is 000000H, for type1 interrupt is 00004H similarly for
type2 is 00008H and ……so on. The first five pointers are dedicated interrupt pointers. i.e. −

 TYPE 0 interrupt represents division by zero situation.

 TYPE 1 interrupt represents single-step execution during the debugging of a program.
 TYPE 2 interrupt represents non-maskable NMI interrupt.
 TYPE 3 interrupt represents break-point interrupt.
 TYPE 4 interrupt represents overflow interrupt.

The interrupts from Type 5 to Type 31 are reserved for other advanced microprocessors, and
interrupts from 32 to Type 255 are available for hardware and software interrupts.

 INT 3-Break Point Interrupt Instruction: It is a 1-byte instruction having op-code is CCH.
These instructions are inserted into the program so that when the processor reaches there, then
it stops the normal execution of program and follows the break-point procedure.
 INTO-Interrupt on overflow instruction: It is a 1-byte instruction and their
mnemonic INTO. The op-code for this instruction is CEH. As the name suggests it is a
conditional interrupt instruction, i.e. it is active only when the overflow flag is set to 1 and
branches to the interrupt handler whose interrupt type number is 4. If the overflow flag is reset
then, the execution continues to the next instruction.

Digital Logic Design and Microprocessor Notes (CSE) Page | 23

 Data and Program Memory in 8086:

Segmentation is the process in which the main memory of the computer is logically divided into
different segments and each segment has its own base address. It is basically used to enhance the
speed of execution of the computer system, so that the processor is able to fetch and execute the
data from the memory easily and fast. Memory is organized into segments, and it uses a segmented
memory model. Each segment is 64 kilobytes (64 KB) in size, and the processor has the capability
to address up to 1 megabyte (MB) of physical memory. The memory is divided into two main
types: data memory and program memory.

1. Data Memory:

The data memory in the 8086 is used for storing variables, arrays, and other data used by the
program. The primary data segments in the 8086 are:

 Data Segment (DS): This segment is used to point to the segment containing data used by
the program. The DS register is often used as an index to access data in memory.
 Extra Segment (ES): The ES register is an additional segment register that can be used
for certain string operations and accessing extra data segments.
 Stack Segment (SS): The SS register points to the segment containing the stack. The stack
is used for storing temporary data, local variables, and return addresses for procedure calls.

Digital Logic Design and Microprocessor Notes (CSE) Page | 24

The addressing of data in memory is done using a combination of a segment register and an offset.
The effective address is calculated as follows:

Effective Address= (Segment Register×16) +Offset

2. Program Memory:

The program memory in the 8086 is used for storing executable code. The primary code segment
is:

 Code Segment (CS): This segment holds the base address of the segment containing the
executable code. The IP (Instruction Pointer) register, combined with CS, points to the current
instruction being executed.

When the processor fetches an instruction, it calculates the physical address of the instruction using
the CS register and IP register:

Physical Address= (CS×16) +IP

The 8086 uses a 16-bit addressing scheme, and the combination of CS and IP forms a 20-bit
physical address.

Digital Logic Design and Microprocessor Notes (CSE) Page | 25

 UNIT-V
8086 INSTRUCTION SET AND PROGRAMMING

 Introduction of Addressing Mode: Addressing modes in the context of a microprocessor refer to the
methods or techniques used to specify the operand of an instruction. The 8086 microprocessor, part of
the x86 family, supports various addressing modes, providing flexibility for programmers to access and
manipulate data in different ways. These addressing modes play a crucial role in assembly language
programming.
 Addressing Modes Of 8086: Different addressing modes provide flexibility in programming and allow
efficient manipulation of data. Here are some of the addressing modes supported by the 8086:
1. Immediate Addressing Mode:
 The operand is a constant data value specified directly in the instruction.
 Example: MOV AX, 1234H (Move the immediate value 1234H to the AX register).
2. Register Addressing Mode:
 The operand is a register.
 Example: MOV CX, BX (Move the contents of register BX to register CX).
3. Direct Addressing Mode:
 The operand is specified by a memory address.
 Example: MOV AL, [1234H] (Move the byte at memory address 1234H to register AL).
4. Register Indirect Addressing Mode:
 The operand is stored at the address contained in a register.
 Example: MOV DL, [SI] (Move the byte at the address in the SI register to register DL).
5. Base-Register Addressing Mode:
 The operand is located at an address formed by adding a constant displacement to the contents of a base
register (BX or BP).
 Example: MOV AL, [BX+10] (Move the byte at the address BX+10 to register AL).
6. Index-Register Addressing Mode:
 The operand is located at an address formed by adding a constant displacement to the contents of an
index register (SI or DI).
 Example: MOV AX, [SI+20] (Move the word at the address SI+20 to register AX).
7. Base-Register with Index Addressing Mode:
 The operand is located at an address formed by adding a constant displacement to the sum of the
contents of a base register and an index register.
 Example: MOV AX, [BX+SI+30] (Move the word at the address BX+SI+30 to register AX).
8. Base-Register with Index and Displacement Addressing Mode:
 Similar to the base-register with index addressing mode, but with an additional constant displacement.
 Example: MOV CX, [BX+SI+10] (Move the word at the address BX+SI+10 to register CX).
9. Relative Addressing Mode:
 Used with branch instructions, where the operand is a signed byte or word that specifies a displacement
relative to the address of the next instruction.
 Example: JMP SHORT Label (Jump to the instruction at the specified label).

Digital Logic Design and Microprocessor Notes (CSE) Page | 26

 Instruction syntax for addressing modes: The syntax for instructions in assembly language
programming for the 8086 microprocessor varies based on the addressing mode used.
1. Immediate Addressing Mode:
 Syntax: INSTRUCTION DESTINATION, IMMEDIATE_DATA
 Example: MOV AX, 1234H
2. Register Addressing Mode:
 Syntax: INSTRUCTION DESTINATION_REGISTER, SOURCE_REGISTER
 Example: MOV CX, BX
3. Direct Addressing Mode:
 Syntax: INSTRUCTION REGISTER, [MEMORY_ADDRESS]
 Example: MOV AL, [1234H]
4. Register Indirect Addressing Mode:
 Syntax: INSTRUCTION REGISTER, [BASE_REGISTER]
 Example: MOV DL, [SI]
5. Base-Register Addressing Mode:
 Syntax: INSTRUCTION REGISTER, [BASE_REGISTER +
CONSTANT_DISPLACEMENT]
 Example: MOV AL, [BX+10]
6. Index-Register Addressing Mode:
 Syntax: INSTRUCTION REGISTER, [INDEX_REGISTER +
CONSTANT_DISPLACEMENT]
 Example: MOV AX, [SI+20]
7. Base-Register with Index Addressing Mode:
 Syntax: INSTRUCTION REGISTER, [BASE_REGISTER + INDEX_REGISTER]
 Example: MOV AX, [BX+SI+30]
8. Base-Register with Index and Displacement Addressing Mode:
 Syntax: INSTRUCTION REGISTER, [BASE_REGISTER + INDEX_REGISTER +
CONSTANT_DISPLACEMENT]
 Example: MOV CX, [BX+SI+10]
9. Relative Addressing Mode (for branch instructions):
 Syntax: JUMP_INSTRUCTION LABEL_OR_OFFSET
 Example: JMP SHORT Label
Note: Replace INSTRUCTION with the actual mnemonic of the instruction, such as MOV, ADD, SUB,
etc. Replace REGISTER, DESTINATION, and SOURCE_REGISTER with the appropriate register
names like AX, BX, SI, DI, etc. Replace MEMORY ADDRESS with the specific memory address in
direct addressing mode. Replace LABEL_OR_OFFSET with the label or offset in relative addressing
mode.

 Data types:
Data types used in programming for the 8086 microprocessor:
1. Byte (8 bits):
Digital Logic Design and Microprocessor Notes (CSE) Page | 27
  A single byte is the smallest addressable unit of memory.
 Example: BYTE_VAR DB 65
2. Word (16 bits):
 A word consists of two bytes or 16 bits.
 Example: WORD_VAR DW 1234H
3. Double word (32 bits):
 While the 8086 is a 16-bit processor, programmers can still work with 32-bit values by using two
consecutive words.
 Example: DWORD_VAR DD 12345678H
4. String:
 A series of consecutive bytes representing characters or data.
 Example: STRING_VAR DB 'Hello'
5. Integer:
 Typically a 16-bit signed or unsigned integer.
 Example: INTEGER_VAR DW 32767
6. Floating Point:
 Floating-point representation is not native to the 8086, but it can be emulated using software or
dedicated co-processors.
 Example (using software emulation):
Assembly Copy code
FLOAT_VAR DD 3.14
7. Packed BCD (Binary Coded Decimal):
 Each decimal digit is packed into a nibble (4 bits).
 Example: BCD_VAR DB 09H (represents the decimal value 9)
8. ASCII Character:
 A single byte representing an ASCII character.
 Example: CHAR_VAR DB 'A'
9. Pointer:
 A 16-bit value representing a memory address.
 Example: PTR_VAR DW 1234H
10. Segment:
 A 16-bit value representing a segment address.
 Example: SEGMENT_VAR DW 0000H
These data types are declared in assembly language using directives such as DB (Define Byte), DW (Define
Word), DD (Define Double word), etc. The choice of data type depends on the nature of the data being
represented and the requirements of the program.

 Instruction set of 8086:

We are having different types of instructions of 8086.they are given below.

1. Data Transfer Instructions
2. Arithmetic Instructions
Digital Logic Design and Microprocessor Notes (CSE) Page | 28
 3. Logical Instructions
4. Branch Instructions
5. String Manipulating Instructions
6. Flag Manipulation Instructions

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