Scribd
Upload
21 views2 pages

EC6201

Uploaded by

detej79667
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
21 views2 pages

EC6201

Uploaded by

detej79667
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

NATIONAL INSTITUTE OF TECHNOLOGY, ROURKELA – 769 008

Electronics & Communications Engineering Department


M.Tech, End Semester Examination 2022-2023
Subject: Digital VLSI Design Subject ID: EC-6201
Max Marks: 50 Time: 2 Hrs
Answer all questions
ANSWER TO THE PARTS OF SAME QUESTION MUST BE DONE AT ONE PLACE.
Figures in right margin indicate marks. This question paper contains two pages.
Unless specifically mentioned u can assume the followings.
 n C ox  110A / V 2 ,  p C ox  50A / V 2 , Vdd  5V, Vtn  1V, Vtp  1V
 ox  0.351pf / cm,  Si  1.035pf / cm,  n  2 p

1. i) Explain thermal oxidation in CMOS fabrication with its types and application scenario.
[2
ii) Differentiate between photolithography and etching. [3
iii) Depict the six steps involved in patterning of Silicon Dioxide in a CMOS process. [2

2. (i) How can a designer manage the crossing of data from one frequency domain to other
domain? [2
(ii) In a RTL net list explain the dependency of contamination delay with the circuit hold margin.
What would be the highest operating frequency if the circuit has a 4ns set up time with the
propagation delay of 10ns and a clock to output delay of 3ns. [2
(iii) What is clock jitter and what are its sources? Enumerate the combined impact of skew and
jitter on the frequency of operation of the circuit. [3

′
3. Consider the Boolean function 𝐹 = (𝐴. (𝐵 + 𝐶) + 𝐷. 𝐸)
(i). Draw a static CMOS circuit to realize the function F. [3
(ii). Draw a Dynamic CMOS circuit to realize F. [2
(iii). Find an equivalent CMOS inverter circuit for simultaneous switching of all inputs
𝑊 𝑊
assuming that ( 𝐿 ) = 15 for all PMOS transistors and ( 𝐿 ) = 10 for all NMOS
𝑃 𝑁
transistors. [2

Page 1 of 2
4. (i) Prove analytically that a logic ‘1’ through an nMOS pass transistor cannot exceed
(𝑉𝑑𝑑 − 𝑉𝑡𝑛 ) [3

(ii) Realize a 2:1 multiplexer using transmission gates. [2


(iii) Estimate the output of the following TG based circuit. [2

5. (i) Implement the following function


𝐹 = 𝐴𝐵 + 𝐶(𝐷 + 𝐸) using CMOS domino logic [3

(ii) What are limitations associated with domino logic? Discuss any one measure to alleviate
this problem in domino logic. [4
6. (i) Explain the write operation in the circuit topology of a 6-T CMOS SRAM cell. [2
(ii) In the design of a SRAM cell estimate the upper limit of the ratio of access and driver
NMOS transistor aspect ratios in a 5V supply voltage. Also find the same ratio for load
PMOS and access NMOS transistors. [3
(iii) Explain the operations of a flash memory cell. Compare the characteristics of a NOR and
NAND flash cells. [3
7. (i) What is DFT? Explain principle of controllability and observability. [3
(ii) How to handle large circuits with partition-and-mux adhoc technique? [2
(iii)What are process variations in CMOS IC fabrication? Suggest a technique to account for
that during the IC design. [2

All the best.

Page 2 of 2

You might also like