NPTEL Online Certification Courses

Indian Institute of Technology Kharagpur

Digital Circuits
Assignment 4- Week 4
TYPE OF QUESTION: MCQ
Number of questions: 15 Total mark: 15 X 1 = 15
______________________________________________________________________________

QUESTION 1:
Which of the following property is WRONG?
A) A XOR 0 = A’
B) A XOR 1 = A’
C) A XOR A = 0
D) A XOR A’ = 1

Correct Answer: A
Detailed Solution:

A XOR 0 = A.0’ + A’.0 = A.1 + 0 = A

So option is Correct
_____________________________________________________________________________

QUESTION 2:
Minimum number of NAND gates are required to design a 2-input XOR gate is ___________.
A) 3
B) 4
C) 5
D) 6

Correct Answer: B
Detailed Solution:

4 NAND gates are sufficient to design an XOR gate

 NPTEL Online Certification Courses
Indian Institute of Technology Kharagpur

QUESTION 3:

Which of the following logic function is implemented by the circuit given below?

A) NAND
B) NOR
C) XOR
D) XNOR

Correct Answer: A

Detailed Solution:
______________________________________________________________________________

QUESTION 4:
How many transistors are required to design a CMOS 2-input NOR gate?
A) 2 PMOS and 1 NMOS transistors
B) 1 PMOS and 2 NMOS transistors
C) 3 PMOS transistors
D) 2 PMOS and 2 NMOS transistors

Correct Answer: D
Detailed Solution:

2 NMOS and 2 PMOS transistors are required to design 2-input CMOS NOR gate
______________________________________________________________________________
 NPTEL Online Certification Courses
Indian Institute of Technology Kharagpur

QUESTION 5:
What is a hazard in digital circuits?
A) An error in the physical layout of the circuit
B) A temporary fluctuation in output due to changes in input
C) A permanent fault in the circuit
D) A delay in the clock signal

Correct Answer: B

Detailed Solution:
A temporary fluctuation in output due to changes in input

____________________________________________________________________________

QUESTION 6:
In digital circuits, what type of hazard occurs when a single input change causes multiple
changes in output before settling?
A) Static-1 hazard
B) Static-0 hazard
C) Dynamic hazard
D) Glitch hazard

Correct Answer: C

Detailed Solution:
Gate delays cause multiple transitions at the output for changes in the input
______________________________________________________________________________

QUESTION 7:
A static-0 hazard in a digital circuit occurs when:
A) The output should remain 0, but temporarily goes to 1
B) The output should remain 1, but temporarily goes to 0
C) The output oscillates between 0 and 1
D) The output remains at a constant 0

Correct Answer: A

Detailed Solution:

Output should stay logic 0, but gate delays cause brief glitch to logic 1.

______________________________________________________________________________
 NPTEL Online Certification Courses
Indian Institute of Technology Kharagpur

QUESTION 8:
Which of the following options correctly represents the SUM and CARRY outputs for a half
adder?
A) SUM = A XOR B, CARRY = A.B
B) SUM = A XNOR B, CARRY = A.B
C) SUM = A XOR B, CARRY = A+B
D) SUM = A.B, CARRY = A XOR B

Correct Answer: A
Detailed Solution:
Refer lecture material
______________________________________________________________________________

QUESTION 9:

What is the primary difference between a half adder and a full adder?

A) A half adder can add two bits while a full adder can add three bits including the carry.
B) A half adder can subtract two bits while a full adder can add two bits.
C) A half adder can add three bits while a full adder can add two bits including the carry.
D) A half adder can multiply two bits while a full adder can add two bits.

Correct Answer: A

Detailed Solution:
______________________________________________________________________________

QUESTION 10:
How many half adders are required to construct a full adder?
A) 1
B) 2
C) 3
D) 4

Correct Answer: B

Detailed Solution:

Two half adder and one OR gate is required to design a full adder
 NPTEL Online Certification Courses
Indian Institute of Technology Kharagpur

QUESTION 11:
When the set of input data to an even parity generator is 01111, the output will be
A) 1
B) 0
C) Don’t care
D) Depends on the previous input

Correct Answer: B

Detailed Solution:

Even parity generator must produce a 1 for all the input combinations that contain an odd
number of 1s.
______________________________________________________________________________

QUESTION 12:
Consider the circuit shown below. Which of the following statements correctly describe the
output X?

A) X is the generated carry-out bit

B) X is equal to logic 1 when addition is performed and X is equal to logic 0 when
subtraction is done.
C) X is equal to logic 1 if there is an overflow during either addition or subtraction.
D) X is equal to logic 0 if there is an overflow during either addition or subtraction.

Correct Answer: C

Detailed Solution:

______________________________________________________________________________
 NPTEL Online Certification Courses
Indian Institute of Technology Kharagpur

QUESTION 13:
The product term to be included to remove possible static hazard for the function f(Y,W,X)=WX + W’Y’ is
A) WY’
B) XY’
C) W’X’
D) XY
Correct Answer: B

Detailed Solution:

______________________________________________________________________________

QUESTION 14:
Which of the following statement if FALSE?
A) Parity checking circuits are used for error dectection and correction
B) Parity generator circuit generates the parity bit before transmitting.
C) Parity checker circuits checks the parity at the reciever
D) Even parity checker output logic 1 when input contains even number of logic 1s
Correct Answer: D

Detailed Solution:
______________________________________________________________________________
QUESTION 15:
How many minimum number of transistors required to design a CMOS inverter?
A) 1 PMOS and 1 NMOS
B) 2 PMOS and 1 NMOS
C) 2 NMOS
D) 2 PMOS
Correct Answer: A

Detailed Solution:
________________________________________________________________

************END*******