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Department of Computer Science Engineering

DECO FINAL QUESTION BANK

UNIT-1
SAQ:
1)Find the 2’s complement of (101101)2.

R=2

M=101101

N=6

2’s complement of (101101)2.:

=2^6-101101
=1000000-101101

1 1 1 1
1

1 0 0 0 0 0 0

- 0 1 0 1 1 0 1

0 0 1 0 0 1 1

2’s complement of (101101)2=(010011)₂.

2) State and Explain the De Morgan’s Theorem

It describes the relationship between the complement of a logical expression and the
complement of its components.
First De Morgan's Theorem: It states that the complement of the logical AND of two
expressions is equal to the logical OR of the complements of the individual expressions.
(A.B)’=A’+B’

Second De Morgan's Theorem: It states that the complement of the logical OR of two
expressions is equal to the logical AND of the complements of the individual expressions.
(A+B)’=A’B’
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3) prove that ABC+ABC’+AB’C+A’BC=AB+AC+BC

4) Convert (4021.2)5to decimal number.

(4021.2)5 = ( ? )10

Solution:

(4021.2)5=(_______)10

4021.2

=4×53+0×52+2×51+1×50+2×151
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=4×125+0×25+2×5+1×1+2×0.2

=500+0+10+1+0.4

=511.4
∴ (4021.2)5=(511.4)10

5a) Convert (101101)2 to Gray code

b)Convert (1010) from Gray code to binary
a)Binary code : 101101

Method-1: (Binary to Gray code)

g5=b5=1

g4=b5⊕b4=1⊕0=1

g3=b4⊕b3=0⊕1=1

g2=b3⊕b2=1⊕1=0

g1=b2⊕b1=1⊕0=1

g0=b1⊕b0=0⊕1=1

∴ Gray code : 111011

b) Gray code : 1010

Method-1: (Gray code to Binary)

b3=g3=1

b2=b3⊕g2=1⊕0=1

b1=b2⊕g1=1⊕1=0

b0=b1⊕g0=0⊕0=0

∴ Binary : 1100

6. Which gates are called as the universal gates? What are its advantages?
The gates called universal gates are the NAND gate and the NOR gate. These gates are considered
universal because any other logical operation or gate can be constructed using combinations of
either NAND gates or NOR gates.
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Advantages of Universal Gates:

1) Simplicity
2) Cost-Effectiveness
3) Flexibility
7. Prove the following Expressions.
i) A+AB=A ii) A(A’+B) =AB
i) LHS:
A + AB
= A(1 + B) (Distributive Law)
= A(1) (Identity Law)
=A (Identity Law)
=RHS (Hence Proved)
ii)LHS:
A(A' + B)
= AA' + AB (Distributive Law)
= 0 + AB (Complement Law)
= AB (Identity Law)
=RHS (Hence Proved)
LAQ:

1,a) Convert i) (11101001110)2=()8

(ii) (A0CB.EE)16 =()10
(iii) (235)10= ( )16

(11101001110)2=()8
Solution:

(11101001110)2=(_______)8
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011 101 001 110
3 5 1 6
∴ (11101001110)2=(3516)8
(ii) (A0CB.EE)16 =()10

Solution:

(A0CB.EE)16=(_______)10

=A×16^3+0×16^2+C×16^1+B×16^0+E×16^-1+E×16^-2

=10×4096+0×256+12×16+11×1+14×0.0625+14×0.00391

=40960+0+192+11+0.875+0.05469

=41163.92969

∴ (A0CB.EE)16=(41163.92969)10

iii)

Solution:

(235)10=(_______)16

16 235
16 14 -11 ↑B
0 -14 ↑E

∴ (235)10=(EB)16
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b) Show how to connect NAND gates to get an AND gate and OR gate?

2.) a) write the decimal number 5 in the weighted code form of

 8421
 5211
b) Express the function Y=A+B’C in canonical SOP and canonical POS form
a) i) 8 4 2 1
8 4 2 1
0 1 0 1

ii)

5 2 1 1
1 0 0 0

b)

To express the function Y = A + B'C in canonical Sum of Products (SOP) and canonical Product of Sums
(POS) forms, we first need to expand the given expression using Boolean algebra rules.

Given function: Y = A + B'C

### Canonical SOP form:

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In the canonical SOP form, we express the function as a sum of products where each term includes all
the variables in the function.

1. We create a truth table for the function Y = A + B'C :

A B C Y

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 1

2. Now, we examine the rows where Y = 1 and write down the corresponding minterms:

Y = Σm(1, 2, 5, 6, 7, 8)

3. Finally, we express the function in canonical SOP form:

Y{SOP} = A'B'C + A'BC' + ABC + AB'C' + ABC' + AB'C

### Canonical POS form:

In the canonical POS form, we express the function as a product of sums where each term corresponds
to a row in the truth table where the function evaluates to 0.

From the truth table, rows where Y = 0 are:

Y = Pi(3, 4)
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2. We express the function in canonical POS form:

Y_{POS} = (A+B+C')(A+B'C)

This represents the canonical POS form of the function.

3.) Evaluate the following Boolean expression using Boolean Algebra and draw the logic
diagram.
(a) F(X,Y,Z) =(X +Y)(X’(Z’+Y’))’+X’Y’+X’Z’.
(b) F(A,B,C,D)=AB’C+B+BD’+ABD’+AC’
F(X,Y,Z) =(X +Y)(X’(Z’+Y’))’+X’Y’+X’Z’.
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Non minimized Minimized

F(A,B,C,D)=AB’C+B+BD’+ABD’+AC’
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Non minimalized form

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4 a) Explain about Boolean postulates and laws.
Postulates of Boolean Algebra:

A postulate is a statement that is presumed to be true when it hasn’t been proven. Postulates in
Boolean algebra are not laws and theorems but statements that hold true. The four potential logical
OR and logical AND operations, as well as the rules followed by the NOT operator, are included in
these postulates. The postulates in Boolean algebra is given below:

0+0=0

0+1=1

1+0=1

1+1=1

0.0=0

0.1=0

1.0=0

1.1=1

1′ = 0

0′ = 1

Boolean Algebra Laws:

Distributive Law:

According to distributive law, if we perform the OR operation of two or more variables and then
perform the AND operation of the result with a single variable, the result will be similar to
performing the AND operation of that single variable with each two or more variable and then
perform the OR operation of that product. For three variables, the distributive law is written as:

A (B + C) = AB + AC

A + (B.C) = (A + B) (A + C)

Associative Law:

The associative law states that the operation can be performed in any order when the variable’s
priority is the same. As ‘multiplication’ and ‘division’ have the same priority. For three variables,
the associative law is written as:

A + (B + C) = (A + B) + C

A. (B.C) = (A.B).C

Commutative LaThis law states that no matter in which order we use the variables. It means the
order of variables doesn’t matter. For two variables, the commutative law is written as:
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A+B=B+A

A.B = B.A

Absorption Law:

This law allows us to absorb similar variables. The absorption law is written as:

B + (B.A) = B

B.(B + A) = B

A + A’.B = A + B

A.(A’ + B) = A.B

AND Law:

These laws use the AND operation. Therefore, they are known as AND laws. The AND law is written
as:

A.0 = 0

A.1 = A

A.A = A

A.A’ = 0

OR Law:

These laws use the OR operation. Therefore, they as known as OR laws. The OR law is written as:

A+0=A

A+1=A

A+A=A

A + A’ = 1

(b) construct the hamming code for BCD 0110. using even parity.

Given data: 0110

m=4

condition : 2^r >=r+m (Note: the correct condition is 2^r >=r+m+1 but the faculty has mentioned

that 2^r >=r+m should be followed)

2^1 >= 1+4 false

2^2 >=2+4 false

2^3 >= 3+4 true

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Therefore r=3

Since r=3 parity p1 , p2 , p4 exist,

M+r 1 2 3 4 5 6 7
Coded data P1 P2 D1 P4 D2 D3 D4
Parity bits 1 1 0 0 1 1 0
P1 1 0 1 0
(1,3,5,7)
P2 1 0 1 0
(2,3,6,7)
P4 0 1 1 0
(4,5,6,7)
ENCODER OF HAMMING CODE:

HAMMING CODE: 1100110

5a) subtract the following numbers using 10’s complement

i) 24-09 ii)69-32 iii)347-265

b) Explain various logic gates with truth table and logic diagram

a)i)24-09

M=24

N=09

R=10

n=2

10’s complement of 09:

=10^2-9

=91

Result=M+10’s complement of N

Ie;

Result =24+91 (since end carry exist discard it)

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1
2 4
+ 9 1

1 1 5

The left most bit of the result is 1, called carry and it is ignored.
So answer is 15

ii) 69-32

M=69

N=32

R=10

n=2

10’s complement of 09:

=10^2-32

=68

Result=M+10’s complement of N

Ie;

Result=M+10’s complement of N

Ie;

Result =69+68 (since end carry exist discard it)

1
6 9
+ 6 8

1 3 7

The left most bit of the result is 1, called carry and it is ignored.
So answer is 37

iii)347-265
M=347

N=265

R=10
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n=3

10’s complement of 265:

=10^3-265

=735

Result=M+10’s complement of N

Ie;

Result =347+735 (since end carry exist discard it)

1 1
3 4 7
+ 7 3 5

1 0 8 2

The left most bit of the result is 1, called carry and it is ignored.
So answer is 082

b)

AND Gate

The AND digital logic gate with ‘n’ i/ps one o/p, which performs logical conjunction based on
the combinations of its inputs. The output of this gate is true only when all the inputs are true.
When one or more inputs of the AND gate’s i/ps are false, then only the output of the AND
gate is false. The symbol and truth table of an AND gate with two inputs is shown below

OR Gate

The OR gate is a digital logic gate with ‘n’ i/ps and one o/p, that performs logical conjunction
based on the combinations of its inputs. The output of the OR gate is true only when one or
more inputs are true. If all the i/ps of the gate are false, then only the output of the OR gate
is false. The symbol and truth table of an OR gate with two inputs is shown below.
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NOT Gate

The NOT gate is a digital logic gate with one input and one output that operates an inverter
operation of the input. The output of the NOT gate is the reverse of the input. When the input
of the NOT gate is true then the output will be false and vice versa. The symbol and truth table
of a NOT gate with one input is shown below. By using this gate, we can implement NOR and
NAND gates

NAND Gate

The NAND gate is a digital logic gate with ‘n’ i/ps and one o/p, that performs the operation of
the AND gate followed by the operation of the NOT gate .NAND gate is designed by combining
the AND and NOT gates. If the input of the NAND gate high, then the output of the gate will
be low.The symbol and truth table of the NAND gate with two inputs is shown below.
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NOR Gate

The NOR gate is a digital logic gate with n inputs and one output, that performs the operation
of the OR gate followed by the NOT gate. NOR gate is designed by combining the OR and NOT
gate. When any one of the i/ps of the NOR gate is true, then the output of the NOR gate will
be false. The symbol and truth table of the NOR gate with the truth table is shown below.

Exclusive-OR Gate

The Exclusive-OR gate is a digital logic gate with two inputs and one output. The short form
of this gate is Ex-OR. It performs based on the operation of the OR gate. . If any one of the
inputs of this gate is high, then the output of the EX-OR gate will be high. The symbol and
truth table of the EX-OR are shown below.
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Exclusive-NOR Gate
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The Exclusive-NOR gate is a digital logic gate with two inputs and one output. The short form
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of this gate is Ex-NOR. It performs based on the operation of the NOR gate. When both the
inputs of this gate are high, then the output of the EX-NOR gate will be high. But, if any one
of the inputs is high (but not both), then the output will be low. The symbol and truth table
of the EX-NOR are shown below.

6 a) perform following binary numbers using 2’scomplement

i) 39-22 ii)-47+22

i) M=39
N=22

2 39
2 19 1 ↑
2 9 1 ↑
2 4 1 ↑
2 2 0 ↑
2 1 0 ↑
0 1 ↑

∴ (39)10=(100111)2

2 22
2 11 0 ↑
2 5 1 ↑
2 2 1 ↑
2 1 0 ↑
0 1 ↑
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∴ (22)10=(10110)
M=100111

N=010110
Note : 2's complement of a number is 1 added to it's 1's complement number.

Step-1: 1's complement of 010110 is obtained by subtracting each digit from 1

1 1 1 1 1 1
- 0 1 0 1 1 0

1 0 1 0 0 1

Step-2: Now add 1 to the 1's complement to obtain the 2's complement :
101001 + 1 = 101010

Step-3: Now Add this 2's complement of B to A

1 1 1 1
1 0 0 1 1 1
+ 1 0 1 0 1 0

1 0 1 0 0 0 1

The left most bit of the result is 1, called carry and it is ignored.
So answer is 010001 ie (17)

ii)M=22

N=47

(47)10=(_______)2

2 47
2 23 1 ↑
2 11 1 ↑
2 5 1 ↑
2 2 1 ↑
2 1 0 ↑
0 1 ↑
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∴ (47)10=(101111)2
(22)10=(_______)2

2 22
2 11 0 ↑
2 5 1 ↑
2 2 1 ↑
2 1 0 ↑
0 1 ↑

∴ (22)10=(10110)2
∴ M=10110
N=101111

Find Subtraction of 10110 and 101111 using 2's complement

Solution:
2's complement subtraction steps :
Here M = 010110, N = 101111.
Find M- N = ? using 2's complement
First find 2's complement of N = 101111

Note : 2's complement of a number is 1 added to it's 1's complement number.

Step-1: 1's complement of 101111 is obtained by subtracting each digit from 1

1 1 1 1 1 1
- 1 0 1 1 1 1

0 1 0 0 0 0

Step-2: Now add 1 to the 1's complement to obtain the 2's complement :
010000 + 1 = 010001

Step-3: Now Add this 2's complement of B to A

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+ 0 1 0 0 0 1

1 0 0 1 1 1

Hints : (Move mouse over the steps for detail calculation highlight)

Here there is no carry, answer is - (2's complement of the sum obtained 100111)

Note : 2's complement of a number is 1 added to it's 1's complement number.

Step-1: 1's complement of 100111 is obtained by subtracting each digit from 1

1 1 1 1 1 1
- 1 0 0 1 1 1

0 1 1 0 0 0

Step-2: Now add 1 to the 1's complement to obtain the 2's complement :
011000 + 1 = 011001
So answer is -011001 ie -(25)
7) Simplify the following Boolean expression
a) ((AB’+ABC)’+A(B+AB’))’

b) AB+A’C+AB’C(AB+C)
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8.a) perform (-50)-(-10) in binary using the signed-2’s complement method

b) perform 121-52 in binary using 1’s complement method
a)
To perform the subtraction (−50)−(−10) using the signed 2's complement method, we need to
represent -50 and -10 in binary using 8-bit signed 2's complement notation and then perform the
subtraction.

Let's represent -50 and -10 in binary using 8-bit signed 2's complement notation:

-50:

50 in binary is 00110010.

To represent -50 in 2's complement, we flip the bits and add 1.

Flipping the bits of 00110010, we get 11001101.

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Adding 1, we get 11001110.
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So, -50 in 8-bit signed by AICTE|
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is 11001110.
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-10:

10 in binary is 00001010.

To represent -10 in 2's complement, we flip the bits and add 1.

Flipping the bits of 00001010, we get 11110101.

Adding 1, we get 11110110.

So, -10 in 8-bit signed 2's complement notation is 11110110.

Now, let's perform the subtraction (−50)−(−10)(−50)−(−10):

-50: 11001110

-(-10): 11110110 (Subtracting -10 is equivalent to adding its 2's complement)

Performing the subtraction:

11001110 (-50)
- 11110110 (-(-10))
--------------------------------
01011000 (Result in binary)
Now, the result 01011000 in binary represents 40 in decimal. Therefore, (-50) - (-10) equals 40 in
decimal when using the signed 2's complement method

b) Represent 121 and 52 in binary:

121=01111001

52=00110100

Calculate the 1's complement of 52:

52=00110100

The 1's complement of 52 is obtained by flipping each bit:

1’s complement of 52=11001011

Perform binary addition of 121 and 2’s complement of 52

01111001++11001011

Check for any carry after adding the numbers

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01111001 (121)

+ 11001011 (-52)

-------------------

1 01000100

Since there's a carry in the leftmost bit, we need to add it back to the result:

01000100+1=01000101

Convert the binary result back to decimal:

01000101=69

Therefore, 121−52=69 in decimal using the 1's complement method

9. Express the following functions in sum of min terms & product of maxterms.
a) F(a,b,c,d) = b’d+a’d+bd b)F(x,y,z) = (xy+z) (xz+y)

a) F(a,b,c,d) = b’d+a’d+bd
F(a,b,c,d) = (a+a’)b’d+(b+b’)a’d+(a+a’)bd
F(a,b,c,d)=ab’d+a’b’d+ba’d+b’a’d+abd+a’bd
This is the canonical form of the expression
Canonical sop:( 0 represents complement )

F(a,b,c,d)=ab’d + a’b’d + ba’d + b’a’d + abd + a’bd

(101) (001) (101) (001) (111) (011)

F(a,b,c,d)= m1 + m3 + m5 + m7
F(a,b,c,d)=Σm(1,3,5,7)

Canonical pos:( 1 represents complement)

F(a,b,c,d)=ab’d + a’b’d + ba’d + b’a’d + abd + a’bd

(010) (110) (010) (110) (000) (100)

F(a,b,c,d)= M0 +M2+M4+M6
F(a,b,c,d)= ΣM(0,2,4,6)
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b)F(a,b,c,d)=(XY+Z)(XZ+Y)

F(a,b,c,d)=XY+ZX+ZY
Cannonical form:
F(a,b,c,d)=XY(Z+Z’)+X(Y+Y’)Z+(X+X’)YZ
F(a,b,c,d)=XYZ + XYZ’ + XYZ + XY’Z + XYZ + X’YZ

Cannonical SOP form:

F(a,b,c,d)=XYZ + XYZ’ + XYZ + XY’Z + XYZ + X’YZ
(111) (110) (111) (101) (111) (011)
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F(a,b,c,d)=m3+m5+m6+m7
F(a,b,c,d)=Σm(3,5,6,7)

Cannonical POS form:

F(a,b,c,d)=XYZ + XYZ’ + XYZ + XY’Z + XYZ + X’YZ
(000) (001) (000) (010) (000) (100)
F(a,b,c,d)=M0+M1+M2+m4
F(a,b,c,d)=ΣM(0,1,2,4)
10. Convert the following decimal numbers to the indicated bases.
i) (7562.45)10 to Octal ii) (1938.257)10 to hexadecimal iii) (175.175)8 to binary
iv)(163.789)16 to Octal number v)(11001101.0101)2to hexadecimal

i) (7562.45)10 = ( ? )8

Solution:

(7562.45)10=(_______)8

8 7562
8 945 2 ↑
8 118 1 ↑
8 14 6 ↑
8 1 6 ↑
0 1 ↑

0.45 × 8 = 3.60  3 ↓
0.60 × 8 = 4.80  4 ↓
0.80 × 8 = 6.40  6 ↓
0.40 × 8 = 3.20  3 ↓
0.20 × 8 = 1.60  1 ↓
0.60 × 8 = 4.80  4 ↓
∴ (7562.45)10=(16612.346314)8
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ii)

(1938.257)10 = ( ? )16

Solution:

(1938.257)10=(_______)16

16 1938
16 121 2 ↑
16 7 9 ↑
0 7 ↑

0.257 × 16 = 4.112  4 ↓
0.112 × 16 = 1.792  1 ↓
0.792 × 16 = 12.672  C ↓
0.672 × 16 = 10.752  A ↓
0.752 × 16 = 12.32  C ↓
0.32 × 16 = 0.512  0 ↓

∴ (1938.257)10=(792.41CAC0)16

iii) (175.175)8 = ( ? )2

Solution:

(175.175)8=(_______)2

1 7 5 . 1 7 5
001 111 101 . 001 111 101

∴ (175.175)8=(1111101.001111101)
iv)
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(163.789)16 = ( ? )8

Solution:

(163.789)16=(_______)8

First convert hexadecimal to binary

(163.789)16=(_______)2

1 6 3 . 7 8 9
0001 0110 0011 . 0111 1000 1001

∴ (163.789)16=(101100011.011110001001)2

Now convert binary to octal

(101100011.011110001001)2=(_______)8

101 100 011 . 011 110 001 001

5 4 3 . 3 6 1 1

∴ (101100011.011110001001)2=(543.3611)8

∴ (163.789)16=(543.3611)8

V)
(11001101.0101)10=(_______)16

16 11001101
16 687568 D ↑
16 42973 0 ↑
16 2685 D ↑
16 167 D ↑
16 10 7 ↑
0 A ↑
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0.101 × 16 = 0.1616  0 ↓
0.1616 × 16 = 2.5856  2 ↓
0.5856 × 16 = 9.3696  9 ↓
0.3696 × 16 = 5.9136  5 ↓
0.9136 × 16 = 14.6176  E ↓
0.6176 × 16 = 9.8816  9 ↓

∴ (11001101.0101)10=(A7DD0D.0295E9)16
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UNIT-II
COMBINATIONAL CIRCUITS

Short Questions
1. What is Half adder? obtain the sum and carry expression.
x S
HA
y C

No of inputs: 2=> x,y

No of outputs: 2=> S,C
Truth Table:
Input Output
x y S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Kmap for S:

0 1

0 0 1
S=xy’+x’y
1 1 0
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Kmap for C:

0 1

0 0 0
C=xy
1 0 1

2. Draw the 2-bitcomparator circuit using logic gates.

3. Distinguish between encoder and decoder.

ENCODER DECODER
The combinational circuits that The combinational circuits that
modify the binary data into N convert the binary data into 2N
output lines are known as output lines are called Decoders.
Encoders.
In this the output lines are n. In this the output lines are 2n.
The implemented signal is It receives coded binary data as
considered as actual signal input. its input.
It is utilized in videos, E-mail, It is mostly utilized in memory
and more. chips, microprocessors, and more.
When it comes to the Here, the decoder is situated at
communication mode, the the receiving side.
encoder is situated at the
transmitting end.
The operating procedure is quite The operating procedure is complex.
simple here.

4. What is a multiplexer? Give the applications.

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The multiplexer is a combinational logic circuit designed to switch one of several
input lines to a single common output line by the application of a control logic. The
input has a maximum of 2N data inputs (where N = selection or control lines) and
single output line.

Applications of Multiplexer

➤Communication system

➤Telephone network

➤Computer memory

➤Transmission from the computer system of a satellite

5. Design half subtractor and implement using NAND gates.

x D
HS
y B
No of inputs: 2=> x,y

No of outputs: 2=> D,B

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Truth Table:
Input Output
x y D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Kmap for D:

0 1

0 0 1
D=xy’+x’y
1 1 0

Kmap for B:

0 1

0 0 1
B= x’y
1 0 0

6. What is an essential prime implicants, Selective prime implicants, redundant

prime implicants
 Essential Prime Implicants (EPI): are those that always appear in the final
solution.
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-Cover minterms not covered by other prime implicants.
 Selective Prime Implicants (SPI): are those that are neither essential nor
redundant.
-They may or may not appear in the minimal expression.
 Redundant Prime Implicants (RPI):They are covered by essential prime
implicants.
-Excluded from the minimal expression.
7. Explain about False implicants

False Prime Implicants (FPI):


-A false prime implicant is obtained by using the maxterm
representation.
 -An FPI contains at least one 0 (don’t-care condition) that cannot be
covered by any other FPI.
 -If an FPI is essential (i.e., it must make the function equal to 1), it is
called an essential false prime implicant1.
 -In summary, false implicants play a role in optimizing Boolean
functions, especially when considering both 1s and 0s in the expression.
8. Design 3X8 decoder using 2X4 decoder
We know that 2 to 4 Decoder has two inputs, A1 & A0 and four outputs, Y0 to Y3.
Whereas, 3 to 8 Decoder has three inputs A2, A1 & A0 and eight outputs, Y0 to Y7.

We require two 2 to 4 decoders for implementing one 3 to 8 decoder. The block

diagram of 3 to 8 decoder using 2 to 4 decoders is shown in the following figure.

A2 A1 A0 | Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
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-----------------------------------------

9.Explain the design procedure for combinational circuits

The design procedure for combinational logic circuits starts with the problem
specification and comprises the following steps:

-Determine required number of inputs and outputs from the specifications.

-Derive the truth table for each of the outputs based on their relationships to the input.
-Simplify the boolean expression for each output. Use Karnaugh Maps or Boolean
algebra.
-Draw a logic diagram that represents the simplified Boolean expression. Verify the
design by analysing or simulating the circuit.

Long Questions

1 (a)simplify the Boolean expression using K-map method f(A,B,C,D) =

∑m (4,5,7,12,14,15)+∑d(3,8,10).
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00 01 11 10
4-0100 3-0011
00 x 5-0101 8-1000

01 1 1 1 7-0111 10-1010

11 12-1100
1 1 1
P1=BCD
14-1110
10 x x P2=A’BD
15-1111
P3=ABC
Y=BCD+A’BD+ABC

(b)Analyze the design of 8x1 multiplexer using only 2x1 multiplexer

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Truth Table:
Y=S0’S1’S’2D0+ S0’S’1S2D1+ S0’ S1S’2D2+ S0’S1S2D3+
Inputs Op
S0S1’S’2D4+ S0S1’S2D5+ S0S1S’2D6+ S0S1S2D7
S0 S1 S2 Y
0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3
1 0 0 D4
1 0 1 D5
1 1 0 D6
1 1 1 D7
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2 a) Reduce the following function using Quin McCluskey tabular

method. f(A,B,C,D)=∑m(0,2,3,4,5,8,10,11,13,14,15).

I. Binary Representation:

Minterm A B C D
s
0 0 0 0 0

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

8 1 0 0 0

10
1 0 1 0

11
1 0 1 1

13
1 1 0 1

14
1 1 1 0

15
1 1 1 1

II. Group of minterms:

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No of 1’s Minterms Variable

ABCD

0 0 0000

1 2 0010

4 0100
8 1000

2 3 0011

5 0101

10 1010

3 11 1011
13 1101

14 1110

4 15 1111
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III)Pair of Minterms:

Combination ABCD

(0,2) 00_0

(0,4) 0_00

(0,8) _000

(2,3) 001_

(2,10) _010
(4,5) 010_
(8,10) 10_0

(3,11) _011

(5,13) _101

(10,11) 101_

(10,14) 1_10

(11,15) 1_11
(13,15) 11_1

(14,15) 111_

III. Cell Combination:

Combination ABCD

(0,2,8,10) _0_0

(0,8,2,10) _0_0

(2,3,10,11) _01_

(2,10,3,11) _01_

(10,11,14,15) 1_1_

(10,14,11,15) 1_1_

IV. Prime Implicant Chart:

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Prime Minterms

Implicants

0 2 3 4 5 8 10 11 13 14 15

(0,2,8,10) x x x x

(2,3,10,11) x x x x

(10,11,14,15) x x x x

=B’D’+B’C+AC =B’(D’+C)+AC

b) define magnitude comparator? draw the block diagram and truth table of 4 bit
magnitude comparator.
A magnitude comparator is a combinational logic circuit that compares two binary numbers and
determines their relative magnitudes. It determines whether one number is greater than, equal to, or
less than the other number. The result of the comparison is stated by three binary variables that
indicate whether these two numbers are:

 A>B
 A=B
 A<B
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Comparing Output
inputs
A3,B3 A2,B2 A1,B1 A0,B0 A>B A<B A=B
A3>B3 X X X 1 0 0
A3<B3 X X X 0 1 0
A3=B3 A2>B2 X X 1 0 0
A3=B3 A2<B2 X X 0 1 0
A3=B3 A2=B2 A1>B1 X 1 0 0
A3=B3 A2=B2 A1<B1 X 0 1 0
A3=B3 A2=B2 A1=B1 A0>B0 1 0 0
A3=B3 A2=B2 A1=B1 A0<B0 0 1 0
A3=B3 A2=B2 A1=B1 A0=B0 1 0 0
A3=B3 A2=B2 A1=B1 A0=B0 0 1 0
A3=B3 A2=B2 A1=B1 A0=B0 0 0 1

3(b)design 3to 8 decoder using 2to 4 decoder circuits.

 We know that 2 to 4 Decoder has two inputs, A1 & A0 and four outputs, Y0 to
Y3. Whereas, 3 to 8 Decoder has three inputs A2, A1 & A0 and eight outputs,
Y0 to Y7.

 We require two 2 to 4 decoders for implementing one 3 to 8 decoder.

The block diagram of 3 to 8 decoder using 2 to 4 decoders is shown in the
following figure.

A2 A1 A0 | Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
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Truth Table:
Input Output
A2 A1 A0 | Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 D0=A’B’C’
0 0 0 | 0 0 0 0 0 0 1
0 0 1 | 0 0 0 0 0 0 0 D1= A’B’C
0 1 0 | 0 0 0 0 0 1 0 D2= A’BC’
0 1 1 | 0 0 0 0 1 0 0
1 0 0 | 0 0 0 1 0 0 0 D3= A’BC
1 0 1 | 0 0 1 0 0 0 0
1 1 0 | 0 1 0 0 0 0 0 D4= AB’C’

1 1 1 | 1 0 0 0 0 0 0 D5= AB’C

D6= ABC’

D7= ABC

4a) what is full subtractor? Draw the block diagram and truth table of full subtractor and
obtain design equation using two half subtractors..
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 A full subtractor is a combinational circuit that performs subtraction of two bits, one is
minuend and other is subtrahend, Where, "x" is the minuend bit, "y" is the
subtrahend bit, "z" is borrow produced at the previous stage. This circuit has
three inputs and two outputs.

 x D
y FS
B
z
 No of inputs: 3=x,y,z

No of outputs: 2=D,B

 Truth Table:
Input Output
x y z D B
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 0 1 0 1
1 1 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

 Kmap for D:

00 01 11 10

0 0 1 0 1

1 1 0 1 0 D=xy’z’+x’y’z+xyz+x’yz’

 Kmap for B:

00 01 11 10

0 0 1 1 1

1 0 0 1 0 B=x’z+yz+x’y
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Obtaining full subtractor using 2 half subtractors:

D= xy’z’ + x’y’z + xyz + x’yz’
=z’(xy’ + x’y) + z(xy + x’y’)
=z’(xy’ + x’y) + z(xy’ + x’y)
D=z ⨁ [x ⨁ y]
B=x’z + yz + x’y

= z(x' + y) + x'y

5. a)what is full adder? draw the block diagram and truth table of full adder and obtain
design equation using two half Adders.
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 Full Adder is the adder that adds three inputs and produces two outputs. The first two inputs
are x and y and the third input is an input carry as z. Two output states are sum and carry.

 x S
y FA
C
z
No of inputs: 3=>x,y,z

No of outputs: 2=>S,C

 Truth Table:
Input Output
x y z D B
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 0 1 0 1
1 1 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

 Kmap for S:

00 01 11 10

0 0 1 0 1

1 1 0 1 0 S=xy’z’+x’y’z+xyz+x’yz’

 Kmap for C:

00 01 11 10

0 0 0 1 0

0 1 1 1  C=xz+yz+xy
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(b)What is a priority encoder? Design a 4x2 priority encoder with appropriate gates.
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 It includes priority function that is the operation of priority encoder is such that if 2 or more inputs are
equal to 1 at the same time, the input having highest priority will be preferred.

 D0 Y1
4x2 priority
D1
D2
encoder Y2
D3

Priority: D3>D2>D1>D0

 Truth Table:
Input Output
D0 D1 D2 D3 Y2 Y1 v
0 0 0 0 X X 0
1 0 0 0 0 0 1
X 1 0 0 0 1 1
X X 1 0 1 0 1
X X X 1 1 1 1

Y2=D2D3’+D3=>D2+D3
Y1=D1D2’D3’+D3=>D1+D3
V=D3+D2+D1+D0

6 a) simplify the Boolean expression using K-map method f(A,B,C,D)

=
πM(0,1,4,5,6,8,9,12,13,14).
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00 01 11 10
0-0000
00 0 0 1-0001

01 0 0 0 4-0100

11 5-0101
0 0
6-0110
10 0 0 0
8-1000

9-1001
O1=C, P1=A’BD’,P2=AB’D’
12-1100
Y=C+A’BD’+AB’D’
13-1101

14-1110

b)Simplify the expression using k-map method F=A’+AB+ABD’+AB’D’+C.

F=A’+AB+ABD’+AB’D’+C
=A’(B+B’)(C+C’)(D+D’)+AB(C+C’)(D+D’)+AB(C+C’)D’+(A+A’)
(B+B’)C(D+D’)
=A’B+A’B’(C+C’)(D+D’)+(ABC+ABC’)(D+D’)+ABCD+ABC’D+(AC+A’C(B+B
’)(D+D’))
= (A’BC+A’B’C+ A’BC’+A’B’C’(D+D’))+ABCD+ABC’D+ ABCD’+ABC’D’
+ABCD+ABC’D+ (ABC+A’BC+ AB’C+A’B’C (D+D’))
= A’BCD+A’B’CD+ A’BC’D+A’B’C’D+ A’BCD’+A’B’CD’+
A’BC’D’+A’B’C’D’+ ABCD+ABC’D+ ABCD’+ABC’D’+ ABCD+ABC’D+
ABCD+A’BCD+ AB’CD+A’B’CD+ ABCD’+A’BCD’+ AB’CD’+A’B’CD’
=A’BCD+A’B’CD+A’BC’D+A’B’C’D+A’BCD’+A’B’CD’+A’BC’D’+A’B’C’D’+
ABCD+ABC’D+ABCD’+ABC’D’+AB’CD+AB’CD’
=1000+1100+1010+1110+1001+1101+1011+1111+0000+0010+0001+0011+0100+
0101
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=M8+M12+M10+M14+M9+M13+M11+M15+M0+M2+M1+M3+M4+M5
= πM(0,1,2,3,4,5,8,9,10,11,12,13,14,15)

0-0000
00 01 11 10
1-0001
00 0 0 0 0 2-0010
01 0 0 3-0011

11 4-0100
0 0 0 0
5-0101
10 0 0 0 0
8-1000

9-1001
O1=C,O2=A’,O3=B
10-1010
Y=C+A’+B 11-1011

12-1100

13-1101

14-1110

15-1111

7. Reduce the following function using QuineMccluskey tabular method.

f(A,B,C,D)=∑m(6,7,8,9)+d(10,11,12,13,14,15)

I. Binary Representation:
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Minterm A B C D
s
6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1

II. Group of minterms:

No of 1’s Minterms Variable

ABCD

8 1000
1

2 6 0110

9 1001

10 1010
12 1100

7 0111
3
11 1011

13 1101

14 1110

4 15 1111
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III. Pair of Minterms:

Combination ABCD

(8,9) 100_

(8,10) 10_0

(8,12) 1_00

(6,7) 011_

(6,14) _110

(9,11) 10_1
(9,13) 1_01

(10,14) 1_10

(12,13) 110_

(12,14) 11_0

(3,11) _011
(5,13) _101

(10,11) 101_

(10,14) 1_10

(7,15) _111

(11,15) 1_11

(13,15) 11_1
(14,15) 111_

iv) Cell Combination:

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Combination ABCD

(8,9,10,11) 10__

(8,9,12,13 ) 1_0_

(8,10,12,14) 1__0

(6,7,14,15) _11_

(9,11,13,15) 1__1
(10,11,14,15) 1_1_
(12,13,14,15) 11__

IV. Prime Implicant Chart: ignore don’t cares

Prime Implicants Minterms a,b,c,d

6 7 8 9

(6,7,14,15) X x _11_

(8,9,10,11,12,13,14,15) x x 1___

Extracted essential prime implicants : -11_,1___

All extracted essential prime implicants : _11_,1___

Minimal Quine-McCluskey Expression = bc + a

8. a)Perform the binary Addition by using 8-bit 2’s complement for the following numbers.

i) -75+26

Here A = 0011010, B = 1001011.

Find A - B = ? using 2's complement
First find 2's complement of B = 1001011
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Step-1: 1's complementDepartment
of 1001011 of Computer
is obtained byScience Engineering
subtracting each digit from 1

1 1 1 1 1 1 1

- 1 0 0 1 0 1 1

0 1 1 0 1 0 0

Step-2: Now add 1 to the 1's complement to obtain the 2's complement :
0110100 + 1 = 0110101

Step-3: Now Add this 2's complement of B to A

1 1

0 0 1 1 0 1 0

+ 0 1 1 0 1 0 1

1 0 0 1 1 1 1

Hints : (Move mouse over the steps for detail calculation highlight)

Here there is no carry, answer is - (2's complement of the sum obtained 1001111)

Note : 2's complement of a number is 1 added to it's 1's complement number.

Step-1: 1's complement of 1001111 is obtained by subtracting each digit from 1

1 1 1 1 1 1 1

- 1 0 0 1 1 1 1

0 1 1 0 0 0 0
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Step-2: Now add 1 to the 1's complement to obtain the 2's complement :
0110000 + 1 = 0110001
So answer is -0110001 ie; -49

b ) Simplify the Boolean expression using K-map method

f(A,B,C,D)=πM(1,2,3,6,7,8,9,12,14) and draw the logic diagram.

00 01 11 10
1-0001
00 0 0 0 2-0010

01 0 0 3-0011

6-0110
11 0 0
7-0111
10 0 0
8-1000

9-1001
Q1=A’C, P1=A’B’D, P2=ABD’, P3=AB’C’
12-1100
Y=A’C+A’B’D+ABD’+AB’C’ 14-1110

10.Design and implement a BCD to 7 segment decoder.

 A 6

B 5 No of input: 4
C 4 No of output: 7
3

0
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Input Output
A B C D a b c d e f g
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
0 1 0 0 0 1 1 0 0 1 1
0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 1 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 0 1 1
1 0 1 0 X X X X X X X
1 0 1 1 X X X X X X X
1 1 0 0 X X X X X X X
1 1 0 1 X X X X X X X
1 1 1 0 X X X X X X X
1 1 1 1 X X X X X X X
a=∑m(0,2,3,5,6,7,8,9)+ ∑ d(10,11,12,13,14,15)

b=∑m(0,1,2,3,4,7,8,9)+ ∑ d(10,11,12,13,14,15)

c=∑m(0,1,3,4,5,6,7,8,9)+ ∑ d(10,11,12,13,14,15)

d=∑m(0,2,3,5,6,8,9)+ ∑ d(10,11,12,13,14,15)

e=∑m(0,2,6,8)+ ∑ d(10,11,12,13,14,15)

f=∑m(0,4,5,6,8,9)+ ∑ d(10,11,12,13,14,15)

g=∑m(2,3,4,5,8,9)+ ∑ d(10,11,12,13,14,15)

Kmap for a:

00 01 11 10

00 1 1 1

01 1 1 1

11 x x x x

10 1 1 x x
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̅̅̅̅̅̅̅̅
a=A+BD+C+B’D’=>A+C+𝐵 ⨁D
Kmap for b:

00 01 11 10

00 1 1 1 1

01 1 1

11 X x x x

10 1 1 x x

O1=B’,Q1=C’D’,Q2=CD
̅̅̅̅̅̅̅̅̅
b=B’+C’D’+CD=>B’+(𝐶 ⨁D)
Kmap for c:

00 01 11 10

00 1 1 1

01 1 1 1 1

11 X x x x

10 1 1 x x

O1=C’,O2=D,O3=B
C=C’+D+B
Kmap for d:
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00 01 11 10

00 1 1 1

01 1 1

X x x x
11
1 1 x x

10

O1=A,Q1=CD’,Q2=B’C,Q3=B’D’,P1=BC’D

D=A+B’C+CD’+B’D’+A=>A+CD’+B ⨁(C+D’)
Kmap for e:

00 01 11 10

00 1 1

01 1

11 x X x x

10 1 x x

Q1=CD’,Q2=B’D’
e=CD’+B’D’
Kmap for f:
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00 01 11 10

00 1

01 1 1

11 x X x x

10 1 1 x x

O1=A,Q1=D’B,Q2=BC’,Q3=C’D’
f=A+C’D’+D’B+BC’=>A+C’D’+B(C’+D’)
Kmap for g:

00 01 11 10

00 1 1

01 1 1 1

11 x x x x

10 1 1 x x

O1=A,Q1=B’C,Q2=CD’,Q3=B

g=A+B’C+CD’+B=>A+CD’+(B ⨁C)
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UNIT-3
LAQ:
1a) Distinguish between combinational circuits and sequential circuits.
b) With a neat diagram explain operation of SR flip flop and derive its truth table, excitation table and
characteristic equation.
a)
Combinational Circuits: Sequential Circuits:
Definition: Combinational circuits are Definition: Sequential circuits are digital
digital circuits where the output is solely circuits where the output not only depends
dependent on the current inputs. They do on the current inputs but also on the past
not have memory elements, which means history of inputs and outputs. They
the output at any given time is solely incorporate memory elements like flip-flops
determined by the combination of inputs at or registers to store past states or outputs.
that moment.
Behavior : In combinational circuits, the Behavior: In sequential circuits, the output
output changes immediately in response to depends on both the current input and the
changes in the input. There is no concept of internal state of the circuit. The circuit's
state or past history influencing the output state is updated based on clock signals and
feedback from previous outputs
Components: Combinational circuits are Components: Sequential circuits consist of
composed of basic logic gates such as AND, combinational logic circuits along with
OR, NOT, and other combinational logic memory elements such as flip-flops or
blocks like multiplexers, demultiplexers, latches.
adders, subtractors, etc.
Examples: Adders, subtractors, Examples: Flip-flops, counters, shift
multiplexers, demultiplexers, encoders, registers, memory units, etc., are examples
decoders, etc., are examples of of sequential circuits.
combinational circuits.
Characteristics: Characteristics:

 Output depends only on current  Output depends on current input and

input. internal state.
 No memory elements.  Contains memory elements.
 Output changes immediately with  Output changes based on clock
input changes. signals and feedback.
 Useful for tasks that involve purely  Used in applications requiring
logical operations. memory, timing, and sequencing.
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b) SR Flip Flop | Diagram | Truth Table | Excitation Table

SR Flip Flop-
 SR flip flop is the simplest type of flip flops.
 It stands for Set Reset flip flop.
 It is a clocked flip flop.
Construction of SR Flip Flop-

There are following two methods for constructing a SR flip flop-

1. By using NOR latch

2. By using NAND latch

1. Construction of SR Flip Flop By Using NOR Latch-

This method of constructing SR Flip Flop uses-

 NOR latch
 Two AND gates
Logic Circuit-

The logic circuit for SR Flip Flop constructed using NOR latch is as shown below-
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2. Construction of SR Flip Flop By Using NAND Latch-

This method of constructing SR Flip Flop uses-

 NAND latch
 Two NAND gates
Logic Circuit-

The logic circuit for SR Flip Flop constructed using NAND latch is as shown below-

Logic Symbol-

The logic symbol for SR Flip Flop is as shown below-

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Truth Table-

The truth table for SR Flip Flop is as shown below-

INPUTS OUTPUTS REMARKS

Qn Qn+1
S R States and Conditions
(Present State) (Next State)

0 0 X Qn Hold State condition S = R = 0

0 1 X 0 Reset state condition S = 0 , R = 1

1 0 X 1 Set state condition S = 1 , R = 0

1 1 X Indeterminate Indeterminate state condition S = R = 1

Truth Table
Characteristic Equation-

Draw a k map using the above truth table-

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From here-
Qn+1 = ( SR + SR’ ) ( Qn + Q’n ) + Qn ( S’R’ + SR’ )

Qn+1 = S + QnR’

Excitation Table-

The excitation table of any flip flop is drawn using its truth table.

Qn
Qn+1 S R

0 0 0 X

0 1 1 0

1 0 0 1

1 1 X 0

Excitation Table

2a) Draw the clocked Master-Slave J-K flip-flop configuration and explain how it removes race- around
condition in J-K flip-flops.

Master Slave JK flip flop –

The Master-Slave Flip-Flop is basically a combination of two JK flip-flops connected together in

a series configuration. Out of these, one acts as the “master” and the other as a “slave”. The
output from the master flip flop is connected to the two inputs of the slave flip flop whose output
is fed back to inputs of the master flip flop.
In addition to these two flip-flops, the circuit also includes an inverter. The inverter is connected
to clock pulse in such a way that the inverted clock pulse is given to the slave flip-flop. In other
words if CP=0 for a master flip-flop, then CP=1 for a slave flip-flop and if CP=1 for master flip
flop then it becomes 0 for slave flip flop.
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Working of a master slave flip flop –

When the clock pulse goes to 1, the slave is isolated; J and K inputs may affect the state of the system. The slave
flip-flop is isolated until the CP goes to 0. When the CP goes back to 0, information is passed from the master flip-
flop to the slave and output is obtained.

Firstly the master flip flop is positive level triggered and the slave flip flop is negative level triggered, so the master
responds before the slave.

If J=0 and K=1, the high Q’ output of the master goes to the K input of the slave and the clock forces the slave to
reset, thus the slave copies the master.

If J=1 and K=0, the high Q output of the master goes to the J input of the slave and the Negative transition of the
clock sets the slave, copying the master.
If J=1 and K=1, it toggles on the positive transition of the clock and thus the slave toggles on the negative transition
of the clock.
If J=0 and K=0, the flip flop is disabled and Q remains unchanged.
Race Around Condition

In JK Flip-flop – For J-K flip-flop, if J=K=1, and if clk=1 for a long period of time, then Q output will toggle as long as
CLK is high, which makes the output of the flip-flop unstable or uncertain. This problem is called race around
condition in J-K flip-flop. This problem (Race Around Condition) can be avoided by ensuring that the clock input is at
logic “1” only for a very short time.
2b)What is SR latch? Explain gated SR latch?

An SR latch (Set/Reset) is an asynchronous device: it works independently of control signals and relies only on the
state of the S and R inputs. In the image, we can see that an SR latch can be created with two NOR gates that have a
cross-feedback loop. SR latches can also be made from NAND gates, but the inputs are swapped and negated.
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Gated SR latch

. The gated SR latch is a simple extension of the SR latch which provides an Enable line which must be driven high
before data can be latched. Even though a control line is now required, the SR latch is not synchronous, because the
inputs can change the output if the enable line is held high at length. (Note: If a clock is supplied to the control line,
the gated SR latch becomes known as an SR flip flop because the output changes only when edge-triggered by the
clock.
When the Enable input is low, then the outputs from the AND gates must also be low, thus
the Q and Q outputs remain latched to the previous data. Only when the enable input is high can the state of the
latch change, as shown in the truth table. When the enable line is asserted, a gated SR latch is identical in operation
to an SR latch.
The Enable line is sometimes a clock signal, but is usually a read or write strobe
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0 0 0 Latched

0 0 1 Latched

0 1 0 Latched

0 1 1 Latched

1 0 0 Latched

1 0 1 0 1

1 1 0 1 0

1 1 1 Metastable

B) Flip flop Conversion – SR flip-flop to JK flip-flop

Step 1: Write the truth table of the required flip-flop

Here the required flip flop is jk flip flop
Hence you need to write the truth table of JK flip flop which is

J K QN QN+1

0 0 0 0

0 0 1 1
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1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 0

Step 2: Write the excitation table of the given flip-flop

In this case the given flip-flop is SR flip-flop
Therefore you need to write the excitation table of SR flip-flop which is

QN QN+1 S R

0 0 0 X

0 1 1 0

1 0 0 1

1 1 X 0

Step 3: Write the conversion table

The conversion table, which is a combination of truth table and excitation table, to implement a JK flip-flop from SR
flip-flop is as follows
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K ofQN
ComputerQN+1
Science Engineering
S R

0 0 0 0 0 X

0 0 1 1 X 0

0 1 0 0 0 X

0 1 1 0 0 1

1 0 0 1 1 0

1 0 1 1 X 0

1 1 0 1 1 0

1 1 1 0 0 1

Step 4: Find the Boolean expressions for the inputs of the given flip-flop.
In this case the given flip-flop is SR.

therefore, write the Boolean expressions for S and R from the conversion table using K-Maps. K-Map for S:
Expression for S would be S = JQN/
K-Map for R:
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Expression for R would be R = KQN

Step 5: Draw the circuit for implementing JK flip-flop using SR flip-flop

4 a) with a neat diagram explain operation of JK flip flop and derive its truth table , excitation table and
characteristic equation.
b)Convert a D flipflop into T flipflop using Standard Procedure
ANS:-
JK Flip Flop- JK flip flop is a refined & improved version of SR Flip Flop that has been introduced to solve the
problem of indeterminate state that occurs in SR flip flop when both the inputs are 1.
In JK flip flop,
Input J behaves like input S of SR flip flop which was meant to set the flip flop.
Input K behaves like input R of SR flip flop which was meant to reset the flip flop.
Construction of JK Flip Flop-
1. Construction of JK Flip Flop By Using SR Flip Flop Constructed From NOR Latch-
this method of constructing JK Flip Flop uses-
SR Flip Flop constructed from NOR latch
Two other connections
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The logic circuit for JK Flip Flop of Computer
constructed Science
using SR Flip Engineeringfrom NOR latch is as shown below-
Flop constructed

Logic Symbol-
The logic symbol for JK Flip Flop is as shown below-

Truth Table-
The truth table for JK Flip Flop is as shown below-
Truth Table
The above truth table may be reduced as-
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INPUTS OUTPUTS REMARKS

Qn (Present State) Qn+1 States and Conditions

J K
(Next State)

0 0 X Qn Hold State condition J = K = 0

0 1 X 0 Reset state condition J = 0 , K = 1

1 0 X 1 Set state condition J = 1 , K = 0

1 1 X Q’n Toggle state condition J = K = 1

Characteristic Equation-
Draw a k map using the above truth table-

From here-
Qn+1 = Q’n (JK + JK’) + Qn (J’K’ + JK’)
Excitation Table-

Qn+1 = Q’nJ + QnK’

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The excitation table of any flip flop is drawn using its truth table.

Qn Qn+1 S R

0 1 1 X

1 0 X 1

1 1 X 0

Excitation Table
b)Convert a D flip flop into T flip flop using Standard Procedure
ANS:- Flip-flop Conversion – D flip-flop to T flip-flop
Step 1: Write the truth table of the required flip-flop
Here the required flip-flop is T flip-flop
Hence you need to write the truth table of T flip-flop which is

T QN QN+1

0 0 0

0 1 1

1 0 1

1 1 0
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In this case the given flip-flop is D flip-flop

Therefore you need to write the excitation table of D flip-flop which is

QN QN+1 D

0 0 0

0 1 1

1 0 0

1 1 1

Step 3: Write the conversion table

The conversion table, which is a combination of truth table and excitation table, to implement a T flip- flop from D
flip-flop is as follows

T QN QN+1 D

0 0 0 0

0 1 1 1

1 0 1 1

1 1 0 0

Step 4: Find the Boolean expressions for the inputs of the given flip-flop
In this case the given flip-flop is D.
Therefore, write the Boolean expression for D from the conversion table using K-Map. K-Map for D:
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D = T/QN + TQ / N

Step 5: Draw the circuit for implementing T flip-flop from D flip-flop

For this, connect the input D of the given flip-flop (D flip-flop) to the circuit made for the expression of D obtained
from the K Map. Therefore, the circuit would be:

5a) obtain excitation table of

SR Flip flop
JK flip flop
D flip flop
T flip flop
ANS:-
The excitation table for each flip-flop.
SR flip flop

The excitation table of the SR flip-flop can be constructed from the information available in the truth table. In the
diagram shown below, the first table shows the truth table, from which the excitation table is derived.

From the truth table, you can observe that when the present state is Qn = 0, the next state becomes Qn+1 = 0 for
two input values S = 0, R = 0 and S = 0, R = 1. (It is shown in the first and third rows with yellow color)
From this we can say that, for the state transition from Qn = 0 to Qn+1 = 0, the excitation inputs required are S = 0
and R = 0 or 1. It is filled in the first row(Yellow color) of the excitation table. Since R has two values(0 and 1), it is
denoted as a don’t care condition(x).
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Similarly, when you observe the truth table, to obtain the next state output Qn+1 = 1 from the present state input
Qn = 0, the required SR inputs are S = 1 and R = 0(shown in the 5th row as pink color).

Thus for state transition from 0 to 1, the excitation inputs require are S = 1 and R = 0. It is filled in the second row of
the excitation table.

The state transition from the present state Qn = 1 to the next state Qn+1 = 0 happens only when the inputs are S =
0 and R = 1(observed from the 4th row in light green color). It is filled in the third row of the excitation table.
In the same way, the state transition from Qn = 1 to Qn+1 = 1 happens at S = 0, R = 0 and S = 1, R
= 0(shown in second and sixth row of the truth table).

It is filled in the fourth row of the excitation table as Qn = 1, Qn+1 = 1 and S = x, R = 0. Here x denotes the don’t care
condition, as it has two values(0 and 1).
***JK flip flop
For the JK flip flop, the excitation table is derived in the same way. From the truth table, for the present state and
next state values Qn = 0 and Qn+1 = 0(indicated in the first and third row with yellow color), the inputs are J = 0 and
K = 0 or 1.
Since K input has two values, it is considered as a don’t care condition(x).
Thus the state transition from Qn = 0 to Qn+1 = 0 takes place when J = 0, K = x. It is filled in the first row of the
excitation table.

The state transition from present state Qn = 0 to the next state Qn+1 = 1 occur, when the inputs are either J = 1, K =
0 or J = 1, K = 1(indicated in the fifth and seventh row with pink color). Thus the excitation table is filled with datas
Qn = 0, Qn+1 = 1, J = 1 and K = x.
Similarly, for the transition of the state from 1 to 0, the inputs are J = 0, K = 1 or J = 1, K = 1(indicated in the fourth
and eighth row with ash color). So for this transition, the required inputs are J = x and K =1, as the value of J can be
either 0 or 1.
For the state transition from Qn = 1 to Qn+1 = 1, the J input can be 0 or 1 but the K input remains at o(indicated in
the second and sixth row with violet color). For this transition to occur, the excitation inputs are J = x and K = 0.
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D flip flop
The excitation table of the D flip-flop is derived from its truth table. The excitation table is constructed in the same
way as explained for the SR flip-flop.
Here, when you observe from the truth table shown below, the next state output is equal to the D input. So it is
very simple to construct the excitation table.

For the state transition from Qn = 0 to Qn+1 = 0, the required excitation input is D = 0, regardless of Qn value. For
transition of states from Qn = 0 to Qn+1 = 1, the input required to excite is D = 1.
The state transit from Qn = 1 to Qn+1 = 0 for the input D = 0. For the input D = 1, the state transition takes place
from Qn = 1 to Qn+1 = 1.
All the above-mentioned state transitions for D flip flop from the present state(Qn) to the next state(Qn+1) for the
corresponding excitation inputs are filled in the table to get the excitation table.
T flip flop
The following figure shows the truth table of the T flip flop, from which the excitation table is derived.
From the truth table, we can observe that, when the T input is 0, there is no change in the state. So for the state
transition from the present state to the next state, i.e., from Qn = 0 to Qn+1 = 0 and from Qn = 1 to Qn+1 = 1, the
excitation input require is T = 0. It is filled in the first and the fourth row in the excitation table.
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Similarly, from the truth table, we can also observe, when T = 1, the state of the flip flop toggles or is
complimented. Thus, for the transition of the state from either 0 to 1 or from 1 to 0, the excitation input is T = 1. It
is filled in the second and third rows of the excitation table.
b) Convert a JK flip flop into D flip flop using standard procedure
Conversion of J-K Flip-Flop into D Flip-Flop
JK Flip-Flop:
JK Flip-Flip is basically a gated SR flip-flop which has an additional input that is clock input. It prevents the invalid
output that may be obtained when both the inputs are 1.
D Flip-Flop:
D Flip-Flop is a modified SR flip-flop which has an additional inverter. It prevents the inputs from becoming the
same value.
Conversion of J-K Flip-Flop into D Flip-Flop:
Step-1:
We construct the characteristic table of D flip-flop and excitation table of JK flip-flop.

Step-2:
Using the K-map we find the boolean expression of J and K in terms of D.
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J=D
K = D'
Step-3:
We construct the circuit diagram of the conversion of JK flip-flop into D flip-flop.
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SAQ
1)Write a short notes on sequential circuit.
A sequential circuit refers to a special type of circuit. It consists of a series of various inputs
and outputs. Here, the outputs depend on a combination of both the present inputs as well
as the previous outputs. This previous output gets treated in the form of the present state.
The sequential circuits can be event driven, clock driven and pulse driven.
2)Difference between latch and flip flop.

Flip-flop Latch
Flip-flop is a bistable device i.e., it Latch is also a bistable device whose states are
has represented
two stable states that are As 0 and 1
represented as 0
two stable states that are states are also represented as 0 and 1. and 1.
represented as 0
*It is a edge triggered device. It is a level triggered device.
*Gates like NOR, NOT, AND, NAND These are also made up of gates.
are building blocks of flip flops.
*They are classified into There is no such classification in latches.
asynchronous
or synchronous flipflops.
.*A Flip-flop always have a clock Latches doesn’t have a clock signal
signal

*Flip-flop can be build from Latches |*Latches can be build from gates
*ex:D Flip-flop, JK Flip-flop |*ex:SR Latch, D Latch
3.) Draw the excitation table of JK flip flop.

4.) Draw the logic diagram of SR flip flop using NAND gates.
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5.) Define race around condition?
Race Around Condition in JK Flip-flop
For J-K flip-flop, if J=K=1, and if clk=1 for a long period of time, then output Q will toggle as
long as CLK remains high which makes the output unstable or uncertain.
This is called a race around condition in J-K flip-flop.
We can overcome this problem by making the clock =1 for very less duration.
The circuit used to overcome race around conditions is called the Master Slave JK flip flop.

6.) List out the applications of filp flop.

 Flip-flops are used to build memory elements in digital systems, such as registers and
memory cells
 Flip-flops are widely used in clocking systems to synchronize the timing of various
components in digital circuits.
 Flip-flops are essential components in counter circuits. They are used to count clock
pulses and produce output signals based on the count value.
 Flip-flops are used for data synchronization in digital communication systems and
interface circuits.

7.) write the characterstic equation for JK flip flop

For a JK flip-flop, the characteristic equation can be written as follows:
Qn+1=J⋅Q’+K’⋅Qn
Where:
Qn+1 is the next state of the flip-flop.
Qn is the current state of the flip-flop.
J and K are the inputs of the JK flip-flop.
‾Q represents the complement of the current state Q.
‾K represents the complement of the input K

8.) Explain about SR latch.

An SR latch, also known as a Set-Reset latch or a Flip-Flop, is a basic memory element in
digital electronics. It's constructed using two cross-coupled NOR gates or NAND gates. The
SR latch has two inputs: Set (S) and Reset (R), and two outputs: Q and Q'.
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9.) Draw the excitation table of SR flip flop.

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UNIT-4:
SAQ:
1. What is the role of MAR and MDR?
The Memory Address Register (MAR) and Memory Data Register (MDR) are two important
registers in a computer system. Here's their role:
Memory Address Register (MAR): The MAR holds the memory address from which data will
be fetched or to which data will be sent and stored via the system bus. It is used to access
data and instructions from memory during the execution phase of an instruction.
Memory Data Register (MDR): The MDR holds the actual data that is being transferred to or
from the addressed memory location. When reading from memory, the data addressed by
the MAR is fed into the MDR and then used by the CPU. When writing to memory, the CPU
writes data from the MDR to the memory location specified by the MAR

2. What is DMA and why it is used?

DMA is a method that enables an I/O device to send or receive data directly to or from the
main memory without involving the CPU. It is managed by a DMA controller
Use: DMA is used to improve overall computer performance by reducing the CPU's
involvement in data transfer operation

3. Write short notes on indirect addressing mode?

In indirect addressing mode, the address field of an instruction contains the memory
location or register that holds the effective address of the operand. Instead of directly
specifying the operand's address, the instruction points to the location where the address is
stored
Working: When an instruction with indirect addressing mode is executed, the CPU retrieves
the effective address from the specified memory location or register. It then uses this
effective address to access the operand in memory or perform the required operation.

4. What is the function of accumulator and program counter?

Accumulator: The accumulator is a special-purpose register in a CPU that is used for

temporary storage of data during arithmetic and logical operations.
Program Counter: The program counter, also known as the instruction pointer or instruction
address register, is a register that stores the memory address of the next instruction to be
fetched and executed by the CPU

5. List out various phases of instruction cycle?

The specific phases may vary depending on the architecture, but here are the commonly
recognized phases:
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1)Fetch, 2) Decode,3) execute 4) Memory Access .5) Registry Write-Back

LAQ:
1. (a) with a neat sketch Explain the various functional blocks of computer and the
way they communicate with each other.
(b)Explain Various Types of Computer Registers.

Functional Blocks of a Computer and their Communication

A computer system consists of several functional blocks that work together to process data
and produce output. These functional blocks include the input unit, central processing unit
(CPU), memory unit, output unit, and interconnection buses. Let's explore each of these
blocks and how they communicate with each other.
Input Unit:

The input unit is responsible for receiving data and instructions from external sources and
converting them into a form that the computer can understand. It comprises devices such as
a keyboard, mouse, scanner, and microphone 1. These devices capture input from users and
transmit it to the CPU for processing. The input unit communicates with the CPU through
the input bus.
Central Processing Unit (CPU):

The CPU is often referred to as the brain of the computer system. It performs all the major
calculations, operations, and comparisons required by the computer. The CPU consists of
three main components: the arithmetic logic unit (ALU), the control unit (CU), and registers.
The ALU performs arithmetic and logical operations, while the control unit coordinates and
controls the activities of other units. The registers store intermediate results temporarily.
The CPU communicates with other units through buses.
Memory Unit:
The memory unit is responsible for storing data and instructions that are currently being
processed by the CPU. It consists of two main types of memory: primary storage (RAM) and
secondary storage (hard disk, solid-state drive, etc.). The primary storage holds data and
instructions that are actively used by the CPU, while the secondary storage provides long-
term storage for data and programs. The memory unit communicates with the CPU through
the memory bus.
Output Unit:
The output unit converts processed data from the CPU into a human-readable form and
presents it to the user. Common output devices include monitors, printers, and speakers.
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The output unit receives data from the CPU through the output bus and converts it into a
format that can be understood by humans.
Interconnection Buses:
The functional blocks of a computer communicate with each other through interconnection
buses. A bus is a transmission path made up of conducting wires that allow data and control
signals to be passed between components. There are three types of buses: the address bus,
the data bus, and the control bus. The address bus carries the address location of data or
instructions, the data bus carries the actual data being transferred, and the control bus
carries control signals for coordinating the activities of different components.
In summary, the functional blocks of a computer, including the input unit, CPU, memory
unit, and output unit, work together to process data and produce output. They
communicate with each other through interconnection buses, which allow the transfer of
data, instructions, and control signals

b) Various types of registers:

Accumulator (AC): The accumulator is a general-purpose register that stores intermediate

results during arithmetic and logical operations .
Data Register (DR): The data register holds the data being processed by the CPU. It is used
for temporary storage of operands and results .
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Address Register (AR): The address register holds the memory address of data or
instructions being accessed by the CPU. It is used for memory addressing purposes .
Program Counter (PC): The program counter register holds the memory address of the next
instruction to be executed. It keeps track of the current position in the program being
executed .

Instruction Register (IR): The instruction register holds the current instruction being
executed by the CPU. It contains the opcode and operands of the instruction .
Temporary Register (TR): The temporary register is used for holding temporary data during
the processing
Input Register (INPR): The INPR receives an 8 bit character from the input device
Output Register (OUTR): The OUTR register holds an 8 bit character from output devices

2.(a)define interrupt? Explain interrupt cycle with flowchart.

(b)Illustrate block diagram of I/O configuration.
a) Interrupt Cycle:
Interrupt cycle is very similar to the instruction cycle. At the very start, the status of flip-
flop R is checked. If it is 0 there is no interrupt and CPU can continue it's ongoing tasks. But
when R=1, it denotes that the ongoing process should halt because an interrupt has
occurred .

When R=0, CPU continues it's tasks checking the status of IEN in parallel. If it is 1, FGI and
FGO are checked in a hierarchy. If any of these flip-flops are found set, R is immediately
set by 1.

When R=1, the content in PC (address of next instruction in memory) is saved at M[0] and
then PC is set by 1 enabling it to point the BUN operation. The instruction at M[1] is a BUN
instruction that leads the control to appropriate I/O ref. Instruction stored at some other
location in the memory. Now separate Fetch, Decode and Execute phases are practised to
entertain the I/O ref. instruction.

Once the I/O ref. instruction is executed completely, PC is loaded with 0 where it finds the
saved RETURN address.
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b) Input-Output Configuration:
The terminal sends and receives serial information.
Each quantity of information has eight bits of an alphanumeric code.
The serial information from the keyboard is shifted into the input register INPR.
The serial information for the printer is stored in the output register OUTR.
These two registers communicate with a communication interface serially and with the AC in
parallel. The input—output configuration is shown in Fig.

 The input register INPR consists of eight bits and holds alphanumeric input information.
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 The 1-bit input flag FGI is a control flip-flop.

 The flag bit is set to 1 when new information is available in the input device and is cleared
to 0 when the information is accepted by the computer.

 The output register OUTR works similarly but the direction of information flow is reversed.
 Initially, the output flag FGO is set to 1.

 The computer checks the flag bit; if it is 1, the information from AC is transferred in
parallel to OUTR and FGO is cleared to 0.

 The output device accepts the coded information, prints the corresponding character, and
when the operation is completed, it sets FGO to 1.

3.) Write short notes on

i) Instruction format
ii) Stored program organization
iii) Strobe control
i) Instruction Format: Instruction format refers to the layout of machine instructions that
can be directly executed by the CPU. It includes components such as addressing mode,
operation code, and operands. There are four main types of instruction formats: Zero
Address, One Address, Two Address, and Three Address Instruction Format. The choice of
instruction format depends on the specific requirements of the computer architecture and
the trade-offs between code size, execution time, and flexibility.
ii) Stored Program Organization: Stored program organization is a concept in computer
architecture that refers to the practice of storing both program instructions and data in the
computer's memory. This concept allows computers to be more flexible and powerful, as it
enables them to execute different tasks by simply changing the instructions stored in
memory. The basic structure of a stored-program computer includes three main units: the
Central Processing Unit (CPU), the Main Memory Unit, and the Input/Output Devices.
Strobe Control: Strobe control is a technique used in asynchronous data transfer to
synchronize the flow of data between two devices. It involves the use of a single control line,
known as a strobe, to time each transfer. There are two types of strobe control methods:
source-initiated strobe and destination-initiated strobe. In both methods, the strobe signal is
used to ensure proper synchronization between the source and destination units, allowing
for the reliable transmission of data without the need for a clock signal

4.a) Explain DMA controller with neat block diagram.

b) Explain handshaking technique in terms of source initiated and destination-initiated data

transfer
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A) A Direct Memory Access (DMA) controller is a specialized hardware device that enables data
transfers between peripherals and memory without involving the CPU. It enhances the overall
efficiency of the system by offloading data transfer tasks from the CPU, allowing it to focus on
executing other instructions
Block Diagram of DMA Controller:

DMA Controller Unit: This unit manages the DMA operations. It includes control logic and
registers necessary for controlling data transfers.
Address Registers: These registers store the starting address in memory where data will be
read from or written to during the transfer.
Count Registers: Count registers determine the number of bytes or words to be transferred
during a DMA operation
Control Registers: Control registers contain various control bits that determine the direction
of data transfer (read or write), the transfer mode (single transfer or block transfer), and
other parameters.
Interrupt Logic: DMA controllers can generate interrupts to signal the CPU when a data
transfer operation is complete or when an error occurs.
Bus Interface: This component enables the DMA controller to communicate with the CPU
and other devices on the system bus.
Operation of DMA Controller:

Initialization: The CPU initializes the DMA controller by setting up the necessary parameters
such as source and destination addresses, transfer size, and transfer mode.
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Arbitration: If multiple devices request access to the bus simultaneously, the arbitration
logic within the DMA controller decides which device gets priority access.
Transfer Execution: Once the DMA controller gains control of the bus, it initiates the data
transfer between the peripheral and memory without involving the CPU.
Interrupt Generation: After completing the data transfer, the DMA controller may generate
an interrupt to inform the CPU of the transfer status.
Completion: Once the data transfer is complete, the DMA controller releases control of the
bus, allowing other devices to access it.
B) Handshaking is a communication protocol used in digital systems to ensure that data
transfers between devices occur smoothly and without errors.
Source-Initiated Data Transfer:
In source-initiated data transfer, the source device takes the initiative to send data to the
destination device

The handshaking process typically involves the following steps:

Request from Source: The source device sends a request signal to the destination device
indicating its readiness to transfer data.

Acknowledgment from Destination: Upon receiving the request signal, the destination
device acknowledges the request by sending an acknowledgment signal back to the source.
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Data Transfer: After receiving acknowledgment, the source begins transmitting the data to
the destination.
Completion Notification: Once the data transfer is complete, the source device notifies the
destination device about the completion of the transfer.
Final Acknowledgment: The destination device acknowledges the completion of the
transfer.
The source-initiated data transfer ensures that data transmission occurs only when both the
source and destination are ready, minimizing the chances of data loss or corruption.
Destination-Initiated Data Transfer:

In destination-initiated data transfer, the destination device initiates the data transfer
process by requesting data from the source device.

WORKING:
The handshaking process typically proceeds as follows:
Request from Destination: The destination device sends a request signal to the source
device, indicating its readiness to receive data.
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Acknowledgment from Source: Upon receiving the request signal, the source device
acknowledges the request by sending an acknowledgment signal back to the destination.
Data Transfer: After receiving acknowledgment, the destination device waits for the source
to initiate the data transfer.
Data Reception: The source begins transmitting the data to the destination.
Completion Notification: Once the data transfer is complete, the destination device notifies
the source device about the completion of the transfer.
Final Acknowledgment: The source device acknowledges the completion of the transfer.
Destination-initiated data transfer allows the destination device to control the data transfer
process, ensuring that data is received only when the destination is ready to process it.
In both source-initiated and destination-initiated data transfer scenarios, handshaking
protocols play a crucial role in establishing communication between devices, coordinating
data transfer, and ensuring the integrity and reliability of the transmitted data.
5.a) Explain basic operational concepts of the computer.
b) Explain common bus structure and various types of computers.

a) The basic operational concepts of a computer system involve the execution of

programs or sequences of instructions stored in computer memory. These instructions
are processed to manipulate data that is already loaded into the computer memory
through input devices.

 The program counter is a critical register in the CPU that keeps track of the execution
of instructions. It points to the memory address of the next instruction to be fetched
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and executed.
 The data transfer between the processor and memory is facilitated by the memory
address register (MAR) and memory data register (MDR). The MAR holds the
address of the memory location to be accessed, and the MDR stores the data that is
transferred between the processor and memory.
 The processor can service devices through two methods: polling routine and interrupt.
In the polling routine, the processor checks each input and output to determine if a
device needs servicing. In the interrupt method, the device sends an interrupt signal to
the processor, allowing it to finish its ongoing tasks or instructions before providing
services to the device.

In summary, the basic operational concepts of a computer involve the execution of

programs, processing of data, and the interaction between the processor, memory, and I/O
devices. These concepts are essential for understanding the fundamental operation of a
computer system.
b) Common Bus Structure:
A computer bus is a communication system that transfers data between components inside
a computer or between computers. It consists of multiple wires (signal lines) carrying
addressing and control information. The bus can be categorized based on its type and
function:

Internal Bus vs. External Bus: An internal bus facilitates communication between internal
components, such as the CPU, memory, and video card, while an external bus connects
external peripherals, such as USB or SCSI devices.
Parallel Bus vs. Serial Bus: A parallel bus transmits multiple bits simultaneously, while a serial
bus transmits data sequentially, one bit at a time.
The common bus structure includes the system bus, which connects the CPU to the main
memory on the motherboard. It is also known as the front-side bus, memory bus, local bus,
or host bus.
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Types of computers:

1) Desktop computers are personal computers designed for use on a desk or

workstation. They are often more powerful than laptops and have a larger display,
making them ideal for tasks such as gaming, graphic design, and other processor-
intensive activities.
2) Portable computers, also known as mobile computers, are designed for easy
transport and use in various locations. They offer flexibility and convenience,
allowing users to work, communicate, and access information while on the go.
3) Workstation computers are high-performance desktop computers designed for
professional use in industries such as engineering, architecture, media production,
data science, and more.
4) Server computers and desktop computers have distinct differences in terms of their
purpose, capabilities, and design
5) Supercomputers are high-performance computers designed to handle complex and
resource-intensive tasks
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UNIT-5:
LAQ:
1. a) Explain three mapping techniques of Cache memory in detail?

b) Explain in detail various types of ROM?

a) Cache Memory: It is a small, fast memory that is inserted between the larger slower main
memory and the processor. It holds the currently active segments of a program and their
data .It is a part of memory system ie; small section of SRAM is added along with the main
memory
Mapping Functions :
There are three main mapping techniques which decides the cache organization:
1. Direct-mapping technique
2. Associative mapping Technique
3. Set associative mapping technique
1. Direct-mapping technique : It is the simplest mapping technique, in which each block
from the main memory has only one possible location in the cache organization. For
example, the block I of the main memory maps on to block i module128 of the cache.
Therefore, whenever one of the main memory blocks 0, 128, 256, ……. Is loaded in the
cache, it is stored in the block 0. Block 1, 129, 257,….. are stored in block 1 of the cache and
so on.

2.Associative Mapping Technique: The figure shows the associative mapping, where in
which main memory block can be placed into any cache block position, in this case, 12 tag
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bits are required to identify a memory block when it is resident in the cache. The tag bits of
an address received from the processor are compared to the tag bits of each block of the
cache, to see if the desired block is present. This is called associative-mapping technique. It
gives the complete freedom in choosing the cache location in which to place the memory
block.

3.Set-Associative Mapping :

It is a combination of the direct and associative-mapping techniques can be used. Blocks of

the cache are grouped into sets and the mapping allows a block of main memoryto reside in
any block of the specific set. In this case memory blocks 0, 64,128……4032 mapped into
cache set 0, and they can occupy either of the two block positions within this set. The cache
might contain the desired block. The tag field of the address must then be associatively
compared to the tags of the two blocks of the set to check if the desired block is present this
two associative search is simple to implement.

b) Types of Read-only Memory (ROM):

1.PROM:-Programmable ROM:
 PROM allows the data to be loaded by the user.
 Program ability is achieved by inserting a fuse at point P in a ROM cell .
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 Before it is programmed, the memory contains all 0‟s
 The user can insert 1s at the required location by burning out t he fuse atthese
locations using high-current pulse.
 This process is irreversible.
Merit:

 It provides flexibility.
 It is faster.
 It is less expensive because they can be programmed directly by the user.
2.EPROM:-Erasable reprogrammable ROM:
 EPROM allows the stored data to be erased and new data to be loaded.
 In an EPROM cell , a connection to ground is always made at P and a special
transistor is used, which has the ability to function either as a normal transistor or as
a disabled transistor that is always turned off.
 This transistor can be programmed to behave as a permanently open switch, by
injecting charge into it that becomes trapped inside.
 Erasure requires dissipating the charges trapped in the transistor of memory cells.
This can be done by exposing the chip to ultra-violet light, so that EPROM chips are
mounted in packages that have transparent windows.
 Merits:
 It provides flexibility during the development phase of digital system.
 It is capable of retaining the stored information for a long time.
 Demerits:
 The chip must be physically removed from the circuit for reprogramming and it’s
entire contents are erased by UV light.
3. Electrically erasable programmable read-only memory (EEPROM)

 Electrically erasable programmable read-only memory (EEPROM) chips that can be

electrically programmed and erased.
 EEPROM chips are too slow to use in many products that make quick changes to the
data stored on the chip.
 Typically EEPROMs are found in electronics devices for storing the small amounts of
nonvolatile data in applications where speed is not the most important
Demerit:
 Erasing EEPROM takes typically quite long.
 The drawback of EEPROM is their speed
Flash Memory:
 In EEPROM, it is possible to read & write the contents of a single cell.
 In Flash device, it is possible to read the contents of a single cell but it is only possible to
write the entire contents of a block.
 Prior to writing, the previous contents of the block are erased. Ex: In MP3 player, the flash
memory stores the data that represents sound.
 Single flash chips cannot provide sufficient storage capacity for embedded system
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application.
 There are 2 methods for implementing larger memory modules consisting of number of
chips. They are,
o Flash Cards
o Flash Drives.
4.Flash Cards:
 One way of constructing larger module is to mount flash chips on a small card.
 Such flash card have standard interface.
 The card is simply plugged into a conveniently accessible slot.
 Its memory size are of 8,32,64MB.
 Eg: A minute of music can be stored in 1MB of memory. Hence 64MB flash cards can store
an hour of music.
Flash Drives:
 Larger flash memory module can be developed by replacing the hard disk drive.
 The flash drives are designed to fully emulate the hard disk.
 The flash drives are solid state electronic devices that have no movable parts.
Merits:
 They have shorter seek and access time which results in faster response.
 They have low power consumption which makes them attractive for battery driven
application.
 They are insensitive to vibration.
Demerits:
 The capacity of flash drive (1GB).
 It leads to higher cost per bit.

2.Explain the following secondary storage devices

i) Magnetic disk

ii) Magnetic tape

iii) Optical disk

1.Magnetic disk:
 Magnetic Disk system consists of one or more disk mounted on a common spindle.

 A thin magnetic film is deposited on each disk, usually on both sides.

 The disks are placed in a rotary drive so that the magnetized surfaces move in close proximity to
read /write heads.

 Each head consists of magnetic yoke & magnetizing coil.

 Digital information can be stored on the magnetic film by applying the current pulse of suitable
polarity to the magnetizing coil.
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 Only changes in the magnetic field under the head can be sensed during the Read
operation
Merits:
 It has a larger capacity for a given physical size. The data intensity is high because the
storage medium is not exposed to contaminating elements.
 The read/write heads of a disk system are movable.
The disk system has 3 parts.
They are,
 Disk Platter (Usually called Disk)
 Disk Drive (spins the disk & moves Read/write heads)
 Disk Controller (controls the operation of the system.)
2.Magnetic tapes:
• In magnetic tape only one side of the ribbon is used for storing data.
• It is sequential memory which contains thin plastic ribbon to store data and coated
by magnetic oxide.
• Data read/write speed is slower because of sequential access.
• It is highly reliable which requires magnetic tape drive writing and reading data.
Advantages :

• These are inexpensive, i.e., low cost memories.

• It provides backup or archival storage.
• It can be used for large files.
Disadvantages :

• Sequential access is the disadvantage, means it does not allow access randomly or
directly.
• It requires caring to store, i.e., vulnerable humidity, dust free, and suitable
environment.
• It stored data cannot be easily updated or modified, i.e., difficult to make updates on
data.
3.Optical Disks
• CD-ROM - read only (books, software releases)

• WORM - write once, read many (archival storage)

• Laser encoding, not magnetic

• 30-50 ms seek times

• 640MB - 17GB storage capacity

• Cheaper than hard disks per MB of storage capacity, but slower

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• portable

• Jukeboxes of optical disks are becoming popular for storing really, really large collections of
data.

3.a) Tabulate comparison between different memories in terms of speed, size

and cost?
b) Draw static RAM cell. Explain its read write operation and write its merits
and demerits?
a)

B) Static RAM cell:

 Two inverters are cross connected to form a batch.
 The batch is connected to two bit lines by transistors T1 and T2.
 These transistors act as switches that can be opened / closed under the control of the
word line.
 When the word line is at ground level, the transistors are turned off and the latch retain its
state
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Read Operation:
In order to read the state of the SRAM cell, the word line is activated to close switches T1
and T2.
 If the cell is in state 1, the signal on bit line b is high and the signal on the bit line bis low.
Thus b and b are complements of each other.
 Sense / write circuit at the end of the bit line monitors the state of b and b’ and set the
output accordingly.
Write Operation:
 The state of the cell is set by placing the appropriate value on bit line b and its
complement on b and then activating the word line. This forces the cell into the
corresponding state.
 The required signal on the bit lines are generated by Sense / Write circuit.

Transistor pairs (T3, T5) and (T4, T6) form the inverters in the latch.
 In state 1, the voltage at point X is high by having T5, T6 on and T4, T5 are OFF.
 Thus T1 and T2 returned ON (Closed), bit line b and b will have high and low signals
respectively.
 The CMOS requires 5V (in older version) or 3.3.V (in new version) of power supply voltage.
 The continuous power is needed for the cell to retain its state
Merit :
 It has low power consumption because the current flows in the cell only when the cell is
being activated accessed.
 Static RAM’s can be accessed quickly. It access time is few Nano seconds.
Demerit:
 SRAM’ s are said to be volatile memories because their contents are lost when the power
is interrupted.

4.a) illustrate virtual memory address translation with the help of neat
diagram
b) Explain memory management techniques in detail?
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a) Virtual Memory Address Translation :

 The Page table information is used by MMU for every read & write access.
The Page table is placed in the main memory but a copy of the small portion of the page
table is located within MMU.
 This small portion or small cache is called Translation Look Aside Buffer (TLB).
 This portion consists of the page table entries that corresponds to the most recently
accessed pages and also contains the virtual address of the entry.
 When the operating system changes the contents of page table , the control bit in TLB will
invalidate the corresponding entry in the TLB. Given a virtual address, the MMU looks in TLB
for the referenced page.
 If the page table entry for this page is found in TLB, the physical address is obtained
immediately. If there is a miss in TLB, then the required entry is obtained from the page
table in the main memory & TLB is updated.
 When a program generates an access request to a page that is not in the main memory,
then Page Fault will occur.
 The whole page must be brought from disk into memory before an access can proceed.
When it detects a page fault, the MMU asks the operating system to generate an interrupt.
 The operating System suspend the execution of the task that caused the page fault and
begin execution of another task whose pages are in main memory because the long delay
occurs while page transfer takes place.
 When the task resumes , either the interrupted instruction must continue from the point
of interruption or the instruction must be restarted.
 If a new page is brought from the disk when the main memory is full ,it must replace one
of the resident pages .In that case ,it uses LRU algorithm which removes the least
referenced Page.
 A modified page has to be written back to the disk before it is removed from the main
memory. In that case , write – through protocol is used.
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Approved by AICTE| Affiliated to Osmania University| Estd.2003.
Department of Computer Science Engineering
b) Segmentation:
An implementation to map two-dimensional user-defined addresses into one-dimensional
physical addresses. This mapping is effected by a segment table. Each entry in the segment
table has a segment base and a segment limit. The segment base contains the starting physical
address where the segment resides in memory, and the segment limit specifies the length of
the segment.

Paging:
Segmentation permits the physical address space of a process to be noncontiguous. Paging is
another memory-management scheme that offers this advantage. However, paging avoids
external fragmentation and the need for compaction, whereas segmentation does not. It also
solves the considerable problem of fitting memory chunks of varying sizes onto the backing
store.

Swapping :
A process must be in memory to be executed. A process, however, can be swapped
temporarily out of memory to a backing store and then brought back into memory for
continued execution . Swapping makes it possible for the total physical address space of all
processes to exceed the real physical memory o

Compaction:
One solution to the problem of external fragmentation is compaction. The goal is to shuffle
the memory contents so as to place all free memory together in one large block. Compaction
is not always possible, however. If relocation is static and is done at assembly or load time,
 LORDS INSTITUTE OF ENGINEERING & TECHNOLOGY
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Approved by AICTE| Affiliated to Osmania University| Estd.2003.
Department of Computer Science Engineering
compaction cannot be done. It is possible only if relocation is dynamic and is done at
execution time.

5.a) Draw and explain block diagram of synchronous DRAM a long with its timing diagram?
b) Write short notes on cache memory and its uses?
a) Synchronous DRAM:
 Here the operations are directly synchronized with clock signal.
 The address and data connections are buffered by means of registers.
 The output of each sense amplifier is connected to a latch.
 A Read operation causes the contents of all cells in the selected row to be loaded in these
latches.
Fig: Synchronous DRAM

Timing diagram:
 LORDS INSTITUTE OF ENGINEERING & TECHNOLOGY
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 First, the row address is latched under control of RAS signal.
 The memory typically takes 2 or 3 clock cycles to activate the selected row.
 Then the column address is latched under the control of CAS signal.
 After a delay of one clock cycle, the first set of data bits is placed on the data lines.
 The SDRAM automatically increments the column address to access the next 3 sets of bits
in the selected row, which are placed on the data lines in the next 3 clock cycles
b) Cache Memory:

The DRAMs which form the main memory are slower devices. So it is necessary to insert
wait states in memory read/write cycles. This reduces the speed of execution. The solution
for this problem is in the memory system small section of SRAM is added along with the
main memory, referred to as cache memory. The program which is to be executed is loaded
in the main memory, but the part of the program and data accessed from the cache
memory. The cache controller looks after this swapping between main memory and cache
memory with the help of DMA controller, Such cache memory is called secondary cache.
Recent processors have the built in cache memory called primary cache.
Use of cache memory:
 The Cache memory stores a reasonable number of blocks at a given time but this number
is small compared to the total number of blocks available in Main Memory.
 The correspondence between main memory block and the block in cache memory is
specified by a mapping function.
 The Cache control hardware decide that which block should be removed to create space
for the new block that contains the referenced word.
 The collection of rule for making this decision is called the replacement algorithm.
 The cache control circuit determines whether the requested word currently exists in the
cache.
 If it exists, then Read/Write operation will take place on appropriate cache location . In
this case Read/Write hit will occur.
SAQ:
1) Explain cache hit and cache miss?
During any particular memory cycle, the cache checks the memory address being
issued by the processor. If this address matches the address of one of the few
memory locations held in the cache, the cache handles the memory cycle very
quickly; this is called a cache hit. If the address does not, then the memory cycle
must be satisfied far more slowly by the main memory; this is called a cache miss.
 LORDS INSTITUTE OF ENGINEERING & TECHNOLOGY
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Approved by AICTE| Affiliated to Osmania University| Estd.2003.
Department of Computer Science Engineering
2.) Draw the memory hierarchy?

3.) Define latency and bandwidth?

A good indication of performance is given by two parameters.
They are,
 Latency
 Bandwidth
Latency:
 It refers to the amount of time it takes to transfer a word of data to or from the
memory.
 For a transfer of single word, the latency provides the complete indication of
memory performance.
 For a block transfer, the latency denotes the time it takes to transfer the first word
of data.
Bandwidth:
 It is defined as the number of bits or bytes that can be transferred in one second.
 Bandwidth mainly depends upon the speed of access to the stored data & on the
number of bits that can be accessed in parallel.
4.) Draw the block diagram of associative memory?
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Approved by AICTE| Affiliated to Osmania University| Estd.2003.
Department of Computer Science Engineering
5.) Write short notes on auxiliary memory?
Secondary memory is also known as External memory or Auxiliary memory. Examples: RAM,
ROM, Cache memory, PROM, EPROM, Registers, etc.

6.) Difference between RAM and ROM.

Data Retention: RAM is volatile memory that can store data as long as power is supplied, while ROM
is non-volatile memory that can retain data even when the power is turned off .

Read/Write Operations: RAM supports both read and write operations, allowing data to be both
read from and written to it. On the other hand, ROM only supports read operations, meaning data
can only be read from it

Use: RAM is used to store the data that needs to be currently processed by the CPU temporarily. It is
typically used as CPU cache and primary memory. ROM, on the other hand, is used to store firmware
or microcode used to initialize and control hardware components of the computer

Speed: RAM generally has higher speed compared to ROM. This means that data can be accessed
and processed faster in RAM than in ROM.