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Unit 2

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33 views7 pages

Unit 2

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sikesag308
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Unit-2

CPU Organization and Instruction Set Architecture (ISA)


The CPU organization defines how the CPU is structured to execute instructions. The
Instruction Set Architecture (ISA) is a key component of this organization, as it defines the
set of operations that the CPU can execute, the data types it can manipulate, and the registers
used for operations. The ISA serves as the interface between hardware and software.

1. Instruction Set Architecture (ISA) of a CPU

The ISA is the set of instructions a CPU understands and executes. It specifies:

Operations (e.g., arithmetic, data transfer, control flow)


Operand types (integer, floating-point, etc.)
Addressing modes (how the CPU fetches operands)
Instruction formats (how instructions are encoded)

The ISA acts as the bridge between machine hardware and the software that runs on it.

Interpretation of Instructions
Each instruction in the ISA consists of an opcode (operation code), which tells the CPU what
operation to perform, and operands, which specify the data to be used in the operation.

The CPU interprets instructions in a cycle that consists of the following steps:

1. Fetch: The CPU retrieves the instruction from memory.


2. Decode: The instruction is decoded to understand the operation and operands.
3. Execute: The operation is performed on the operands.
4. Write-back: The result of the operation is written back to memory or a register.

Instruction Set-Based Classification of Processors


There are two primary types of processors based on the ISA:
1. RISC (Reduced Instruction Set Computer)

Key Features:
Simple, fixed-length instructions.
Limited instruction set with a focus on frequently used operations.
Most instructions execute in a single clock cycle.
Emphasis on optimizing instruction pipelines.
Advantages:
Simplified hardware and faster execution for each instruction.
Easier to implement efficient pipelining due to the uniform instruction size.
Disadvantages:
Programs may be longer because more instructions are needed to perform complex
operations.

2. CISC (Complex Instruction Set Computer)

Key Features:
Larger, more complex instruction set, with variable-length instructions.
Instructions can execute complex tasks in a single instruction.
Many instructions take multiple clock cycles.
Advantages:
Shorter programs, as complex instructions perform more tasks.
Can directly execute high-level language constructs.
Disadvantages:
More complex hardware and control unit.
Harder to implement efficient pipelining due to variable instruction length.

Comparison: RISC vs. CISC

Feature RISC CISC


Instruction Complexity Simple and limited Complex and rich
Instruction Length Fixed Variable
Clock Cycles per Instruction 1 (most) Multiple (depends on instruction)
Pipelines Easier to pipeline Harder to implement pipelining
Program Length Longer Shorter
Examples ARM, MIPS Intel x86, Motorola 68000
CPU Architecture Types
CPU architecture defines how instructions interact with the CPU’s internal components. The
main types include:

1. Accumulator-Based Architecture

Instructions operate on an accumulator register.


The result of all operations is stored in the accumulator.
Advantage: Simple hardware design.
Disadvantage: Limited flexibility, as all operations involve the accumulator.

2. Register-Based Architecture

Instructions use multiple general-purpose registers to hold data.


The CPU can operate directly on these registers.
Advantage: More flexible and faster as multiple operands can be held in registers.

3. Stack-Based Architecture

Uses a stack for storing operands.


Operations pop operands from the stack, perform the operation, and push the result back.
Advantage: Simple expression evaluation.
Disadvantage: Limited random access to operands.

4. Memory/Register Architecture

A combination of register and memory architectures.


Instructions can operate on both registers and memory directly.
Advantage: More flexibility in instruction operations.

Instruction Cycle: Fetch-Decode-Execute


The Instruction Cycle describes the steps a CPU follows to execute an instruction:
1. Fetch: The CPU fetches the instruction from memory at the address stored in the Program
Counter (PC).
2. Decode: The instruction is decoded to identify the operation and the operands needed.
3. Execute: The CPU executes the decoded instruction, which could involve arithmetic
operations, data transfer, or control flow.
4. Write-back: The result of the operation is written back to a register or memory location.

This cycle is repeated continuously while the program runs.

Addressing Modes
Addressing modes define how an instruction specifies its operands. Common addressing
modes include:

1. Register Addressing Mode

The operand is in a CPU register.


Example: ADD R1, R2 (Add the value in register R2 to register R1).

2. Immediate Addressing Mode

The operand is a constant value included in the instruction.


Example: ADD R1, #5 (Add 5 to the value in register R1).

3. Direct Addressing Mode

The operand is located in memory, and the instruction directly specifies the memory
address.
Example: LOAD R1, 1000 (Load the value at memory address 1000 into register R1).

4. Indirect Addressing Mode

The instruction provides a memory address, which points to another memory location that
contains the operand.
Example: LOAD R1, (1000) (Use the value at memory address 1000 as an address to
find the operand).
5. Indexed Addressing Mode

An index register is added to a base address to obtain the operand address.


Example: LOAD R1, 1000(R2) (Load the value from memory address 1000 + R2 into
register R1).

Operations in the Instruction Set


Operations in the instruction set generally fall into three main categories:

1. Arithmetic and Logical Operations

Arithmetic: Perform operations like addition, subtraction, multiplication, and division (e.g.,
ADD , SUB , MUL ).
Logical: Perform bitwise operations like AND, OR, XOR, and NOT (e.g., AND , OR , XOR ).

2. Data Transfer Operations

Move data between CPU registers and memory (e.g., LOAD , STORE , MOV ).
Transfer data between registers.

3. Control Flow Operations

Change the sequence of execution (e.g., jumps, branches, function calls).


Example: JMP , CALL , RET , BEQ (branch if equal).

Instruction Set Formats


Instruction formats define how an instruction is encoded in binary. There are three main types:

1. Fixed Format

All instructions have the same length (e.g., 32 bits).


Simplifies instruction decoding but may waste space.
Common in RISC architectures.

2. Variable Format

Instruction length varies depending on the operation.


Saves space but complicates instruction decoding.
Common in CISC architectures.

3. Hybrid Format

Combines features of both fixed and variable formats to balance space efficiency and
simplicity.

Pipelining in CPUs
Pipelining is a technique used to increase CPU throughput by overlapping the execution of
multiple instructions. The instruction cycle is divided into stages (e.g., fetch, decode, execute),
and each stage processes a different instruction simultaneously.

1. Basic Concepts

Each stage of the pipeline handles a different part of an instruction.


As one instruction moves to the next stage, a new instruction enters the first stage,
allowing multiple instructions to be in progress at once.

2. Throughput and Speedup

Throughput refers to the number of instructions the CPU can complete in a given time.
Speedup measures how much faster the pipeline executes instructions compared to non-
pipelined execution.

3. Hazards

Pipelines can encounter problems known as hazards:


Data Hazards: Occur when an instruction depends on the result of a previous instruction
still in the pipeline.
Control Hazards: Occur when the pipeline encounters a branch or jump instruction that
changes the control flow.
Structural Hazards: Occur when two instructions need the same hardware resource at
the same time.

To manage hazards, techniques such as branch prediction, forwarding, and stalling are
used.

This explanation covers the fundamental concepts of CPU organization, ISA, instruction cycle,
addressing modes, and pipelining, providing a detailed breakdown of each topic.

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