Scribd
Upload
11 views2 pages

New Text Document

Uploaded by

sudeepsudeepsr054
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
11 views2 pages

New Text Document

Uploaded by

sudeepsudeepsr054
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
You are on page 1/ 2

3.

Design Verilog HDL to implement simple circuits using structural, data flow and
behavioural model.

Verilog code for structural model

module LogicGates(a,b,c,d,e);
input a,b,c;
output d,e;
wire w1;
and(w1,a,b);
not(e,c);
or(d,w1,e);
endmodule

testbench code
module TestModule;
// Inputs
reg a,b,c;
// Outputs
wire d,e;
// Instantiate the Unit Under Test (UUT)
LogicGates uut (.a(a),.b(b),.c(c),.d(d),.e(e));
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
initial begin
// Initialize Inputs

a = 0;b = 0;c = 0;
#5 a = 0;b = 0;c = 1;
#5 a = 0;b = 1;c = 0;
#5 a = 0;b = 1;c = 1;
#5 a = 1;b = 0;c = 0;
#5 a = 1;b = 0;c = 1;
#5 a = 1;b = 1;c = 0;
#5 a = 1;b = 1;c = 1;
#5;
$finish;
end
endmodule
Verilog code for dataflow model
module LogicGates(a,b,c,d,e);
input a,b,c;
output d,e;
assign d = (a&&b)||(!c);
assign e = !c;
endmodule

Verilog code for behavioural model


module LogicGates(a,b,c,d,e);
input a,b,c;
output reg d,e;
always @(a,b,c)
begin
case({a,b,c})
3'b000: d = 1;
3'b001: d = 0;
3'b010: d = 1;
3'b011: d = 0;
3'b100: d = 1;
3'b101: d = 0;
3'b110: d = 1;
3'b111: d = 1;
default : d = 0;
endcase
case ({a,b,c})
3'b000: e = 1;
3'b001: e = 0;
3'b010: e = 1;
3'b011: e = 0;
3'b100: e = 1;
3'b101: e = 0;
3'b110: e = 1;
3'b111: e = 0;
default : e =0;
endcase
end
endmodule

You might also like