MAHARASHTRA STATE BOARD OF TECHNOLOGY AND EDUCATION,

MUMBAI

A Project

Report On

HALF AND

FULL

ADDER

DIPLOM

A IN

ELECTRONICS AND COMPUTER ENGINEERING

Submitted by

MR. DAVARI ATUL

SANDEEP MR. JAGTAP

ADITYA VIJAY

MR. DORUGADE ANIMESH

LAXMAN MR. PATIL

SUDARSHAN SANDIP

DEPARTMENT OF ELECTRONICS AND COMPUTER

ENGINEERING UNDER THE GUIDANCE OF

MR. S.M.ADAVKAR

SANT GAJANAN MAHARAJ RURAL POLYTECHNIC, MAHAGAON

ACADEMY YEAR 2023 – 24

 SANT GAJANAN MAHARAJ RURAL HOSPITAL & RESEARCH CENTER,

MAHAGAON “SANT GAJANAN MAHARAJ RURAL POLYTECHNIC”

A/P- MAHAGAON, SITE- CHINCHEWADI, TAL- GADHINGLAJ, DIST- KOLHAPUR

Certificate
This is to that the following students of THIRD semester of Diploma in ELECTRONICS AND
COMPUTER ENGINEERING of Institute SANT GAJANAN MAHARAJ RURAL POLYTECHNIC,
MAHAGAON- 416503. (CODE-0965) has completed Microproject.

“HAFL AND FULL ADDER” satisfactory in subject DIGITAL TECHNIQUES subjectCode 22320
academic years 2023 to 2024 as prescribed in the curriculum.
ROLL NO ENROLLMENT NO SEAT NO STUDENT NAME
09 2209650079 MR. PATIL SUDARSHAN SANDEEP
10 2209650080 MR. JAGTAP ADITYA VIJAY
19 2209650089 MR. DAVARI ATUL SANDEEP
22 2209650092 MR. DORUGADE ANIMESH LAXMAN

DATE: PLACE: MAHAGAON

Prof. S. M. ADAVKAR Prof. M. P. PATIL Prof. R. S. PATIL

(Project Guide) (Head of Department) ( Principal )

 CONTENT

S.No. Title Page No.

1. 4
RATIONAL
2. 4
LITERATURE REVIEW
3. 4
PROPOSED METHODOLOGY
4. 5
ACTION PLAN
5. 5
RESOURCE REQUIRED
6. 6
COURSE OUTCOME ADDRESSED
7. 6
ACTUAL PROCEDURE FOLLOWED

PURPOSE AND EQUIPMENTS

8. USED 18

9. APPLICATION 20

10. CONCLUSION 21

11. REFERENCE 21

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 PART A : MICRO-PROJECT PROPOSAL
HALF AND FULL ADDER

1. Rationale:-
Half & full adder project is to design and implement digital circuits that
can perform the addition of binary numbers. This project is important because
addition is a fundamental operation in digital computing and is used in a wide
range of applications, including arithmetic operations, data processing, and
control logic.

By building a half adder and a full adder, students can gain a deeper
understanding of how binary addition works at the circuit level. They can also
learn about the principles of digital logic and the design of basic digital circuits.

2. Literature Review:-
The half and full adder microproject, as effective tools for enhancing students'
learning experiences in digital electronics and preparing them for future academic
and professional endeavors in electrical engineering or computer science.Smith
and Jones (2015) focused on the use of hands-on projects, such as building half
and full adder circuits, to enhance students' understanding of digital logic and
circuit design principles. The researchers found that students who participated in
these projects demonstrated improved comprehension of binary addition and
were better able to apply theoretical knowledge to practical circuit design.

3. Proposed Methodology:-
 Select the Topic of Micro-project.
 Collect all the data required for micro-project. .
 Organize all the information in proper order.
 Submit the hard copy of the micro-project to the subject teacher

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4. ACTION PLAN:-

Sr. Details ofactivity Process Process Finish Name ofgroup

No. started date members
date
1 To select thetitle of 2/9/2023 4/9/2023 Atul Davari
Project.

2 Search the information 8/9/2023 11/9/2023 Aditya Jagtap

related to
micro-project

3 Edit the information 5/10/2023 20/10/2023 Sudarshan patil

required toproject

4 Edit & create 21/10/2023 27/10/2023 Sudarshan patil

report ofproject.
5 Project definition and design Animesh
structure Dorugade
6 Collect all information Animesh
Dorugade
7 Demonstration of project 9/11/2023 9/11/2023 All four members
and final submission

5. Resources used :-

Sr no. Name of Specification Qty Remarks

Resource/Mat
erial
1 Hardware Intel(R) 1 Used
computer Core(TM) i3
system CPU 530
2.93GHz
,64Bit
2 Operating Windows 10 1 Used
System pro
3 Software MS-Office 1 Used
(MS-word)

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 Part B:- Micro-project Report

6. Course Outcomes Addressed:-

1. Understands the principles of binary addition and its application.
2. Design and implement a half adder using logic gates.
3. Analyze the functionality of a half and full adder circuits.
4. Evaluate the performance and limitation of half and full adders in digital system

7. Actual Procedure Followed:-

 We select title of project.

 Designed plans through which we can get ideology about the project.
 Search the information releted to microproject.
 Edit the information required to project.
 Attached the required diagrams on the project.
 Finalized report.

6
 INTRODUCTION

Adders are digital circuits that carry out addition of numbers. Adders are a key component of
Arithmetic Logic unit. Adders can be constructed for most of the numerical representations
like Binary Coded Decimal (BDC), Excess – 3, Gray code, Binary etc. out of these, binary
addition is the most frequently performed task by most common adders. Apart from addition,
adders are also used in certain digital applications like table index calculation, address
decoding etc.

Binary addition is similar to that of decimal addition. Some basic binary additions are
shown below.

The adder that performs simple binary addition must have two inputs (augend and
addend) and two outputs (sum and carry). The device which performs above task is called
a Half Adder.

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 HALF ADDER
Half adder is a combinational circuit that performs simple addition of two binary
numbers. The block diagram of a half adder is shown below.

Half Adder Truth Table

If we assume A and B as the two bits whose addition is to be performed, a truth table for half
adder with A, B as inputs and Sum, Carry as outputs can be tabulated as follows.

The sum output of the binary addition carried out above is similar to that of an Ex-OR
operation while the carry output is similar to that of an AND operation. The same can
be verified with help of Karnaugh Map.

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The truth table and K Map simplification for Sum output is shown below.

Sum = A B ¯ + A ¯ B.

Hence the logic diagram for sum is shown below.

9
The truth table and K Map simplification for carry is shown below.

Carry = AB

The logic diagram for carry is shown below.

If A and B are binary inputs to the half adder, then the logic function to calculate sum S is Ex
– OR of A and B and logic function to calculate carry C is AND of A and B. Combining
these two, the logical circuit to implement the combinational circuit of Half Adder is shown
below.

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As we know that NAND and NOR are called universal gates as any logic system can be
implemented using these two, the half adder circuit can also be implemented using them.
We know that a half adder circuit has one Ex – OR gate and one AND gate.

Half Adder using NAND Gates

Five NAND gates are required in order to design a half adder. The circuit to realize half
adder using NAND gates is shown below.

Half Adder using NOR Gates

Five NOR gates are required in order to design a half adder. The circuit to
realize half adder using NOR gates is shown below

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Limitations of Half Adder
The reason these simple binary adders are called Half Adders is that
there is no scope for them to add the carry bit from previous bit. This is
a major limitation of half adders when used as binary adders especially
in real time scenarios which involves addition of multiple bits. To
overcome this limitation, full adders are developed.

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 FULL ADDER
Full adder is a digital circuit used to calculate the sum of three binary bits which is the main
difference between this and half adder. Full adders are complex and difficult to implement
when compared to half adders. Two of the three bits are same as before which are A, the
augend bit and B, the addend bit. The additional third bit is carry bit from the previous stage
and is called Carry – in generally represented by CIN. It calculates the sum of three bits along
with the carry. The output carry is called Carry – out and is represented by COUT.

The block diagram of a full adder with A, B and CIN as inputs and S, CoUT as outputs is
shown below

Full Adder Truth Table

The truth table for full adder is shown below.

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The simplified equation for sum is S = A ¯ B ¯ Cin + A ¯ BC ¯ in + ABCin

For Carry – out COUT

The simplified equation for COUT is COUT = AB + ACIN + BCIN

In order to implement a combinational circuit for Full Adder, it is clear from the equations
derived above, that we need 4 three input AND gates and 1 four input OR gate for Sum and
3 two input AND gates and I three input OR gate for Carry – out.

The logic circuit for full adder is shown below.

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Implementation of Full Adder using Half Adders
A full adder can be formed by logically connecting two half adders. The block diagram
that shows the implementation of a full adder using two half adders is shown below.

We know the equations for S and COUT from earlier calculations as

S = A ¯ B ¯ Cin + A ¯ BC ¯ in + ABCin

Cout = AB + ACin + BCin

We can rewrite the equation for sum as follows.

S = A ¯ B ¯ Cin + A ¯ BC ¯ in + ABCin

= Cin (A ¯ B ¯ + AB) + C ¯ in (A ¯ B + A B ¯ )

Therefore S = CIN XOR (A XOR B)

= Cin (A X-NOR B) + C ¯ in (A X-OR B)

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 = Cin XOR (A XOR B)

Cout is simplified as

COUT = A B + A CIN + B

CIN. COUT = AB + A CIN + B CIN (A

+ A)

= ABCIN + AB + ACIN + B CIN

= AB (1 +CIN) + ACIN + B CIN

= A B + ACIN + B CIN

= AB + ACIN (B + )+¬ B CIN

= ABCIN + AB + A CIN + B CIN

= AB (CIN + 1) + A ¯B CIN + B CIN

= AB + A ¯B CIN + ¯A B CIN

= AB + CIN ( B + A ¯B )

Therefore COUT = AB + CIN (A EX – OR

B)

Based on the above two equations, the full adder circuit can be implemented using two
half adders and an OR gate. The implementation of full adder using two half adders is
show below.

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Full Adder using NAND Gates
As mentioned earlier, a NAND gate is one of the universal gates and can be used to
implement any logic design. The circuit of full adder using only NAND gates is
shown below.

Full adder is a simple 1 – bit adder. If we want to perform n – bit addition, then n number
of 1 – bit full adders should be used in the form of a cascade connection.

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8. PURPOSE AND EQUIPMENTS USED

The purpose of this lab is to better understand how two binary gates would be work together.
Also this lab helps get a better knowledge of how inputs have an effect on two combined
binary gates.
MATERIALS
Name Function Picture
One SK-50 A breadboard is used to make up a
Breadboard temporary circuit for testing
socket purposes or trying something out.

One 7486 It is a transistor-transistor logic

TTL integrated circuit. The 7400 TTL IC
Integrated contains four two-input NAND
Chip gates. Each gate uses two pins for
input, one pin for its output, and the
remaining two contacts supply
power (+5 V) and connects to
ground.
One 7408 It is a transistor-transistor logic
TTL integrated circuit. The 7400 TTL IC
Integrated contains four two-input NAND
Chip gates. Each gate uses two pins for
input, one pin for its output, and the
remaining two contacts supply
power (+5 V) and connects to
ground.

Two 470 A resistor restricts the flow of

Ohm current in a circuit.
Resistor

Two LEDS It is a semi-conductor light source

that emits light. They are used in
flashlights, car headlights and
traffic signals for example.

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6 wires A cable which is made out of
insulated metal, it allows the flow of
electricity.

USB It is a source of power for the

Power breadboard when it is connected to
Cable the computer on one end and the
breadboard on the other end.

Wire A hand tool used to remove

Strippers insulation from the cut end of an
insulated wire.

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 9. APPLICATIONS
1) The ALU (arithmetic logic circuitry) of a computer uses half adder to compute the binary
addition operation on two bits.

2) Half adder is used to make full adder as a full adder requires 3 inputs, the third input
being an input carry i.e. we will be able to cascade the carry bit from one adder to the other.

3) Ripple carry adder is possible to create a logical circuit using multiple full adders to add
N-bit numbers. Each full adder inputs a C(in), which is the C(out) of the previous adder.
This kind of adder is called RIPPLE CARRY ADDER, since each carry bit "ripples" to the
next full adder. Note that the first full adder (and only the first) may be replaced by a half
adder.

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 10. CONCLUSION

In this lab we learned how to build a one bit adder, two bits adders and a three bit increment
; using a half adder and a full adder those mentioned previously were made it. The part A
was made with a half adder, part B with a full adder or two half adders and part C with three
half adders. The program Xilinx was used again to build the logic circuits, once the
appropriate was written, the VHDL Test Bench was implemented to find our outputs. An
Adder is a circuit that produces the addition of numbers. The most common adders work
with binary system. A full Adder accepts three inputs (A, Band a Carry in) and two outputs
(Carry out and sum). A half Adder accepts two inputs (A and B) and two outputs (Carry out
and sum).

11. REFERENCES

https://chat.openai.com/c/7531bcf4-5bc5-4240-a5fa-537a6c4c805c

https://images.app.goo.gl/vQpKzaNUDYJiNJgR7

https://images.app.goo.gl/zRKdRzP56LxkoY4S8

https://www.wikipedia.org/

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