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Lab 6

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11 views5 pages

Lab 6

Uploaded by

sudeepsudeepsr054
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as TXT, PDF, TXT or read online on Scribd
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module mux_2to1_behavioral (Y, A, B, S);

output Y;
input A, B, S;
reg Y;
always @(A,B,S)
begin
if (S == 0)
Y = A;
else
Y = B;
end
endmodule

2:1 Multiplexer Testbench Code


module mux_2to1_tb_behavioral;
reg S, A, B;
wire Y;
mux_2to1_behavioral uut (.S(S), .A(A), .B(B), .Y(Y));
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
end

initial begin
// $monitor("S=%b, A=%b, B=%b, Y=%b", S, A, B, Y);

// Test case 1: S=0, A=1, B=0


S = 0;
A = 1;
B = 0;
#10;

// Test case 2: S=1, A=0, B=1


S = 1;
A = 0;
B = 1;
#10;

// Test case 3: S=0, A=0, B=1


S = 0;
A = 0;
B = 1;
#10;

// Test case 4: S=1, A=1, B=0


S = 1;
A = 1;
B = 0;
#10;

$finish;
end

endmodule

b) 4:1 Multiplexer Verilog Code

module mux4to1 (out, in0, in1, in2, in3, s);


output out;
input in0, in1, in2, in3;
input [1:0] s;
reg out;
always @(in0,in1, in2, in3, s)
case(s)
2'b00: out = in0;
2'b01: out = in1;
2'b10: out = in2;
2'b11: out = in3;
endcase
endmodule

4:1 Multiplexer Testbench Code


module mux_4to1_tb_behavioral;
reg in0, in1, in2, in3;
reg [1:0] s;
wire out;
mux4to1 uut(.out(out), .in0(in0), .in1(in1), .in2(in2), .in3(in3), .s(s));
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
initial begin
// Test case 1:
s[1:0] = 2'b00;

in0=1;
in1=0;
in2=1;
in3=0;
#10;
// Test case 2:
s[1:0] = 2'b01;
in0=1;
in1=0;
in2=1;
in3=0;
#10;
// Test case 3:
s[1:0] = 2'b10;
in0=1;
in1=0;
in2=1;
in3=0;
#10;
// Test case 4:
s[1:0] = 2'b11;
in0=1;
in1=0;
in2=1;
in3=0;
#10;

$finish;
end

endmodule

a) 8:1 Multiplexer Verilog Code


module mux4to1 (out, in0, in1, in2, in3, in4, in5, in6, in7, s);
output out;
input in0, in1, in2, in3, in4, in5, in6, in7;
input [2:0] s;
reg out;
always @(in0,in1, in2, in3, in4, in5, in6, in7, s)
case(s)
3'b000: out = in0;
3'b001: out = in1;
3'b010: out = in2;
3'b011: out = in3;
3'b100: out = in4;
3'b101: out = in5;
3'b110: out = in6;
3'b111: out = in7;
endcase
endmodule

8:1 Multiplexer Testbench Code

module mux_4to1_tb_behavioral;
reg in0, in1, in2, in3, in4, in5, in6, in7;
reg [2:0] s;
wire out;
mux4to1
uut(.out(out), .in0(in0), .in1(in1), .in2(in2), .in3(in3), .in4(in4), .in5(in5), .i
n6(in6),
.in7(in7), .s(s));
initial begin
$dumpfile("dump.vcd");

$dumpvars(1);
end
initial begin
// Test case 1:
s[2:0] = 3'b000;
in0=1;
in1=0;
in2=1;
in3=0;
in4=1;
in5=1;
in6=0;
in7=0;
#10;
// Test case 2:
s[2:0] = 3'b001;
in0=1;
in1=0;
in2=1;
in3=0;
in4=1;
in5=1;
in6=0;
in7=0;
#10;
// Test case 3:
s[2:0] = 3'b010;
in0=0;
in1=1;
in2=1;

in3=0;
in4=1;
in5=1;
in6=0;
in7=0;
#10;
// Test case 4:
s[2:0] = 3'b011;
in0=1;
in1=0;
in2=1;
in3=0;
in4=1;
in5=1;
in6=0;
in7=0;
#10;
// Test case 5:
s[2:0] = 3'b100;
in0=1;
in1=0;
in2=1;
in3=0;
in4=1;
in5=1;
in6=0;
in7=0;
#10;
// Test case 6:
s[2:0] = 3'b101;

in0=1;
in1=0;
in2=1;
in3=0;
in4=1;
in5=1;
in6=0;
in7=0;
#10;
// Test case 7:
s[2:0] = 3'b110;
in0=1;
in1=0;
in2=1;
in3=0;
in4=1;
in5=1;
in6=0;
in7=0;
#10;
// Test case 8:
s[2:0] = 3'b111;
in0=1;
in1=0;
in2=1;
in3=0;
in4=1;
in5=1;
in6=0;
in7=0;

#10;
$finish;
end
endmodule

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