DEPARTMENT OF COMPUTER ENGINEERING

BE: SEM III Subject: DLCA

Department: Computer Engineering.

Class: SE
Subject: Digital Logic & Computer Organization & Architecture (DLCA)

Experiment List

Serial Name of Experiment

No.
1 To apply the fundamentals of the digital logic for verifying the truth tables
of logic gates.
2 To develop binary to gray and gray to binary code converter.

3 To develop a half adder and full adder circuit using logic gates and verify
it using truth table.
4 To verify the truth tables of JK, D & T flipflop.
5 To implement Booth’s multiplication algorithm using C programming.

6 To implement restoring division algorithm using C programming

language.
7 To implement non-restoring division algorithm using C programming
language.
8 To apply the basics of arithmetic & logical processing for ALU design.
9 To make use of the knowledge of memory organization for implementing
memory design.
10 To implement cache memory design with the help of concepts of
memory organization.

Subject in Charge Head of Department

Prof. Vishakha Chaudhari Prof. S. H. Malave
 Experiment No. 01

STUDY OF BASIC GATES

AIM: To study and verify the truth table of various logic gates using ICs and realize Boolean

expressions using gates.

APPARATUS REQUIRED: Power Supply, Breadboard, Connecting wires

COMPONENTS: ICs 7400, 7402, 7404, 7408, 7432, 7486

ICPINOUTS TRUTH-TABLE

NAND

A B Y=A.B

0 0 1

0 1 1

1 0 1

1 1 0

NOR

A B Y=A+B

0 0 1

0 1 0

1 0 0

1 1 0

NOT

A Y=A
 0 1

1 0

AND

A B Y=A.B

0 0 0

0 1 0

1 0 0

1 1 1

OR

A B Y=A+B

0 0 0

0 1 1

1 0 1

1 1 1

EX-OR

A B Y=AB+AB

0 0 0

0 1 1
 1 0 1

1 1 0

THEORY

Logic gates are the digital circuits with one output and one or more inputs. They are the basic

building blocks of any logic circuit. Different logic gates are: AND, OR, NOT, NAND, NOR, EX-

OR. They work according to certain logic.

AND: Logic eqn. Y = A.B

The output of AND gate is true when the inputs A and B are True.

OR: Logic eqn. Y = A+B.

The output of OR gate is true when one of the inputs A and B or both the inputs are true.

NOT: Logic eqn. Y= .

The output of NOT gate is complement of the input.

NAND: Logic eqn. Y=

The output of NAND gate is true when one of the inputs or both the inputs are low level.

NOR: Logical eqn. Y= .

The output of NOR gate is true when both the inputs are low.

EX-OR: Logic eqn. Y= .

The output of EX-OR gate is true when both the inputs are low.

Implementation for 2 input variables

Implement the Boolean function by using basic logic gates. F = (A + B) * (A + B’)

In the given function, we have a complement term, (A + B) and (A + B’). So, to represent the
compliment input, we are using the NOT gates at the input side. And to represent the sum term,

we use OR gates. See the below given logic diagram for representation of the Boolean function.

PROCEDURE

1) Give biasing to the IC and do necessary connections.

2) Give various combinations of inputs and note down the output for all gate ICs one by one.

1) 3)Realize the expression using basic gates.

CONCLUSION

Thus, all basic gates are studied.

 Experiment No. 02
BINARY TO GREY CODE ANDGREY TO BINARY CODE CONVERSION

AIM: To realize binary to gray code and gray code to binary converter.

APPARATUS: Power supply, Breadboard, connecting wire.

COMPONENTS: IC 7486.

THEORY:

The availability of large variety of codes for the same discrete elements of information results in

the use of different codes by different systems. A conversion circuit must be inserted between

the two systems if each uses different codes for same information. Thus, code converter is a

circuit that makes the two systems compatible even though each uses different binary code.

The bit combination is assigned to binary code to gray code. Each code uses four bits to

represent a decimal digit. There are four inputs and four outputs. Gray code is a non-weighted

code.

The input variables are designated as B3, B2, B1, B0 and the output variables are designated

as C3, C2, C1, Co. from the truth table, combinational circuit is designed. The Boolean functions

are obtained from K-Map for each output variable.

A code converter is a circuit that makes the two systems compatible even though each uses a

different binary code. To convert from binary code to Excess-3 code, the input lines must supply

the bit combination of elements as specified by code and the output lines generate the

corresponding bit combination of code. Each one of the four maps represent one of the four

outputs of the circuit as a function of the four input variables.

A two-level logic diagram may be obtained directly from the Boolean expressions derived by the

maps. These are various other possibilities for a logic diagram that implements this circuit. Now

the OR gate whose output is C+D has been used to implement partially each of three outputs.

TRUTH TABLE
 B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

K-Map for G3 : K-Map for G2 :

G3 = B3

K-Map for G1 K-Map for G0

K-Map for B3: K-Map for B2:

B3 = G3

K-Map for B1: K-Map for B0:

PROCEDURE:

1) Connect VCC and ground pins of IC to the power supply.

2) Connect the circuit as shown in the figure.

3) Obtain output for different combinations of inputs.

4) Verify truth tables.

BINARY TO GRAY CODE CONVERTOR:

CIRCUIT DIAGRAM:

GRAY CODE TO BINARY CONVERTER:

TRUTH TABLE:

G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
 0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1

CIRCUIT DIAGRAM:

RESULT:
Thus, conversion from grey to binary and binary to grey code conversion is studied.
 Experiment No. 03
DESIGN A (I) HALF ADDER AND (II) FULL ADDER

AIM: To realize arithmetic circuits i) Half adder ii) Full adder.

APPARATUS: Power supply, Breadboard, connecting wire.

COMPONENTS: IC 7408,7486,7404,7432.

THEORY:

HALF ADDER:

A half adder has two inputs for the two bits to be added and two outputs one from the sum ‘S’

and other from the carry ‘c’ into the higher adder position. The circuit is called as a carry signal

from the addition of the less significant bits sum from the X-OR Gate the carry out from the AND

gate.

FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of input; it consists of three

inputs and two outputs. A full adder is useful to add three bits at a time but a half adder cannot

do so. In full adder sum output will be taken from X-OR Gate, carry output will be taken from OR

Gate.
TRUTH TABLE OF HALF ADDER:

A B CARRY SUM

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

K-Map for SUM: K-Map for CARRY

SUM=A’B+AB’ CARRY=AB

=AB

CIRCUIT DIAGRAM:
TRUTH TABLE OF FULL ADDER:
A B C CARRY SUM

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

K-MAP FOR SUM:

 SUM = A’B’C + A’BC’ + ABC’ + ABC

=A B C

K-MAP FOR CARRY:

CARRY = AB + BC + AC

CIRCUIT DIAGRAM:
PROCEDURE:
1) Connections are given as per circuit diagram.

2) Logical inputs are given as per circuit diagram.

3) Observe the output and verify the truth table.

RESULT:

Thus, the half adder and full adder was designed and their truth table is verified
 Experiment No. 04
FLIP-FLOPS

AIM: Design the JK and SR Flip Flop using NAND as Universal gate. Verify the truth table of JK

Flip Flop using IC 7476. Implement T Flip Flop and D Flip Flop using JK Flip Flop

APPARATUS REQUIRED: Power supply, Breadboard

COMPONENTS: IC 7400, IC 7410, IC 7473, IC 7474, IC 7476

PindiagramofIC-7476

CIRCUIT DIAGRAM AND TRUTH TABLE:

I) SRFF using NAND

II) JK FF using NAND

III) JKFF (IC7476)

Clk J K Q Q Comment

0 0 NC NC No Change

0 1 0 1 Reset
 1 0 1 0 Set

1 1 Toggle Toggle

IV) TFF using JK

Clk T Q Q

0 NC NC

1 Toggle

V) DFF using JK

Clk D Q Q Comment

0 0 0 Reset

1 1 1 Set

THEORY:

Flip-flops are the basic building blocks of sequential ckt. The clocked FFs change their o/p state

depending upon i/p's at certain interval of time synchronized with the clock pulse applied to it.

Different types of FFs are S-R, J-K, D&T. Their operations are described by the respective truth

tables. MSI chip 7476 incorporates two negative edge triggered Master–Slave JK flip flops. The

J-K flip flop can be converted to D&T flip flop.

PROCEDURE:

1) Give biasing to the IC and do necessary connections.

2) For various combinations of i/p verify the truth table.

CONCLUSION:

Thus R-S, J-K, D&T Flip-Flops are studied.

ASSIGNMENTS:

1) Construct clocked S-R FF using only NAND gates & verify the truth table.

2) Verify the truth table of J-K FF using IC 7476.Observe the effect of Preset & Clear i/ps.

3) Convert the J-K FF to D&T FF.