RNS INSTITUTE OF TECHNOLOGY

(AICTE Approved, VTU Affiliated and NAAC‘A+ Grade’ Accredited)

(UG programs – CSE, ECE, ISE, EIE and EEE have been Accredited by NBA up to 30/6/2025)
Channasandra, Dr. Vishnuvardhan Road, Bengaluru - 560 098
DEPARTMENT OF COMPUTER SCIENCE &ENGINEERING

DIGITAL DESIGN & COMPUTER

ORGANISATION LABORATORY
MANUAL

For Third Semester B.E-2023 Batch

[VTU/CBCS, 2022 syllabus]
Subject Code – BCS302

NAME : .......................................................................................................................................................................................................................................................................................................................................................................................................................................

USN :.....................................................................................................................................................................................................................................................................................................................................................................................................................................................

SECTION : ................................................................................................................................................................... BATCH : ...........................................................................................................................................................................................

 VISION AND MISSION OF INSTITUTION
Vision
Building RNSIT into a World Class Institution

Mission
To impart high quality education in Engineering, Technology and Management with a
Difference, Enabling Students to Excel in their Career by
1. Attracting quality Students and preparing them with a strong foundation in fundamentals so as to
achieve distinctions in various walks of life leading to outstanding contributions
2. Imparting value based, need based, choice based and skill based professional education to the
aspiring youth and carving them into disciplined, World class Professionals with social
responsibility
3. Promoting excellence in Teaching, Research and Consultancy that galvanizes academic
consciousness among Faculty and Students
4. Exposing Students to emerging frontiers of knowledge in various domains and make them suitable
for Industry, Entrepreneurship, Higher studies, and Research & Development
5. Providing freedom of action and choice for all the Stake holders with better visibility

VISION AND MISSION OF CSE DEPARTMENT

Vision
Preparing better computer professionals for a real world

Mission
The Department of Computer Science and Engineering will make every effort to promote an
intellectual and an ethical environment in which the strengths and skills of Computer
Professionals will flourish by
1. Imparting Solid foundations and Applied aspects in both Computer Science Theory and
Programming practices
2. Providing Training and encouraging R&D and Consultancy Services in frontier areas of Computer
Science with a Global outlook
3. Fostering the highest ideals of Ethics, Values and creating Awareness on the role of Computing
in Global Environment
4. Educating and preparing the graduates, highly Sought-after, Productive, and Well-respected for
their work culture
5. Supporting and inducing Lifelong Learning practice
 PREFACE

We have developed this comprehensive laboratory manual on Digital design & computer
organization with the primary objectives: To make the students comfortable with the Verilog
hardware description language. The manual will help them to learn various digital circuit
modelling issues using Verilog, and some case studies. Through this course students will get
exposure to design of digital circuits using Verilog HDL.

Our profound and sincere efforts will be fruitful only when students acquire the extensive
knowledge by reading this manual and apply the concepts learnt apart from the requirements
specified in Digital design & computer organization Laboratory as prescribed by VTU,
Belagavi.

Department of CSE
 ACKNOWLEDGMENT

A material of this scope would not have been possible without the contribution of many people. We
express our sincere gratitude to Mr. Satish R Shetty, Chairman of RNS Group of Companies for
providing magnanimous support in all our endeavors.

We are grateful to Dr. Ramesh Babu H S, Principal, RNSIT and Dr. Kiran P, HOD, CSE for
extending their constant encouragement and support.

Our heartfelt thanks to Mr. Prasanna Kumar M, Mrs. Lakshmi R and Mrs. Supritha N for their
unparalleled contribution throughout the preparation of this comprehensive manual. We also
acknowledge our colleagues for their timely suggestions and unconditional support.

Department of CSE

Department of CSE, RNSIT

 DIGITAL DESIGN & COMPUTER ORGANIZATION LABORATORY
INTERNAL EVALUATION SHEET

EVALUATION (MAX MARKS 25)

TEST REGULAR RECORD TOTAL MARKS
EVALUATION
A B C A+B+C
10 5 10 25

R1: REGULAR LAB EVALUATION WRITE UP RUBRIC (MAX MARKS 10)

Sl. Needs
No. Parameters Good Average
improvement
a. Understanding of Clear understanding of problem Problem statement is understood Problem statement is not
problem statement while designing and clearly but few mistakes while clearly understood while
(3 marks) implementing the program (3) designing and implementing designing the program (1)
program (2)
b. Writing program Program handles all possible Average condition is defined and Program does not handle
(4 marks) conditions (4) verified. (3) possible conditions (1)
c. Result and Meticulous documentation and Acceptable documentation shown Documentation does not
documentation all conditions are taken care (3) (2) take care all conditions
(3 marks) (1)

R2: REGULAR LAB EVALUATION VIVA RUBRIC (MAX MARKS 10)

Sl. Needs
Parameter Excellent Good Average
No. Improvement
a. Conceptual Answers 80% of the Answers 60% of the viva Answers 30% of the Unable to relate the
understanding viva questions asked questions asked (7) viva questions asked concepts (1)
(10 marks) (10) (4)

R3: REGULAR LAB PROGRAM EXECUTION RUBRIC (MAX MARKS 10)

Sl.
Parameters Excellent Good Needs Improvement
No.
a. Design, implementation Program follows syntax and Program has few logical Syntax and semantics
and demonstration semantics of Verilog errors, moderately of Verilog
(5 marks) programming language. demonstrates all possible programming is not
Demonstrates the complete concepts implemented in clear (1)
knowledge of the program written programs (3)
(5)
b. Result and All expected results are Moderately debugs the Expected results are not
documentation demonstrated successful, all program and Partial demonstrated properly,
(5 marks) errors are debugged with own documentation unable to debug the
practical knowledge and clear (3) errors and no proper
documentation according to the documentation (1)
guidelines (5)

R4: RECORD EVALUATION RUBRIC (MAX MARKS 20)

Sl. Needs
Parameter Excellent Good Average
No. Improvement
a. Documentation Meticulous record writing Write up contains Write up contains Program written
(10 marks) including program, comments program and expected only program (15) with few mistakes
and expected output as per the output, but comments (10)
guidelines mentioned (20) are not included (18)

Department of CSE, RNSIT

A. TEST /LAB INTERNALS MARKS (MAX MARKS 10)
Write up Execution Viva Sign Total Avg. Final
TEST # 6 28 6 40 40 10

TEST-1

TEST-2 𝟒𝟎 10

B. REGULAR LAB EVALUATION (MAX MARKS 5)

Write
Date of Exen. Viva Total Teacher
Program # Lab programs up
Execution (10) (10) 30 Signature
(10)

Total
Marks 240 3𝟎 5

Department of CSE, RNSIT

 FINAL MARKS OBTAINED

A : TEST (10) TOTAL Signature of lab in charge:

(A+B+C)
B : REGULAR EVALUATION (5)

C: RECORD (10) 25

Department of CSE, RNSIT

Digital Design & Computer Organization Laboratory (BCS302)

TABLE OF CONTENTS
SL. PAGE
NO. CONTENTS
NO.
INTRODUCTION
LABORATORY PROGRAMS

1 Simplify a 4-variable logic expression

1.1 Program
1.2 Output

2 Design a 4-bit full adder and subtractor

2.1 Program
2.2 Output

3 Design Verilog HDL to implement simple circuits

3.1 Program
3.2 Output

4 Design Verilog HDL to implement Binary Adder-Subtractor

4.1 Program
4.2 Output

5 Design Verilog HDL to implement Decimal adder.

5.1 Program
5.2 Output

6 Design Verilog HDL to implement multiplexer like 2:1, 4:1 and 8:1
6.1 Program
6.2 Output

7 Design Verilog HDL to implement types of De-Multiplexer

7.1 Program
7.2 Output

8 Design Verilog HDL to implement types of Flip-Flops such as SR,

JK and D
8.1 Program
8.2 Output
VIVA QUESTIONS
ADDITIONAL PROGRAMS

1
 Digital Design & Computer Organization Laboratory (BCS302)

SYALLABUS
SEMESTER – III
DIGITAL DESIGN & COMPUTER ORGANIZATION LABORATORY
(Effective from the academic year 2023-2024)

Course Code – BCS302 CIE Marks - 50

Number of Contact Hours/Week -3:0:2:0 SEE Marks - 50

Total Number of Lab Contact Hours - 20 Exam Hours - 03

Course Learning Objectives:

This course will enable students to:

• To demonstrate the functionalities of binary logic system
● To explain the working of combinational and sequential logic system

Programs List:
Sl.No Experiments

Simulation packages preferred: Multisim, Modelsim, PSpice or any other relevant

1 Given a 4-variable logic expression, simplify it using appropriate technique and simulate the same
using basic gates.

2 Design a 4 bit full adder and subtractor and simulate the same using basic gates.

3 Design Verilog HDL to implement simple circuits using structural, Data flow and Behavioural model.

4 Design Verilog HDL to implement Binary Adder-Subtractor – Half and Full Adder, Half and Full
Subtractor.

5 Design Verilog HDL to implement Decimal adder.

6 Design Verilog program to implement Different types of multiplexer like 2:1, 4:1 and 8:1.

7 Design Verilog program to implement types of De-Multiplexer.

8 Design Verilog program for implementing various types of Flip-Flops such as SR, JK and D.
 Digital Design & Computer Organization Laboratory (BCS302)

COs COURSE OUTCOMES

BCS302.1 Interpret the basics of digital design and fundamentals of machine instructions,
addressing modes and Processor performance.
BCS302.2 Study the approaches involved in achieving communication between processor
and I/O devices.
BCS302.3 Apply various techniques to simplify Boolean expressions and design
combinational and sequential circuits with HDL.
BCS302.4 Analyze internal Organization of Memory and Impact of cache/Pipelining on
Processor Performance.

Laboratory Outcomes: The student should be able to:

Apply the K–Map techniques to simplify various Boolean expressions.
Design different types of combinational and sequential circuits along with Verilog programs.
Describe the fundamentals of machine instructions, addressing modes and Processor
performance.
CIE for the practical component of the IPCC

● 15 marks for the conduction of the experiment and preparation of laboratory record, and 10 marks
for the test to be conducted after the completion of all the laboratory sessions.
● On completion of every experiment/program in the laboratory, the students shall be evaluated including
viva-voce and marks shall be awarded on the same day.
● The CIE marks awarded in the case of the Practical component shall be based on the continuous
evaluation of the laboratory report. Each experiment report can be evaluated for 10 marks. Marks of all
experiments’ write-ups are added and scaled down to 15 marks.
● The laboratory test (duration 02/03 hours) after completion of all the experiments shall be conducted
for 50 marks and scaled down to 10 marks.
● Scaled-down marks of write-up evaluations and tests added will be CIE marks for the laboratory
component of IPCC for 25 marks.
● The student has to secure 40% of 25 marks to qualify in the CIE of the practical component of the IPCC.

CO-PO MATRIX
COURSE
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3 PSO4
OUTCOMES
CO1 3 3 3 1 1 - - - - - - 2 3 3 1 -
CO2 3 3 3 1 - - - - - - - 2 3 2 2 -
CO3 3 3 3 3 3 - - - - - - 2 3 3 1 -
CO4 3 3 3 1 - - - - - - - 2 3 2 2 -
 Digital Design & Computer Organization Laboratory (BCS302)

DIGITAL DESIGN & COMPUTER ORGANIZATION

LABORATORY

INTRODUCTION
Language Overview

Verilog HDL is a Hardware Description Language (HDL). A Hardware Description

Language is a language used to describe a digital system, for example, a computer or a component of
a computer. One may describe a digital system at several levels. For example, an HDL might describe
the layout of the wires, resistors and transistors on an Integrated Circuit (IC) chip and the switch
level. Or, it might describe the logical gates and flip flops in a digital system, i.e., the gate level. An
even higher level describes the registers and the transfers of vectors of information between registers.
This is called the Register Transfer Level (RTL). Verilog supports all of these levels. However, this
handout focuses on only the portions of Verilog which support the RTL level.
What is Verilog?
Verilog is one of the two major Hardware Description Languages (HDL) used by hardware
Designers in industry and academia. VHDL is the other one. The industry is currently split on
Which is better. Many feel that Verilog is easier to learn and use than VHDL. As one hardware
designer puts it, “I hope the competition uses VHDL.” VHDL was made an IEEE Standard in1987,
and Verilog in 1995.
Verilog was introduced in 1985 by Gateway Design System Corporation, now a part of
Cadence Design Systems, Inc.’s Systems Division. Until May, 1990, with the formation of Open
Verilog International (OVI), Verilog HDL was a proprietary language of Cadence. Cadence was
motivated to open the language to the Public Domain with the expectation that the market for Verilog
HDL-related software products would grow more rapidly with broader acceptance of the language.
Cadence realized that Verilog HDL users wanted other software and service companies to embrace
the language and develop Verilog-supported design tools.
Verilog HDL allows a hardware designer to describe designs at a high level of abstraction
such as at the architectural or behavioural level as well as the lower implementation levels (i. e. , gate
and switch levels) leading to Very Large Scale Integration (VLSI) Integrated Circuits (IC) layouts and
chip fabrication. A primary use of HDLs is the simulation of designs before the designer must commit
to fabrication. This handout does not cover all of Verilog HDL but focuses on the use of Verilog HDL
 Digital Design & Computer Organization Laboratory (BCS302)
at the architectural or behavioural levels. The handout emphasizes design at the Register Transfer
Level (RTL).

Why Use Verilog HDL?

Digital systems are highly complex. At their most detailed level, they may consists of millions
of elements, i. e., transistors or logic gates. Therefore, for large digital systems, gate-level design is
dead. For many decades, logic schematics served as the lingua franca of logic design, but not
anymore. Today, hardware complexity has grown to such a degree that a schematic with logic gates is
almost useless as it shows only a web of connectivity and not the functionality of design. Since the
1970s, Computer engineers and electrical engineers have moved toward hardware description
languages (HDLs).
The most prominent modern HDLs in industry are Verilog and VHDL. Verilog is the top HDL
used by over 10,000 designers at such hardware vendors as Sun Microsystems, Apple Computer and
Motorola. Industrial designers like Verilog. It works.
The Verilog language provides the digital designer with a means of describing a digital system at a
wide range of levels of abstraction, and, at the same time, provides access to computer-aided design
tools to aid in the design process at these levels.
Verilog allows hardware designers to express their design with behavioural constructs,
deterring the details of implementation to a later stage of design in the design. An abstract
representation helps the designer explore architectural alternatives through simulations and to detect
design bottlenecks before detailed design begins.
Though the behavioural level of Verilog is a high-level description of a digital system, it is
still a precise notation. Computer-aided-design tools, i. e., programs, exist which will “compile”
programs in the Verilog notation to the level of circuits consisting of logic gates and flip flops. One
could then go to the lab and wire up the logical circuits and have a functioning system. And, other
tools can “compile” programs in Verilog notation to a description of the integrated circuit masks for
very large-scale integration (VLSI). Therefore, with the proper automated tools, one can create a
VLSI description of a design in Verilog and send the VLSI description via electronic mail to a silicon
foundry in California and receive the integrated chip in a few weeks by way of snail mail. Verilog
also allows the designer to specific designs at the logical gate level using gate constructs and the
transistor level using switch constructs.
Our goal in the course is not to create VLSI chips but to use Verilog to precisely describe the
functionality of any digital system, for example, a computer. However, a VLSI chip designed by way
of Verilog’s behavioural constructs will be rather slow and be wasteful of chip area. The lower levels
 Digital Design & Computer Organization Laboratory (BCS302)
in Verilog allow engineers to optimize the logical circuits and VLSI layouts to maximize speed and
minimize area of the VLSI chip.
 Digital Design & Computer Organization Laboratory (BCS302)

Program Structure
The Verilog language describes a digital system as a set of modules. Each of these modules
has an interface to other modules to describe how they are interconnected. Usually, we place one
module per file but that is not a requirement. The modules may run concurrently, but usually we have
one top level module which specifies a closed system containing both test data and hardware models.
The top-level module invokes instances of other modules.
Modules can represent pieces of hardware ranging from simple gates to complete systems,
e. g., a microprocessor. Modules can either be specified behaviourally or structurally (or a
combination of the two). A behavioural specification defines the behaviour of a digital system
(module) using traditional programming language constructs, e. g., ifs, assignment statements. A
structural specification expresses the behaviour of a digital system (module) as a hierarchical
interconnection of sub modules. At the bottom of the hierarchy the components must be primitives or
specified behaviourally. Verilog primitives include gates, e. g., nand, as well as pass transistors
(switches).
The structure of a module is the following:
module <module name> (<port list>);
<declares>
<module items>
End module
The <module name> is an identifier that uniquely names the module. The <port list> is a list
of input, inout and output ports which are used to connect to other modules. The <declares> section
specifies data objects as registers, memories and wires as wells as procedural constructs such as
functions and tasks.
The <module items> may be initial constructs, always constructs, continuous assignments or
instances of modules.
Digital Design & Computer Organization Laboratory (BCS302)

Simulation
Steps:
1. Start The Xilinx Project Navigator By Using The Desktop Shortcut or By using the Start
→Programs →Xilinx ISE (14.7).
2. Create a New project Select File menu and Then Select New Project.
3. Specify the project Name and Location in pop up Window and click next.
4. To Create New Verilog file Right click on the device name and Select NEW SOURCE.
Select Verilog module in New Source Wizard and Give Suitable name for the Project Click
NEXT for the Define Module Window.
5. Write Behavioral Verilog code in Verilog Editor.