General Purpose Input/Output

ECE473: Embedded Systems

University of Michigan - Dearborn

Dr. Samir Rawashdeh

Includes material by:

- UT-Austin - Bard, Valvano, Gerstlauer, and Yerraballi
- TI Tiva C Series Reference Material

1
 ARM Cortex M4-based System
Microcontroller System bus
ARM® CortexTM-M I/O
processor
Input
PPB NVIC High- ports
speed
32-bit I/O
Instructions
Internal
Advanced
peripherals High-perf Output
Bus ports
Instructions
Flash ROM Data
ICode bus DCode bus RAM
Debugging
 ARM Cortex-M4 processor
 Harvard architecture
 Different busses for instructions and data
 RISC machine
 Pipelining effectively provides single cycle operation for many
instructions .
 Thumb-2 configuration employs both 16 and 32 bit instructions
 Tiva
TM4C123x
Diagram

3
 Input/Output: TM4C123
Cortex M4 Systick
System Bus Interface NVIC

GPIO Port A GPIO Port B

PA7 PB7
PA6 Four PB6
PA5/SSI0Tx Eight PB5
UARTs I2Cs
PA4/SSI0Rx PB4
PA3/SSI0Fss PB3/I2C0SDA
PA2/SSI0Clk Four PB2/I2C0SCL
PA1/U0Tx CAN 2.0 PB1
SSIs
PA0/U0Rx PB0
GPIO Port C GPIO Port D
PC7
PC6
Twelve
PD7
PD6 6 General-Purpose
PC5 USB 2.0 PD5
PC4
PC3/TDO/SWO
Timers PD4
PD3 I/O (GPIO) ports:
PC2/TDI Six PD2
PC1/TMS/SWDIO
PC0/TCK/SWCLK
JTAG
64-bit wide PD1
PD0
• Four 8-bit ports
GPIO Port E GPIO Port F
(A, B, C, D)
PE5
PE4 ADC Two Analog PF4 • One 6-bit port (E)
PE3 2 channels Comparators PF3
PE2
PE1
12 inputs
Two PWM
PF2
PF1
• One 5-bit port (F)
12 bits
PE0 Modules PF0

Advanced High Performance Bus Advanced Peripheral Bus

 Switch Configuration
+3.3V +3.3V
TM4C TM4C
10kΩ
s Input port t Input port
10kΩ
Negative logic Positive logic

Negative Logic s Positive Logic t

– pressed, 0V, false – pressed, 3.3V, true
– not pressed, 3.3V, true – not pressed, 0V, false
+3.3V +3.3V +3.3V +3.3V
TM4C TM4C TM4C TM4C
10kΩ 10kΩ
3.3V 0V
s Input port s Input port t Input port t Input port
0.0V 3.3V
10kΩ 10kΩ
Pressed Not pressed Pressed Not pressed
 LED Configuration

Current
high LM3S +3.3V
2 + a Out R
I I or 1mA
R 1mA TM4C
(mA) 1 - k LM3S LED
or
TM4C LED
voltage low
0 Out
1.5 1.6 1.7
V (volts)
(a) LED curve (b) Positive logic interface (c) Negative logic interface
 LED Interfacing
R = (3V – 1.5)/0.001 R = (5.0-2-0.5)/0.01
= 1.5 kOhm = 220 Ohm
high LM3S +5V
Out or R 10mA
R 1mA TM4C 7406
LM3S
or +5V LED
TM4C LED
high 0.5V
Out

LED current < 8 ma LED current > 8 ma

 LaunchPad Switches and LEDs
R1 0Ω
TM4C123 PF0
PF4
Serial PA1 R13 0Ω 5V
PA0 Green
R29 Blue Red
+5 PB1
0Ω 330Ω 330Ω 330Ω
USB PD5
PD4 R12 SW1 SW2
R25 PF3
PB0 0Ω
0Ω
PD0 R11
R9 0Ω
PB6 PF2
0Ω
R10 0Ω
PD1 R2 DTC114EET1G
PB7 PF1
0Ω

 The switches on the LaunchPad

Negative logic
Require internal pull-up (set bits in PUR)
 The PF3-1 LEDs are positive logic
I/O Ports and Control Registers
Read from port address
n n GPIO_PORTF_DATA_R
Processor
n n
DQ Input/Output Port

Write to port address

Direction bits
GPIO_PORTF_DIR_R
n 1 means output
DQ 0 means input
Bus Write to port direction register

• The input/output direction of a bidirectional port is

specified by its direction register.
• GPIO_PORTF_DIR_R , specify if corresponding
pin is input or output:
– 0 means input
– 1 means output
 I/O Ports and Control Registers
Address 7 6 5 4 3 2 1 0 Name
400F.E108 - - GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA SYSCTL_RCGC2_R
4002.53FC - - - DATA DATA DATA DATA DATA GPIO_PORTF_DATA_R
4002.5400 - - - DIR DIR DIR DIR DIR GPIO_PORTF_DIR_R
4002.5420 - - - SEL SEL SEL SEL SEL GPIO_PORTF_AFSEL_R
4002.551C - - - DEN DEN DEN DEN DEN GPIO_PORTF_DEN_R

• Initialization (executed once at beginning)

1. Turn on clock in SYSCTL_RCGC2_R
2. Wait two bus cycles (two NOP instructions)
3. Set DIR to 1 for output or 0 for input
4. Clear AFSEL bits to 0 to select regular I/O
5. Set DEN bits to 1 to enable data pins
• Input/output from pin
6. Read/write GPIO_PORTF_DATA_R
 To set
The or operation to set bits 1 and 0 of a register.
The other six bits remain constant.
Friendly software modifies just the bits that need to be.
GPIO_PORTD_DIR_R |= 0x03; // PD1,PD0 outputs
Assembly:
LDR R0,=GPIO_PORTD_DIR_R
LDR R1,[R0] ; read previous value
ORR R1,R1,#0x03 ; set bits 0 and 1
STR R1,[R0] ; update

c7 c6 c5 c4 c3 c2 c1 c0 value of R1
0 0 0 0 0 0 1 1 0x03 constant
c7 c6 c5 c4 c3 c2 1 1 result of the ORR

Bard, Gerstlauer, Valvano, Yerraballi

 To clear
The AND operation can also be used to clear bits.
GPIO_PORTD_DATA_R &= 0xFE; /* clear PD0 */

Assembly:
LDR R0,=GPIO_PORTD_DATA_R
LDR R1,[R0] ; read port D
AND R1,R1,#0xFE ; clear bit 0
STR R1,[R0] ; update

b7 b6 b5 b4 b3 b2 b1 b0 value of R1
1 1 1 1 1 1 1 0 0xFE constant
b7 b6 b5 b4 b3 b2 b1 0 result of the AND

Bard, Gerstlauer, Valvano, Yerraballi

 To toggle
The exclusive or operation can also be used to toggle bits.
GPIO_PORTD_DATA_R ^= 0x80; /* toggle PD7 */

Assembly:
LDR R0,=GPIO_PORTD_DATA_R
LDR R1,[R0] ; read port D
EOR R1,R1,#0x80 ; toggle bit 7
STR R1,[R0] ; update

b7 b6 b5 b4 b3 b2 b1 b0 value of R1
1 0 0 0 0 0 0 0 0x80 constant
~b7 b6 b5 b4 b3 b2 b1 b0 result of the EOR

Bard, Gerstlauer, Valvano, Yerraballi

 TM4C123 I/O registers
Address 7 6 5 4 3 2 1 0 Name
$400F.E108 - - GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA SYSCTL_RCGC2_R
$4000.4000 PORTA base address
$4000.5000 PORTB base address
$4000.6000 PORTC base address
$4000.7000 PORTD base address
$4002.4000 PORTE base address
$4002.5000 PORTF base address
base+$3FC DATA DATA DATA DATA DATA DATA DATA DATA GPIO_PORTx_DATA_R
base+$400 DIR DIR DIR DIR DIR DIR DIR DIR GPIO_PORTx_DIR_R
base+$420 SEL SEL SEL SEL SEL SEL SEL SEL GPIO_PORTx_AFSEL_R
base+$510 PUE PUE PUE PUE PUE PUE PUE PUE GPIO_PORTx_PUR_R
base+$51C DEN DEN DEN DEN DEN DEN DEN DEN GPIO_PORTx_DEN_R
base+$524 CR CR CR CR CR CR CR CR GPIO_PORTx_CR_R
base+$528 AMSEL AMSEL AMSEL AMSEL AMSEL AMSEL AMSEL AMSEL GPIO_PORTx_AMSEL_R

31-28 27-24 23-20 19-16 15-12 11-8 7-4 3-0

base+$52C PMC7 PMC6 PMC5 PMC4 PMC3 PMC2 PMC1 PMC0 GPIO_PORTx_PCTL_R
base+$520 LOCK (32 bits) GPIO_PORTx_LOCK_R

• Four 8-bit ports (A, B, C, D) • PA1-0 to COM port

• One 6-bit port (E) • PC3-0 to debugger
• One 5-bit port (F) • PD5-4 to USB device
Ramesh Yerraballi, Jon Valvano, Bill Bard, Andreas Gerstlauer
 Initialization Ritual

• Initialization (executed once at beginning)

1. Turn on Port F clock in SYSCTL_RCGC2_R
Wait two bus cycles (two NOP)
2. Unlock PF0 (PD7 also needs unlocking)
3. Clear AMSEL to disable analog
4. Clear PCTL to select GPIO
5. Set DIR to 0 for input, 1 for output
6. Clear AFSEL bits to 0 to select regular I/O
Set PUE bits to 1 to enable internal pull-up
7. Set DEN bits to 1 to enable data pins
• Input from switches, output to LED
Read/write GPIO_PORTF_DATA_R
Prog 4.1, show PortF_Init function in InputOutput_xxxasm
 Abstraction - Device Driver
Abstraction allows us to modularize our code and give us
the option to expose what we want users to see and hide
what we don’t want them to see.
A Device Driver is a good example where abstraction is
used to expose public routines that we want users of the
driver to call and use private routines to hide driver
internals from the user (more on private routines later)
LED Driver(PE0)
LED_Init
A user simply has to know
LED_Off what a routine expects and
LED_On what it returns in order to
call it (calling convention).
LED_Toggle Internals do not matter to caller
 Port E LED Abstraction
PE0 EQU 0x40024004 ;bit-specific address Port E bit 0
LED_Init
LDR R1, =SYSCTL_RCGC2_R ; R1 -> SYSCTL_RCGC2_R
LDR R0, [R1] ; previous value
ORR R0, R0, #0x00000010 ; activate clock for Port E
STR R0, [R1]
NOP
NOP ; allow time to finish activating
LDR R1, =GPIO_PORTE_DIR_R ; R1 -> GPIO_PORTE_DIR_R
LDR R0, [R1] ; previous value
ORR R0, R0, #0x01 ; PE0 output
STR R0, [R1] ; set direction register
LDR R1, =GPIO_PORTE_AFSEL_R ; R1 -> GPIO_PORTE_AFSEL_R
LDR R0, [R1] ; previous value
BIC R0, R0, #0x01 ; disable alt funct
STR R0, [R1] ; set alternate function register
LDR R1, =GPIO_PORTE_DEN_R ; R1 -> GPIO_PORTE_DEN_R
LDR R0, [R1] ; previous value
ORR R0, R0, #0x01 ; enable PE0 digital port
STR R0, [R1] ; set digital enable register
BX LR

Program 4.3. Software interface for an LED on PE0 (SSR_xxx.zip).

 Port E LED Abstraction
LED_Off
LDR R1, =PE0 ; R1 is 0x40024004
MOV R0, #0
STR R0, [R1] ; affect just PE0
BX LR
LED_On
LDR R1, =PE0 ; R1 is 0x40024004
MOV R0, #1
STR R0, [R1] ; affect just PE0
BX LR
LED_Toggle
LDR R1, =PE0 ; R1 is 0x40024004
LDR R0, [R1] ; previous value
EOR R0, R0, #1 ; flip bit 0
STR R0, [R1] ; affect just PE0
BX LR
Program 4.3. Software interface for an LED on PE0 (SSR_xxx.zip).
 I/O Port Bit-Specific
• I/O Port bit-specific
addressing is used to
access port data register
– Define address offset as
4*2b, where b is the
selected bit position
– 256 possible bit Port F = 0x4002.5000
combinations (0-8)
0x4002.5000+0x0004+0x0040
– Add offsets for each bit
= 0x4002.5044
selected to base address
for the port
Provides friendly and atomic
– Example: PF4 and PF0
access to port pins

Show PortF_Input2 function in InputOutput_xxxasm

Bard, Gerstlauer, Valvano, Yerraballi
 TM4C123 I/O Pins
I/O Pin Characteristics Set AFSEL to 0
Can be employed as an n-bit parallel
interface
Pins also provide alternative functions:
 UART Universal asynchronous receiver/transmitter
 SSI Synchronous serial interface
 I2C Inter-integrated circuit
 Timer Periodic interrupts, input capture, and output
compare
 PWM Pulse width modulation
 ADC Analog to digital converter, measure analog
signals
 Analog Compare two analog signals
Comparator
 QEI Quadrature encoder interface Set AFSEL to 1
 USB Universal serial bus
 Ethernet High speed network
 CAN Controller area network
 Analog and Alternate Function
AMSEL =1 PCTL (And DEN = 1)
IO Ain 0 1 2 3 4 5 6 7 8 9 14
PA2 Port SSI0Clk
PA3 Port SSI0Fss
PA4 Port SSI0Rx
PA5 Port SSI0Tx
PA6 Port I2C1SCL M1PWM2
PA7 Port I2C1SDA M1PWM3
PB0 Port U1Rx T2CCP0
PB1 Port U1Tx T2CCP1
PB2 Port I2C0SCL T3CCP0
PB3 Port I2C0SDA T3CCP1
PB4 Ain10 Port SSI2Clk M0PWM2 T1CCP0 CAN0Rx
PB5 Ain11 Port SSI2Fss M0PWM3 T1CCP1 CAN0Tx
PB6 Port SSI2Rx M0PWM0 T0CCP0
PB7 Port SSI2Tx M0PWM1 T0CCP1
PC4 C1- Port U4Rx U1Rx M0PWM6 IDX1 WT0CCP0 U1RTS
PC5 C1+ Port U4Tx U1Tx M0PWM7 PhA1 WT0CCP1 U1CTS
PC6 C0+ Port U3Rx PhB1 WT1CCP0 USB0epen
PC7 C0- Port U3Tx WT1CCP1 USB0pflt
PD0 Ain7 Port SSI3Clk SSI1Clk I2C3SCL M0PWM6 M1PWM0 WT2CCP0
PD1 Ain6 Port SSI3Fss SSI1Fss I2C3SDA M0PWM7 M1PWM1 WT2CCP1
PD2 Ain5 Port SSI3Rx SSI1Rx M0Fault0 WT3CCP0 USB0epen
PD3 Ain4 Port SSI3Tx SSI1Tx IDX0 WT3CCP1 USB0pflt
PD6 Port U2Rx M0Fault0 PhA0 WT5CCP0
PD7 Port U2Tx PhB0 WT5CCP1 NMI
PE0 Ain3 Port U7Rx
PE1 Ain2 Port U7Tx
PE2 Ain1 Port
PE3 Ain0 Port
PE4 Ain9 Port U5Rx I2C2SCL M0PWM4 M1PWM2 CAN0Rx
PE5 Ain8 Port U5Tx I2C2SDA M0PWM5 M1PWM3 CAN0Tx
PF0 Port U1RTS SSI1Rx CAN0Rx M1PWM4 PhA0 T0CCP0 NMI C0o
PF1 Port U1CTS SSI1Tx M1PWM5 PhB0 T0CCP1 C1o TRD1
PF2 Port SSI1Clk M0Fault0 M1PWM6 T1CCP0 TRD0
PF3 Port SSI1Fss CAN0Tx M1PWM7 T1CCP1 TRCLK
PF4 Port M1Fault0 IDX0 T2CCP0 USB0epen